58 // |
58 // |
59 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); |
59 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); |
60 // |
60 // |
61 // rcx and rdx are first and second argument registers on windows |
61 // rcx and rdx are first and second argument registers on windows |
62 |
62 |
63 __ pushq(rbp); |
63 __ push(rbp); |
64 __ movq(rbp, c_rarg0); // cpuid_info address |
64 __ mov(rbp, c_rarg0); // cpuid_info address |
65 __ pushq(rbx); |
65 __ push(rbx); |
66 __ pushq(rsi); |
66 __ push(rsi); |
67 |
67 |
68 // |
68 // |
69 // we have a chip which supports the "cpuid" instruction |
69 // we have a chip which supports the "cpuid" instruction |
70 // |
70 // |
71 __ xorl(rax, rax); |
71 __ xorl(rax, rax); |
72 __ cpuid(); |
72 __ cpuid(); |
73 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); |
73 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); |
74 __ movl(Address(rsi, 0), rax); |
74 __ movl(Address(rsi, 0), rax); |
75 __ movl(Address(rsi, 4), rbx); |
75 __ movl(Address(rsi, 4), rbx); |
76 __ movl(Address(rsi, 8), rcx); |
76 __ movl(Address(rsi, 8), rcx); |
77 __ movl(Address(rsi,12), rdx); |
77 __ movl(Address(rsi,12), rdx); |
78 |
78 |
83 // cpuid(0x4) Deterministic cache params |
83 // cpuid(0x4) Deterministic cache params |
84 // |
84 // |
85 __ movl(rax, 4); |
85 __ movl(rax, 4); |
86 __ xorl(rcx, rcx); // L1 cache |
86 __ xorl(rcx, rcx); // L1 cache |
87 __ cpuid(); |
87 __ cpuid(); |
88 __ pushq(rax); |
88 __ push(rax); |
89 __ andl(rax, 0x1f); // Determine if valid cache parameters used |
89 __ andl(rax, 0x1f); // Determine if valid cache parameters used |
90 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache |
90 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache |
91 __ popq(rax); |
91 __ pop(rax); |
92 __ jccb(Assembler::equal, std_cpuid1); |
92 __ jccb(Assembler::equal, std_cpuid1); |
93 |
93 |
94 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); |
94 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); |
95 __ movl(Address(rsi, 0), rax); |
95 __ movl(Address(rsi, 0), rax); |
96 __ movl(Address(rsi, 4), rbx); |
96 __ movl(Address(rsi, 4), rbx); |
97 __ movl(Address(rsi, 8), rcx); |
97 __ movl(Address(rsi, 8), rcx); |
98 __ movl(Address(rsi,12), rdx); |
98 __ movl(Address(rsi,12), rdx); |
99 |
99 |
101 // Standard cpuid(0x1) |
101 // Standard cpuid(0x1) |
102 // |
102 // |
103 __ bind(std_cpuid1); |
103 __ bind(std_cpuid1); |
104 __ movl(rax, 1); |
104 __ movl(rax, 1); |
105 __ cpuid(); |
105 __ cpuid(); |
106 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
106 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
107 __ movl(Address(rsi, 0), rax); |
107 __ movl(Address(rsi, 0), rax); |
108 __ movl(Address(rsi, 4), rbx); |
108 __ movl(Address(rsi, 4), rbx); |
109 __ movl(Address(rsi, 8), rcx); |
109 __ movl(Address(rsi, 8), rcx); |
110 __ movl(Address(rsi,12), rdx); |
110 __ movl(Address(rsi,12), rdx); |
111 |
111 |
120 // |
120 // |
121 // Extended cpuid(0x80000008) |
121 // Extended cpuid(0x80000008) |
122 // |
122 // |
123 __ movl(rax, 0x80000008); |
123 __ movl(rax, 0x80000008); |
124 __ cpuid(); |
124 __ cpuid(); |
125 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); |
125 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); |
126 __ movl(Address(rsi, 0), rax); |
126 __ movl(Address(rsi, 0), rax); |
127 __ movl(Address(rsi, 4), rbx); |
127 __ movl(Address(rsi, 4), rbx); |
128 __ movl(Address(rsi, 8), rcx); |
128 __ movl(Address(rsi, 8), rcx); |
129 __ movl(Address(rsi,12), rdx); |
129 __ movl(Address(rsi,12), rdx); |
130 |
130 |
132 // Extended cpuid(0x80000005) |
132 // Extended cpuid(0x80000005) |
133 // |
133 // |
134 __ bind(ext_cpuid5); |
134 __ bind(ext_cpuid5); |
135 __ movl(rax, 0x80000005); |
135 __ movl(rax, 0x80000005); |
136 __ cpuid(); |
136 __ cpuid(); |
137 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); |
137 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); |
138 __ movl(Address(rsi, 0), rax); |
138 __ movl(Address(rsi, 0), rax); |
139 __ movl(Address(rsi, 4), rbx); |
139 __ movl(Address(rsi, 4), rbx); |
140 __ movl(Address(rsi, 8), rcx); |
140 __ movl(Address(rsi, 8), rcx); |
141 __ movl(Address(rsi,12), rdx); |
141 __ movl(Address(rsi,12), rdx); |
142 |
142 |
144 // Extended cpuid(0x80000001) |
144 // Extended cpuid(0x80000001) |
145 // |
145 // |
146 __ bind(ext_cpuid1); |
146 __ bind(ext_cpuid1); |
147 __ movl(rax, 0x80000001); |
147 __ movl(rax, 0x80000001); |
148 __ cpuid(); |
148 __ cpuid(); |
149 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); |
149 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); |
150 __ movl(Address(rsi, 0), rax); |
150 __ movl(Address(rsi, 0), rax); |
151 __ movl(Address(rsi, 4), rbx); |
151 __ movl(Address(rsi, 4), rbx); |
152 __ movl(Address(rsi, 8), rcx); |
152 __ movl(Address(rsi, 8), rcx); |
153 __ movl(Address(rsi,12), rdx); |
153 __ movl(Address(rsi,12), rdx); |
154 |
154 |
155 // |
155 // |
156 // return |
156 // return |
157 // |
157 // |
158 __ bind(done); |
158 __ bind(done); |
159 __ popq(rsi); |
159 __ pop(rsi); |
160 __ popq(rbx); |
160 __ pop(rbx); |
161 __ popq(rbp); |
161 __ pop(rbp); |
162 __ ret(0); |
162 __ ret(0); |
163 |
163 |
164 # undef __ |
164 # undef __ |
165 |
165 |
166 return start; |
166 return start; |