1 /*

     2  * Copyright 2003-2008 Sun Microsystems, Inc.  All Rights Reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,

    20  * CA 95054 USA or visit www.sun.com if you need additional information or

    21  * have any questions.

    22  *

    23  */

    24 

    25 #include "incls/_precompiled.incl"

    26 #include "incls/_assembler_x86_64.cpp.incl"

    27 

    28 // Implementation of AddressLiteral

    29 

    30 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {

    31   _is_lval = false;

    32   _target = target;

    33   switch (rtype) {

    34   case relocInfo::oop_type:

    35     // Oops are a special case. Normally they would be their own section

    36     // but in cases like icBuffer they are literals in the code stream that

    37     // we don't have a section for. We use none so that we get a literal address

    38     // which is always patchable.

    39     break;

    40   case relocInfo::external_word_type:

    41     _rspec = external_word_Relocation::spec(target);

    42     break;

    43   case relocInfo::internal_word_type:

    44     _rspec = internal_word_Relocation::spec(target);

    45     break;

    46   case relocInfo::opt_virtual_call_type:

    47     _rspec = opt_virtual_call_Relocation::spec();

    48     break;

    49   case relocInfo::static_call_type:

    50     _rspec = static_call_Relocation::spec();

    51     break;

    52   case relocInfo::runtime_call_type:

    53     _rspec = runtime_call_Relocation::spec();

    54     break;

    55   case relocInfo::none:

    56     break;

    57   default:

    58     ShouldNotReachHere();

    59     break;

    60   }

    61 }

    62 

    63 // Implementation of Address

    64 

    65 Address Address::make_array(ArrayAddress adr) {

    66 #ifdef _LP64

    67   // Not implementable on 64bit machines

    68   // Should have been handled higher up the call chain.

    69   ShouldNotReachHere();

    70   return Address();

    71 #else

    72   AddressLiteral base = adr.base();

    73   Address index = adr.index();

    74   assert(index._disp == 0, "must not have disp"); // maybe it can?

    75   Address array(index._base, index._index, index._scale, (intptr_t) base.target());

    76   array._rspec = base._rspec;

    77   return array;

    78 #endif // _LP64

    79 }

    80 

    81 // exceedingly dangerous constructor

    82 Address::Address(int disp, address loc, relocInfo::relocType rtype) {

    83   _base  = noreg;

    84   _index = noreg;

    85   _scale = no_scale;

    86   _disp  = disp;

    87   switch (rtype) {

    88     case relocInfo::external_word_type:

    89       _rspec = external_word_Relocation::spec(loc);

    90       break;

    91     case relocInfo::internal_word_type:

    92       _rspec = internal_word_Relocation::spec(loc);

    93       break;

    94     case relocInfo::runtime_call_type:

    95       // HMM

    96       _rspec = runtime_call_Relocation::spec();

    97       break;

    98     case relocInfo::none:

    99       break;

   100     default:

   101       ShouldNotReachHere();

   102   }

   103 }

   104 

   105 // Convert the raw encoding form into the form expected by the constructor for

   106 // Address.  An index of 4 (rsp) corresponds to having no index, so convert

   107 // that to noreg for the Address constructor.

   108 Address Address::make_raw(int base, int index, int scale, int disp) {

   109   bool valid_index = index != rsp->encoding();

   110   if (valid_index) {

   111     Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));

   112     return madr;

   113   } else {

   114     Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));

   115     return madr;

   116   }

   117 }

   118 

   119 

   120 // Implementation of Assembler

   121 int AbstractAssembler::code_fill_byte() {

   122   return (u_char)'\xF4'; // hlt

   123 }

   124 

   125 // This should only be used by 64bit instructions that can use rip-relative

   126 // it cannot be used by instructions that want an immediate value.

   127 

   128 bool Assembler::reachable(AddressLiteral adr) {

   129   int64_t disp;

   130 

   131   // None will force a 64bit literal to the code stream. Likely a placeholder

   132   // for something that will be patched later and we need to certain it will

   133   // always be reachable.

   134   if (adr.reloc() == relocInfo::none) {

   135     return false;

   136   }

   137   if (adr.reloc() == relocInfo::internal_word_type) {

   138     // This should be rip relative and easily reachable.

   139     return true;

   140   }

   141   if (adr.reloc() != relocInfo::external_word_type &&

   142       adr.reloc() != relocInfo::runtime_call_type ) {

   143     return false;

   144   }

   145 

   146   // Stress the correction code

   147   if (ForceUnreachable) {

   148     // Must be runtimecall reloc, see if it is in the codecache

   149     // Flipping stuff in the codecache to be unreachable causes issues

   150     // with things like inline caches where the additional instructions

   151     // are not handled.

   152     if (CodeCache::find_blob(adr._target) == NULL) {

   153       return false;

   154     }

   155   }

   156   // For external_word_type/runtime_call_type if it is reachable from where we

   157   // are now (possibly a temp buffer) and where we might end up

   158   // anywhere in the codeCache then we are always reachable.

   159   // This would have to change if we ever save/restore shared code

   160   // to be more pessimistic.

   161 

   162   disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));

   163   if (!is_simm32(disp)) return false;

   164   disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));

   165   if (!is_simm32(disp)) return false;

   166 

   167   disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));

   168 

   169   // Because rip relative is a disp + address_of_next_instruction and we

   170   // don't know the value of address_of_next_instruction we apply a fudge factor

   171   // to make sure we will be ok no matter the size of the instruction we get placed into.

   172   // We don't have to fudge the checks above here because they are already worst case.

   173 

   174   // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal

   175   // + 4 because better safe than sorry.

   176   const int fudge = 12 + 4;

   177   if (disp < 0) {

   178     disp -= fudge;

   179   } else {

   180     disp += fudge;

   181   }

   182   return is_simm32(disp);

   183 }

   184 

   185 

   186 // make this go away eventually

   187 void Assembler::emit_data(jint data,

   188                           relocInfo::relocType rtype,

   189                           int format) {

   190   if (rtype == relocInfo::none) {

   191     emit_long(data);

   192   } else {

   193     emit_data(data, Relocation::spec_simple(rtype), format);

   194   }

   195 }

   196 

   197 void Assembler::emit_data(jint data,

   198                           RelocationHolder const& rspec,

   199                           int format) {

   200   assert(imm64_operand == 0, "default format must be imm64 in this file");

   201   assert(imm64_operand != format, "must not be imm64");

   202   assert(inst_mark() != NULL, "must be inside InstructionMark");

   203   if (rspec.type() !=  relocInfo::none) {

   204     #ifdef ASSERT

   205       check_relocation(rspec, format);

   206     #endif

   207     // Do not use AbstractAssembler::relocate, which is not intended for

   208     // embedded words.  Instead, relocate to the enclosing instruction.

   209 

   210     // hack. call32 is too wide for mask so use disp32

   211     if (format == call32_operand)

   212       code_section()->relocate(inst_mark(), rspec, disp32_operand);

   213     else

   214       code_section()->relocate(inst_mark(), rspec, format);

   215   }

   216   emit_long(data);

   217 }

   218 

   219 void Assembler::emit_data64(jlong data,

   220                             relocInfo::relocType rtype,

   221                             int format) {

   222   if (rtype == relocInfo::none) {

   223     emit_long64(data);

   224   } else {

   225     emit_data64(data, Relocation::spec_simple(rtype), format);

   226   }

   227 }

   228 

   229 void Assembler::emit_data64(jlong data,

   230                             RelocationHolder const& rspec,

   231                             int format) {

   232   assert(imm64_operand == 0, "default format must be imm64 in this file");

   233   assert(imm64_operand == format, "must be imm64");

   234   assert(inst_mark() != NULL, "must be inside InstructionMark");

   235   // Do not use AbstractAssembler::relocate, which is not intended for

   236   // embedded words.  Instead, relocate to the enclosing instruction.

   237   code_section()->relocate(inst_mark(), rspec, format);

   238 #ifdef ASSERT

   239   check_relocation(rspec, format);

   240 #endif

   241   emit_long64(data);

   242 }

   243 

   244 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {

   245   assert(isByte(op1) && isByte(op2), "wrong opcode");

   246   assert(isByte(imm8), "not a byte");

   247   assert((op1 & 0x01) == 0, "should be 8bit operation");

   248   int dstenc = dst->encoding();

   249   if (dstenc >= 8) {

   250     dstenc -= 8;

   251   }

   252   emit_byte(op1);

   253   emit_byte(op2 | dstenc);

   254   emit_byte(imm8);

   255 }

   256 

   257 void Assembler::emit_arith(int op1, int op2, Register dst, int imm32) {

   258   assert(isByte(op1) && isByte(op2), "wrong opcode");

   259   assert((op1 & 0x01) == 1, "should be 32bit operation");

   260   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");

   261   int dstenc = dst->encoding();

   262   if (dstenc >= 8) {

   263     dstenc -= 8;

   264   }

   265   if (is8bit(imm32)) {

   266     emit_byte(op1 | 0x02); // set sign bit

   267     emit_byte(op2 | dstenc);

   268     emit_byte(imm32 & 0xFF);

   269   } else {

   270     emit_byte(op1);

   271     emit_byte(op2 | dstenc);

   272     emit_long(imm32);

   273   }

   274 }

   275 

   276 // immediate-to-memory forms

   277 void Assembler::emit_arith_operand(int op1,

   278                                    Register rm, Address adr,

   279                                    int imm32) {

   280   assert((op1 & 0x01) == 1, "should be 32bit operation");

   281   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");

   282   if (is8bit(imm32)) {

   283     emit_byte(op1 | 0x02); // set sign bit

   284     emit_operand(rm, adr, 1);

   285     emit_byte(imm32 & 0xFF);

   286   } else {

   287     emit_byte(op1);

   288     emit_operand(rm, adr, 4);

   289     emit_long(imm32);

   290   }

   291 }

   292 

   293 

   294 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {

   295   assert(isByte(op1) && isByte(op2), "wrong opcode");

   296   int dstenc = dst->encoding();

   297   int srcenc = src->encoding();

   298   if (dstenc >= 8) {

   299     dstenc -= 8;

   300   }

   301   if (srcenc >= 8) {

   302     srcenc -= 8;

   303   }

   304   emit_byte(op1);

   305   emit_byte(op2 | dstenc << 3 | srcenc);

   306 }

   307 

   308 void Assembler::emit_operand(Register reg, Register base, Register index,

   309                              Address::ScaleFactor scale, int disp,

   310                              RelocationHolder const& rspec,

   311                              int rip_relative_correction) {

   312   relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();

   313   int regenc = reg->encoding();

   314   if (regenc >= 8) {

   315     regenc -= 8;

   316   }

   317   if (base->is_valid()) {

   318     if (index->is_valid()) {

   319       assert(scale != Address::no_scale, "inconsistent address");

   320       int indexenc = index->encoding();

   321       if (indexenc >= 8) {

   322         indexenc -= 8;

   323       }

   324       int baseenc = base->encoding();

   325       if (baseenc >= 8) {

   326         baseenc -= 8;

   327       }

   328       // [base + index*scale + disp]

   329       if (disp == 0 && rtype == relocInfo::none  &&

   330           base != rbp && base != r13) {

   331         // [base + index*scale]

   332         // [00 reg 100][ss index base]

   333         assert(index != rsp, "illegal addressing mode");

   334         emit_byte(0x04 | regenc << 3);

   335         emit_byte(scale << 6 | indexenc << 3 | baseenc);

   336       } else if (is8bit(disp) && rtype == relocInfo::none) {

   337         // [base + index*scale + imm8]

   338         // [01 reg 100][ss index base] imm8

   339         assert(index != rsp, "illegal addressing mode");

   340         emit_byte(0x44 | regenc << 3);

   341         emit_byte(scale << 6 | indexenc << 3 | baseenc);

   342         emit_byte(disp & 0xFF);

   343       } else {

   344         // [base + index*scale + disp32]

   345         // [10 reg 100][ss index base] disp32

   346         assert(index != rsp, "illegal addressing mode");

   347         emit_byte(0x84 | regenc << 3);

   348         emit_byte(scale << 6 | indexenc << 3 | baseenc);

   349         emit_data(disp, rspec, disp32_operand);

   350       }

   351     } else if (base == rsp || base == r12) {

   352       // [rsp + disp]

   353       if (disp == 0 && rtype == relocInfo::none) {

   354         // [rsp]

   355         // [00 reg 100][00 100 100]

   356         emit_byte(0x04 | regenc << 3);

   357         emit_byte(0x24);

   358       } else if (is8bit(disp) && rtype == relocInfo::none) {

   359         // [rsp + imm8]

   360         // [01 reg 100][00 100 100] disp8

   361         emit_byte(0x44 | regenc << 3);

   362         emit_byte(0x24);

   363         emit_byte(disp & 0xFF);

   364       } else {

   365         // [rsp + imm32]

   366         // [10 reg 100][00 100 100] disp32

   367         emit_byte(0x84 | regenc << 3);

   368         emit_byte(0x24);

   369         emit_data(disp, rspec, disp32_operand);

   370       }

   371     } else {

   372       // [base + disp]

   373       assert(base != rsp && base != r12, "illegal addressing mode");

   374       int baseenc = base->encoding();

   375       if (baseenc >= 8) {

   376         baseenc -= 8;

   377       }

   378       if (disp == 0 && rtype == relocInfo::none &&

   379           base != rbp && base != r13) {

   380         // [base]

   381         // [00 reg base]

   382         emit_byte(0x00 | regenc << 3 | baseenc);

   383       } else if (is8bit(disp) && rtype == relocInfo::none) {

   384         // [base + disp8]

   385         // [01 reg base] disp8

   386         emit_byte(0x40 | regenc << 3 | baseenc);

   387         emit_byte(disp & 0xFF);

   388       } else {

   389         // [base + disp32]

   390         // [10 reg base] disp32

   391         emit_byte(0x80 | regenc << 3 | baseenc);

   392         emit_data(disp, rspec, disp32_operand);

   393       }

   394     }

   395   } else {

   396     if (index->is_valid()) {

   397       assert(scale != Address::no_scale, "inconsistent address");

   398       int indexenc = index->encoding();

   399       if (indexenc >= 8) {

   400         indexenc -= 8;

   401       }

   402       // [index*scale + disp]

   403       // [00 reg 100][ss index 101] disp32

   404       assert(index != rsp, "illegal addressing mode");

   405       emit_byte(0x04 | regenc << 3);

   406       emit_byte(scale << 6 | indexenc << 3 | 0x05);

   407       emit_data(disp, rspec, disp32_operand);

   408 #ifdef _LP64

   409     } else if (rtype != relocInfo::none ) {

   410       // [disp] RIP-RELATIVE

   411       // [00 000 101] disp32

   412 

   413       emit_byte(0x05 | regenc << 3);

   414       // Note that the RIP-rel. correction applies to the generated

   415       // disp field, but _not_ to the target address in the rspec.

   416 

   417       // disp was created by converting the target address minus the pc

   418       // at the start of the instruction. That needs more correction here.

   419       // intptr_t disp = target - next_ip;

   420       assert(inst_mark() != NULL, "must be inside InstructionMark");

   421       address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;

   422       int64_t adjusted = (int64_t) disp -  (next_ip - inst_mark());

   423       assert(is_simm32(adjusted),

   424              "must be 32bit offset (RIP relative address)");

   425       emit_data((int) adjusted, rspec, disp32_operand);

   426 

   427 #endif // _LP64

   428     } else {

   429       // [disp] ABSOLUTE

   430       // [00 reg 100][00 100 101] disp32

   431       emit_byte(0x04 | regenc << 3);

   432       emit_byte(0x25);

   433       emit_data(disp, rspec, disp32_operand);

   434     }

   435   }

   436 }

   437 

   438 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,

   439                              Address::ScaleFactor scale, int disp,

   440                              RelocationHolder const& rspec,

   441                              int rip_relative_correction) {

   442   relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();

   443   int regenc = reg->encoding();

   444   if (regenc >= 8) {

   445     regenc -= 8;

   446   }

   447   if (base->is_valid()) {

   448     if (index->is_valid()) {

   449       assert(scale != Address::no_scale, "inconsistent address");

   450       int indexenc = index->encoding();

   451       if (indexenc >= 8) {

   452         indexenc -= 8;

   453       }

   454       int baseenc = base->encoding();

   455       if (baseenc >= 8) {

   456         baseenc -= 8;

   457       }

   458       // [base + index*scale + disp]

   459       if (disp == 0 && rtype == relocInfo::none  &&

   460           base != rbp && base != r13) {

   461         // [base + index*scale]

   462         // [00 reg 100][ss index base]

   463         assert(index != rsp, "illegal addressing mode");

   464         emit_byte(0x04 | regenc << 3);

   465         emit_byte(scale << 6 | indexenc << 3 | baseenc);

   466       } else if (is8bit(disp) && rtype == relocInfo::none) {

   467         // [base + index*scale + disp8]

   468         // [01 reg 100][ss index base] disp8

   469         assert(index != rsp, "illegal addressing mode");

   470         emit_byte(0x44 | regenc << 3);

   471         emit_byte(scale << 6 | indexenc << 3 | baseenc);

   472         emit_byte(disp & 0xFF);

   473       } else {

   474         // [base + index*scale + disp32]

   475         // [10 reg 100][ss index base] disp32

   476         assert(index != rsp, "illegal addressing mode");

   477         emit_byte(0x84 | regenc << 3);

   478         emit_byte(scale << 6 | indexenc << 3 | baseenc);

   479         emit_data(disp, rspec, disp32_operand);

   480       }

   481     } else if (base == rsp || base == r12) {

   482       // [rsp + disp]

   483       if (disp == 0 && rtype == relocInfo::none) {

   484         // [rsp]

   485         // [00 reg 100][00 100 100]

   486         emit_byte(0x04 | regenc << 3);

   487         emit_byte(0x24);

   488       } else if (is8bit(disp) && rtype == relocInfo::none) {

   489         // [rsp + imm8]

   490         // [01 reg 100][00 100 100] disp8

   491         emit_byte(0x44 | regenc << 3);

   492         emit_byte(0x24);

   493         emit_byte(disp & 0xFF);

   494       } else {

   495         // [rsp + imm32]

   496         // [10 reg 100][00 100 100] disp32

   497         emit_byte(0x84 | regenc << 3);

   498         emit_byte(0x24);

   499         emit_data(disp, rspec, disp32_operand);

   500       }

   501     } else {

   502       // [base + disp]

   503       assert(base != rsp && base != r12, "illegal addressing mode");

   504       int baseenc = base->encoding();

   505       if (baseenc >= 8) {

   506         baseenc -= 8;

   507       }

   508       if (disp == 0 && rtype == relocInfo::none &&

   509           base != rbp && base != r13) {

   510         // [base]

   511         // [00 reg base]

   512         emit_byte(0x00 | regenc << 3 | baseenc);

   513       } else if (is8bit(disp) && rtype == relocInfo::none) {

   514         // [base + imm8]

   515         // [01 reg base] disp8

   516         emit_byte(0x40 | regenc << 3 | baseenc);

   517         emit_byte(disp & 0xFF);

   518       } else {

   519         // [base + imm32]

   520         // [10 reg base] disp32

   521         emit_byte(0x80 | regenc << 3 | baseenc);

   522         emit_data(disp, rspec, disp32_operand);

   523       }

   524     }

   525   } else {

   526     if (index->is_valid()) {

   527       assert(scale != Address::no_scale, "inconsistent address");

   528       int indexenc = index->encoding();

   529       if (indexenc >= 8) {

   530         indexenc -= 8;

   531       }

   532       // [index*scale + disp]

   533       // [00 reg 100][ss index 101] disp32

   534       assert(index != rsp, "illegal addressing mode");

   535       emit_byte(0x04 | regenc << 3);

   536       emit_byte(scale << 6 | indexenc << 3 | 0x05);

   537       emit_data(disp, rspec, disp32_operand);

   538 #ifdef _LP64

   539     } else if ( rtype != relocInfo::none ) {

   540       // [disp] RIP-RELATIVE

   541       // [00 reg 101] disp32

   542       emit_byte(0x05 | regenc << 3);

   543       // Note that the RIP-rel. correction applies to the generated

   544       // disp field, but _not_ to the target address in the rspec.

   545 

   546       // disp was created by converting the target address minus the pc

   547       // at the start of the instruction. That needs more correction here.

   548       // intptr_t disp = target - next_ip;

   549 

   550       assert(inst_mark() != NULL, "must be inside InstructionMark");

   551       address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;

   552 

   553       int64_t adjusted = (int64_t) disp -  (next_ip - inst_mark());

   554       assert(is_simm32(adjusted),

   555              "must be 32bit offset (RIP relative address)");

   556       emit_data((int) adjusted, rspec, disp32_operand);

   557 #endif // _LP64

   558     } else {

   559       // [disp] ABSOLUTE

   560       // [00 reg 100][00 100 101] disp32

   561       emit_byte(0x04 | regenc << 3);

   562       emit_byte(0x25);

   563       emit_data(disp, rspec, disp32_operand);

   564     }

   565   }

   566 }

   567 

   568 // Secret local extension to Assembler::WhichOperand:

   569 #define end_pc_operand (_WhichOperand_limit)

   570 

   571 address Assembler::locate_operand(address inst, WhichOperand which) {

   572   // Decode the given instruction, and return the address of

   573   // an embedded 32-bit operand word.

   574 

   575   // If "which" is disp32_operand, selects the displacement portion

   576   // of an effective address specifier.

   577   // If "which" is imm64_operand, selects the trailing immediate constant.

   578   // If "which" is call32_operand, selects the displacement of a call or jump.

   579   // Caller is responsible for ensuring that there is such an operand,

   580   // and that it is 32/64 bits wide.

   581 

   582   // If "which" is end_pc_operand, find the end of the instruction.

   583 

   584   address ip = inst;

   585   bool is_64bit = false;

   586 

   587   debug_only(bool has_disp32 = false);

   588   int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn

   589 

   590   again_after_prefix:

   591   switch (0xFF & *ip++) {

   592 

   593   // These convenience macros generate groups of "case" labels for the switch.

   594 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3

   595 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \

   596              case (x)+4: case (x)+5: case (x)+6: case (x)+7

   597 #define REP16(x) REP8((x)+0): \

   598               case REP8((x)+8)

   599 

   600   case CS_segment:

   601   case SS_segment:

   602   case DS_segment:

   603   case ES_segment:

   604   case FS_segment:

   605   case GS_segment:

   606     assert(0, "shouldn't have that prefix");

   607     assert(ip == inst + 1 || ip == inst + 2, "only two prefixes allowed");

   608     goto again_after_prefix;

   609 

   610   case 0x67:

   611   case REX:

   612   case REX_B:

   613   case REX_X:

   614   case REX_XB:

   615   case REX_R:

   616   case REX_RB:

   617   case REX_RX:

   618   case REX_RXB:

   619 //     assert(ip == inst + 1, "only one prefix allowed");

   620     goto again_after_prefix;

   621 

   622   case REX_W:

   623   case REX_WB:

   624   case REX_WX:

   625   case REX_WXB:

   626   case REX_WR:

   627   case REX_WRB:

   628   case REX_WRX:

   629   case REX_WRXB:

   630     is_64bit = true;

   631 //     assert(ip == inst + 1, "only one prefix allowed");

   632     goto again_after_prefix;

   633 

   634   case 0xFF: // pushq a; decl a; incl a; call a; jmp a

   635   case 0x88: // movb a, r

   636   case 0x89: // movl a, r

   637   case 0x8A: // movb r, a

   638   case 0x8B: // movl r, a

   639   case 0x8F: // popl a

   640     debug_only(has_disp32 = true;)

   641     break;

   642 

   643   case 0x68: // pushq #32

   644     if (which == end_pc_operand) {

   645       return ip + 4;

   646     }

   647     assert(0, "pushq has no disp32 or imm64");

   648     ShouldNotReachHere();

   649 

   650   case 0x66: // movw ... (size prefix)

   651     again_after_size_prefix2:

   652     switch (0xFF & *ip++) {

   653     case REX:

   654     case REX_B:

   655     case REX_X:

   656     case REX_XB:

   657     case REX_R:

   658     case REX_RB:

   659     case REX_RX:

   660     case REX_RXB:

   661     case REX_W:

   662     case REX_WB:

   663     case REX_WX:

   664     case REX_WXB:

   665     case REX_WR:

   666     case REX_WRB:

   667     case REX_WRX:

   668     case REX_WRXB:

   669       goto again_after_size_prefix2;

   670     case 0x8B: // movw r, a

   671     case 0x89: // movw a, r

   672       break;

   673     case 0xC7: // movw a, #16

   674       tail_size = 2;  // the imm16

   675       break;

   676     case 0x0F: // several SSE/SSE2 variants

   677       ip--;    // reparse the 0x0F

   678       goto again_after_prefix;

   679     default:

   680       ShouldNotReachHere();

   681     }

   682     break;

   683 

   684   case REP8(0xB8): // movl/q r, #32/#64(oop?)

   685     if (which == end_pc_operand)  return ip + (is_64bit ? 8 : 4);

   686     assert((which == call32_operand || which == imm64_operand) && is_64bit ||

   687            which == narrow_oop_operand && !is_64bit, "");

   688     return ip;

   689 

   690   case 0x69: // imul r, a, #32

   691   case 0xC7: // movl a, #32(oop?)

   692     tail_size = 4;

   693     debug_only(has_disp32 = true); // has both kinds of operands!

   694     break;

   695 

   696   case 0x0F: // movx..., etc.

   697     switch (0xFF & *ip++) {

   698     case 0x12: // movlps

   699     case 0x28: // movaps

   700     case 0x2E: // ucomiss

   701     case 0x2F: // comiss

   702     case 0x54: // andps

   703     case 0x57: // xorps

   704     case 0x6E: // movd

   705     case 0x7E: // movd

   706     case 0xAE: // ldmxcsr   a

   707       debug_only(has_disp32 = true); // has both kinds of operands!

   708       break;

   709     case 0xAD: // shrd r, a, %cl

   710     case 0xAF: // imul r, a

   711     case 0xBE: // movsbl r, a

   712     case 0xBF: // movswl r, a

   713     case 0xB6: // movzbl r, a

   714     case 0xB7: // movzwl r, a

   715     case REP16(0x40): // cmovl cc, r, a

   716     case 0xB0: // cmpxchgb

   717     case 0xB1: // cmpxchg

   718     case 0xC1: // xaddl

   719     case 0xC7: // cmpxchg8

   720     case REP16(0x90): // setcc a

   721       debug_only(has_disp32 = true);

   722       // fall out of the switch to decode the address

   723       break;

   724     case 0xAC: // shrd r, a, #8

   725       debug_only(has_disp32 = true);

   726       tail_size = 1;  // the imm8

   727       break;

   728     case REP16(0x80): // jcc rdisp32

   729       if (which == end_pc_operand)  return ip + 4;

   730       assert(which == call32_operand, "jcc has no disp32 or imm64");

   731       return ip;

   732     default:

   733       ShouldNotReachHere();

   734     }

   735     break;

   736 

   737   case 0x81: // addl a, #32; addl r, #32

   738     // also: orl, adcl, sbbl, andl, subl, xorl, cmpl

   739     tail_size = 4;

   740     debug_only(has_disp32 = true); // has both kinds of operands!

   741     break;

   742 

   743   case 0x83: // addl a, #8; addl r, #8

   744     // also: orl, adcl, sbbl, andl, subl, xorl, cmpl

   745     debug_only(has_disp32 = true); // has both kinds of operands!

   746     tail_size = 1;

   747     break;

   748 

   749   case 0x9B:

   750     switch (0xFF & *ip++) {

   751     case 0xD9: // fnstcw a

   752       debug_only(has_disp32 = true);

   753       break;

   754     default:

   755       ShouldNotReachHere();

   756     }

   757     break;

   758 

   759   case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a

   760   case REP4(0x10): // adc...

   761   case REP4(0x20): // and...

   762   case REP4(0x30): // xor...

   763   case REP4(0x08): // or...

   764   case REP4(0x18): // sbb...

   765   case REP4(0x28): // sub...

   766   case 0xF7: // mull a

   767   case 0x87: // xchg r, a

   768     debug_only(has_disp32 = true);

   769     break;

   770   case REP4(0x38): // cmp...

   771   case 0x8D: // lea r, a

   772   case 0x85: // test r, a

   773     debug_only(has_disp32 = true); // has both kinds of operands!

   774     break;

   775 

   776   case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8

   777   case 0xC6: // movb a, #8

   778   case 0x80: // cmpb a, #8

   779   case 0x6B: // imul r, a, #8

   780     debug_only(has_disp32 = true); // has both kinds of operands!

   781     tail_size = 1; // the imm8

   782     break;

   783 

   784   case 0xE8: // call rdisp32

   785   case 0xE9: // jmp  rdisp32

   786     if (which == end_pc_operand)  return ip + 4;

   787     assert(which == call32_operand, "call has no disp32 or imm32");

   788     return ip;

   789 

   790   case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1

   791   case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl

   792   case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a

   793   case 0xDD: // fld_d a; fst_d a; fstp_d a

   794   case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a

   795   case 0xDF: // fild_d a; fistp_d a

   796   case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a

   797   case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a

   798   case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a

   799     debug_only(has_disp32 = true);

   800     break;

   801 

   802   case 0xF3:                    // For SSE

   803   case 0xF2:                    // For SSE2

   804     switch (0xFF & *ip++) {

   805     case REX:

   806     case REX_B:

   807     case REX_X:

   808     case REX_XB:

   809     case REX_R:

   810     case REX_RB:

   811     case REX_RX:

   812     case REX_RXB:

   813     case REX_W:

   814     case REX_WB:

   815     case REX_WX:

   816     case REX_WXB:

   817     case REX_WR:

   818     case REX_WRB:

   819     case REX_WRX:

   820     case REX_WRXB:

   821       ip++;

   822     default:

   823       ip++;

   824     }

   825     debug_only(has_disp32 = true); // has both kinds of operands!

   826     break;

   827 

   828   default:

   829     ShouldNotReachHere();

   830 

   831 #undef REP8

   832 #undef REP16

   833   }

   834 

   835   assert(which != call32_operand, "instruction is not a call, jmp, or jcc");

   836   assert(which != imm64_operand, "instruction is not a movq reg, imm64");

   837   assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");

   838 

   839   // parse the output of emit_operand

   840   int op2 = 0xFF & *ip++;

   841   int base = op2 & 0x07;

   842   int op3 = -1;

   843   const int b100 = 4;

   844   const int b101 = 5;

   845   if (base == b100 && (op2 >> 6) != 3) {

   846     op3 = 0xFF & *ip++;

   847     base = op3 & 0x07;   // refetch the base

   848   }

   849   // now ip points at the disp (if any)

   850 

   851   switch (op2 >> 6) {

   852   case 0:

   853     // [00 reg  100][ss index base]

   854     // [00 reg  100][00   100  esp]

   855     // [00 reg base]

   856     // [00 reg  100][ss index  101][disp32]

   857     // [00 reg  101]               [disp32]

   858 

   859     if (base == b101) {

   860       if (which == disp32_operand)

   861         return ip;              // caller wants the disp32

   862       ip += 4;                  // skip the disp32

   863     }

   864     break;

   865 

   866   case 1:

   867     // [01 reg  100][ss index base][disp8]

   868     // [01 reg  100][00   100  esp][disp8]

   869     // [01 reg base]               [disp8]

   870     ip += 1;                    // skip the disp8

   871     break;

   872 

   873   case 2:

   874     // [10 reg  100][ss index base][disp32]

   875     // [10 reg  100][00   100  esp][disp32]

   876     // [10 reg base]               [disp32]

   877     if (which == disp32_operand)

   878       return ip;                // caller wants the disp32

   879     ip += 4;                    // skip the disp32

   880     break;

   881 

   882   case 3:

   883     // [11 reg base]  (not a memory addressing mode)

   884     break;

   885   }

   886 

   887   if (which == end_pc_operand) {

   888     return ip + tail_size;

   889   }

   890 

   891   assert(0, "fix locate_operand");

   892   return ip;

   893 }

   894 

   895 address Assembler::locate_next_instruction(address inst) {

   896   // Secretly share code with locate_operand:

   897   return locate_operand(inst, end_pc_operand);

   898 }

   899 

   900 #ifdef ASSERT

   901 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {

   902   address inst = inst_mark();

   903   assert(inst != NULL && inst < pc(),

   904          "must point to beginning of instruction");

   905   address opnd;

   906 

   907   Relocation* r = rspec.reloc();

   908   if (r->type() == relocInfo::none) {

   909     return;

   910   } else if (r->is_call() || format == call32_operand) {

   911     opnd = locate_operand(inst, call32_operand);

   912   } else if (r->is_data()) {

   913     assert(format == imm64_operand || format == disp32_operand ||

   914            format == narrow_oop_operand, "format ok");

   915     opnd = locate_operand(inst, (WhichOperand) format);

   916   } else {

   917     assert(format == 0, "cannot specify a format");

   918     return;

   919   }

   920   assert(opnd == pc(), "must put operand where relocs can find it");

   921 }

   922 #endif

   923 

   924 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {

   925   if (reg_enc >= 8) {

   926     prefix(REX_B);

   927     reg_enc -= 8;

   928   } else if (byteinst && reg_enc >= 4) {

   929     prefix(REX);

   930   }

   931   return reg_enc;

   932 }

   933 

   934 int Assembler::prefixq_and_encode(int reg_enc) {

   935   if (reg_enc < 8) {

   936     prefix(REX_W);

   937   } else {

   938     prefix(REX_WB);

   939     reg_enc -= 8;

   940   }

   941   return reg_enc;

   942 }

   943 

   944 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {

   945   if (dst_enc < 8) {

   946     if (src_enc >= 8) {

   947       prefix(REX_B);

   948       src_enc -= 8;

   949     } else if (byteinst && src_enc >= 4) {

   950       prefix(REX);

   951     }

   952   } else {

   953     if (src_enc < 8) {

   954       prefix(REX_R);

   955     } else {

   956       prefix(REX_RB);

   957       src_enc -= 8;

   958     }

   959     dst_enc -= 8;

   960   }

   961   return dst_enc << 3 | src_enc;

   962 }

   963 

   964 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {

   965   if (dst_enc < 8) {

   966     if (src_enc < 8) {

   967       prefix(REX_W);

   968     } else {

   969       prefix(REX_WB);

   970       src_enc -= 8;

   971     }

   972   } else {

   973     if (src_enc < 8) {

   974       prefix(REX_WR);

   975     } else {

   976       prefix(REX_WRB);

   977       src_enc -= 8;

   978     }

   979     dst_enc -= 8;

   980   }

   981   return dst_enc << 3 | src_enc;

   982 }

   983 

   984 void Assembler::prefix(Register reg) {

   985   if (reg->encoding() >= 8) {

   986     prefix(REX_B);

   987   }

   988 }

   989 

   990 void Assembler::prefix(Address adr) {

   991   if (adr.base_needs_rex()) {

   992     if (adr.index_needs_rex()) {

   993       prefix(REX_XB);

   994     } else {

   995       prefix(REX_B);

   996     }

   997   } else {

   998     if (adr.index_needs_rex()) {

   999       prefix(REX_X);

  1000     }

  1001   }

  1002 }

  1003 

  1004 void Assembler::prefixq(Address adr) {

  1005   if (adr.base_needs_rex()) {

  1006     if (adr.index_needs_rex()) {

  1007       prefix(REX_WXB);

  1008     } else {

  1009       prefix(REX_WB);

  1010     }

  1011   } else {

  1012     if (adr.index_needs_rex()) {

  1013       prefix(REX_WX);

  1014     } else {

  1015       prefix(REX_W);

  1016     }

  1017   }

  1018 }

  1019 

  1020 

  1021 void Assembler::prefix(Address adr, Register reg, bool byteinst) {

  1022   if (reg->encoding() < 8) {

  1023     if (adr.base_needs_rex()) {

  1024       if (adr.index_needs_rex()) {

  1025         prefix(REX_XB);

  1026       } else {

  1027         prefix(REX_B);

  1028       }

  1029     } else {

  1030       if (adr.index_needs_rex()) {

  1031         prefix(REX_X);

  1032       } else if (reg->encoding() >= 4 ) {

  1033         prefix(REX);

  1034       }

  1035     }

  1036   } else {

  1037     if (adr.base_needs_rex()) {

  1038       if (adr.index_needs_rex()) {

  1039         prefix(REX_RXB);

  1040       } else {

  1041         prefix(REX_RB);

  1042       }

  1043     } else {

  1044       if (adr.index_needs_rex()) {

  1045         prefix(REX_RX);

  1046       } else {

  1047         prefix(REX_R);

  1048       }

  1049     }

  1050   }

  1051 }

  1052 

  1053 void Assembler::prefixq(Address adr, Register src) {

  1054   if (src->encoding() < 8) {

  1055     if (adr.base_needs_rex()) {

  1056       if (adr.index_needs_rex()) {

  1057         prefix(REX_WXB);

  1058       } else {

  1059         prefix(REX_WB);

  1060       }

  1061     } else {

  1062       if (adr.index_needs_rex()) {

  1063         prefix(REX_WX);

  1064       } else {

  1065         prefix(REX_W);

  1066       }

  1067     }

  1068   } else {

  1069     if (adr.base_needs_rex()) {

  1070       if (adr.index_needs_rex()) {

  1071         prefix(REX_WRXB);

  1072       } else {

  1073         prefix(REX_WRB);

  1074       }

  1075     } else {

  1076       if (adr.index_needs_rex()) {

  1077         prefix(REX_WRX);

  1078       } else {

  1079         prefix(REX_WR);

  1080       }

  1081     }

  1082   }

  1083 }

  1084 

  1085 void Assembler::prefix(Address adr, XMMRegister reg) {

  1086   if (reg->encoding() < 8) {

  1087     if (adr.base_needs_rex()) {

  1088       if (adr.index_needs_rex()) {

  1089         prefix(REX_XB);

  1090       } else {

  1091         prefix(REX_B);

  1092       }

  1093     } else {

  1094       if (adr.index_needs_rex()) {

  1095         prefix(REX_X);

  1096       }

  1097     }

  1098   } else {

  1099     if (adr.base_needs_rex()) {

  1100       if (adr.index_needs_rex()) {

  1101         prefix(REX_RXB);

  1102       } else {

  1103         prefix(REX_RB);

  1104       }

  1105     } else {

  1106       if (adr.index_needs_rex()) {

  1107         prefix(REX_RX);

  1108       } else {

  1109         prefix(REX_R);

  1110       }

  1111     }

  1112   }

  1113 }

  1114 

  1115 void Assembler::emit_operand(Register reg, Address adr,

  1116                              int rip_relative_correction) {

  1117   emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,

  1118                adr._rspec,

  1119                rip_relative_correction);

  1120 }

  1121 

  1122 void Assembler::emit_operand(XMMRegister reg, Address adr,

  1123                              int rip_relative_correction) {

  1124   emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,

  1125                adr._rspec,

  1126                rip_relative_correction);

  1127 }

  1128 

  1129 void Assembler::emit_farith(int b1, int b2, int i) {

  1130   assert(isByte(b1) && isByte(b2), "wrong opcode");

  1131   assert(0 <= i &&  i < 8, "illegal stack offset");

  1132   emit_byte(b1);

  1133   emit_byte(b2 + i);

  1134 }

  1135