1179 Node* out_ctrl = new_lb->proj_out(LoadBarrierNode::Control); |
1179 Node* out_ctrl = new_lb->proj_out(LoadBarrierNode::Control); |
1180 |
1180 |
1181 if (is_strip_mined && (i == LoopNode::EntryControl)) { |
1181 if (is_strip_mined && (i == LoopNode::EntryControl)) { |
1182 assert(region->in(i)->is_OuterStripMinedLoop(), ""); |
1182 assert(region->in(i)->is_OuterStripMinedLoop(), ""); |
1183 igvn.replace_input_of(region->in(i), i, out_ctrl); |
1183 igvn.replace_input_of(region->in(i), i, out_ctrl); |
|
1184 phase->set_idom(region->in(i), out_ctrl, phase->dom_depth(out_ctrl)); |
1184 } else if (ctrl == region->in(i)) { |
1185 } else if (ctrl == region->in(i)) { |
1185 igvn.replace_input_of(region, i, out_ctrl); |
1186 igvn.replace_input_of(region, i, out_ctrl); |
|
1187 // Only update the idom if is the loop entry we are updating |
|
1188 // - A loop backedge doesn't change the idom |
|
1189 if (region->is_Loop() && i == LoopNode::EntryControl) { |
|
1190 phase->set_idom(region, out_ctrl, phase->dom_depth(out_ctrl)); |
|
1191 } |
1186 } else { |
1192 } else { |
1187 Node* iff = region->in(i)->in(0); |
1193 Node* iff = region->in(i)->in(0); |
1188 igvn.replace_input_of(iff, 0, out_ctrl); |
1194 igvn.replace_input_of(iff, 0, out_ctrl); |
1189 phase->set_idom(iff, out_ctrl, phase->dom_depth(out_ctrl)+1); |
1195 phase->set_idom(iff, out_ctrl, phase->dom_depth(out_ctrl)+1); |
1190 } |
1196 } |