228 |
228 |
229 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
229 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
230 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
230 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
231 |
231 |
232 char buf[512]; |
232 char buf[512]; |
233 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
233 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
234 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), |
234 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), |
235 (has_hardware_popc() ? ", popc" : ""), |
235 (has_hardware_popc() ? ", popc" : ""), |
236 (has_vis1() ? ", vis1" : ""), |
236 (has_vis1() ? ", vis1" : ""), |
237 (has_vis2() ? ", vis2" : ""), |
237 (has_vis2() ? ", vis2" : ""), |
238 (has_vis3() ? ", vis3" : ""), |
238 (has_vis3() ? ", vis3" : ""), |
240 (has_cbcond() ? ", cbcond" : ""), |
240 (has_cbcond() ? ", cbcond" : ""), |
241 (has_aes() ? ", aes" : ""), |
241 (has_aes() ? ", aes" : ""), |
242 (has_sha1() ? ", sha1" : ""), |
242 (has_sha1() ? ", sha1" : ""), |
243 (has_sha256() ? ", sha256" : ""), |
243 (has_sha256() ? ", sha256" : ""), |
244 (has_sha512() ? ", sha512" : ""), |
244 (has_sha512() ? ", sha512" : ""), |
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245 (has_crc32c() ? ", crc32c" : ""), |
245 (is_ultra3() ? ", ultra3" : ""), |
246 (is_ultra3() ? ", ultra3" : ""), |
246 (is_sun4v() ? ", sun4v" : ""), |
247 (is_sun4v() ? ", sun4v" : ""), |
247 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), |
248 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), |
248 (is_sparc64() ? ", sparc64" : ""), |
249 (is_sparc64() ? ", sparc64" : ""), |
249 (!has_hardware_mul32() ? ", no-mul32" : ""), |
250 (!has_hardware_mul32() ? ", no-mul32" : ""), |
361 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { |
362 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { |
362 FLAG_SET_DEFAULT(UseSHA, false); |
363 FLAG_SET_DEFAULT(UseSHA, false); |
363 } |
364 } |
364 } |
365 } |
365 |
366 |
|
367 // SPARC T4 and above should have support for CRC32C instruction |
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368 if (has_crc32c()) { |
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369 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions |
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370 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { |
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371 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); |
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372 } |
|
373 } else { |
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374 if (UseCRC32CIntrinsics) { |
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375 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled."); |
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376 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); |
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377 } |
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378 } |
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379 } else if (UseCRC32CIntrinsics) { |
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380 warning("CRC32C instruction is not available on this CPU"); |
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381 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); |
|
382 } |
|
383 |
366 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
384 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
367 (cache_line_size > ContendedPaddingWidth)) |
385 (cache_line_size > ContendedPaddingWidth)) |
368 ContendedPaddingWidth = cache_line_size; |
386 ContendedPaddingWidth = cache_line_size; |
369 |
387 |
370 // This machine does not allow unaligned memory accesses |
388 // This machine does not allow unaligned memory accesses |