73 |
73 |
74 tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score()); |
74 tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score()); |
75 // Flags |
75 // Flags |
76 if( _is_oop ) tty->print("Oop "); |
76 if( _is_oop ) tty->print("Oop "); |
77 if( _is_float ) tty->print("Float "); |
77 if( _is_float ) tty->print("Float "); |
|
78 if( _is_vector ) tty->print("Vector "); |
78 if( _was_spilled1 ) tty->print("Spilled "); |
79 if( _was_spilled1 ) tty->print("Spilled "); |
79 if( _was_spilled2 ) tty->print("Spilled2 "); |
80 if( _was_spilled2 ) tty->print("Spilled2 "); |
80 if( _direct_conflict ) tty->print("Direct_conflict "); |
81 if( _direct_conflict ) tty->print("Direct_conflict "); |
81 if( _fat_proj ) tty->print("Fat "); |
82 if( _fat_proj ) tty->print("Fat "); |
82 if( _was_lo ) tty->print("Lo "); |
83 if( _was_lo ) tty->print("Lo "); |
477 |
478 |
478 NOT_PRODUCT( C->verify_graph_edges(); ) |
479 NOT_PRODUCT( C->verify_graph_edges(); ) |
479 |
480 |
480 // Move important info out of the live_arena to longer lasting storage. |
481 // Move important info out of the live_arena to longer lasting storage. |
481 alloc_node_regs(_names.Size()); |
482 alloc_node_regs(_names.Size()); |
482 for( uint i=0; i < _names.Size(); i++ ) { |
483 for (uint i=0; i < _names.Size(); i++) { |
483 if( _names[i] ) { // Live range associated with Node? |
484 if (_names[i]) { // Live range associated with Node? |
484 LRG &lrg = lrgs( _names[i] ); |
485 LRG &lrg = lrgs(_names[i]); |
485 if( lrg.num_regs() == 1 ) { |
486 if (!lrg.alive()) { |
486 _node_regs[i].set1( lrg.reg() ); |
487 _node_regs[i].set_bad(); |
|
488 } else if (lrg.num_regs() == 1) { |
|
489 _node_regs[i].set1(lrg.reg()); |
487 } else { // Must be a register-pair |
490 } else { // Must be a register-pair |
488 if( !lrg._fat_proj ) { // Must be aligned adjacent register pair |
491 if (!lrg._fat_proj) { // Must be aligned adjacent register pair |
489 // Live ranges record the highest register in their mask. |
492 // Live ranges record the highest register in their mask. |
490 // We want the low register for the AD file writer's convenience. |
493 // We want the low register for the AD file writer's convenience. |
491 _node_regs[i].set2( OptoReg::add(lrg.reg(),-1) ); |
494 _node_regs[i].set2( OptoReg::add(lrg.reg(),(1-lrg.num_regs())) ); |
492 } else { // Misaligned; extract 2 bits |
495 } else { // Misaligned; extract 2 bits |
493 OptoReg::Name hi = lrg.reg(); // Get hi register |
496 OptoReg::Name hi = lrg.reg(); // Get hi register |
494 lrg.Remove(hi); // Yank from mask |
497 lrg.Remove(hi); // Yank from mask |
495 int lo = lrg.mask().find_first_elem(); // Find lo |
498 int lo = lrg.mask().find_first_elem(); // Find lo |
496 _node_regs[i].set_pair( hi, lo ); |
499 _node_regs[i].set_pair( hi, lo ); |
566 } |
569 } |
567 |
570 |
568 // Check for float-vs-int live range (used in register-pressure |
571 // Check for float-vs-int live range (used in register-pressure |
569 // calculations) |
572 // calculations) |
570 const Type *n_type = n->bottom_type(); |
573 const Type *n_type = n->bottom_type(); |
571 if( n_type->is_floatingpoint() ) |
574 if (n_type->is_floatingpoint()) |
572 lrg._is_float = 1; |
575 lrg._is_float = 1; |
573 |
576 |
574 // Check for twice prior spilling. Once prior spilling might have |
577 // Check for twice prior spilling. Once prior spilling might have |
575 // spilled 'soft', 2nd prior spill should have spilled 'hard' and |
578 // spilled 'soft', 2nd prior spill should have spilled 'hard' and |
576 // further spilling is unlikely to make progress. |
579 // further spilling is unlikely to make progress. |
597 lrg._def = lrg._def ? NodeSentinel : n; |
600 lrg._def = lrg._def ? NodeSentinel : n; |
598 |
601 |
599 // Limit result register mask to acceptable registers |
602 // Limit result register mask to acceptable registers |
600 const RegMask &rm = n->out_RegMask(); |
603 const RegMask &rm = n->out_RegMask(); |
601 lrg.AND( rm ); |
604 lrg.AND( rm ); |
602 // Check for bound register masks |
|
603 const RegMask &lrgmask = lrg.mask(); |
|
604 if( lrgmask.is_bound1() || lrgmask.is_bound2() ) |
|
605 lrg._is_bound = 1; |
|
606 |
|
607 // Check for maximum frequency value |
|
608 if( lrg._maxfreq < b->_freq ) |
|
609 lrg._maxfreq = b->_freq; |
|
610 |
605 |
611 int ireg = n->ideal_reg(); |
606 int ireg = n->ideal_reg(); |
612 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP, |
607 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP, |
613 "oops must be in Op_RegP's" ); |
608 "oops must be in Op_RegP's" ); |
|
609 |
|
610 // Check for vector live range (only if vector register is used). |
|
611 // On SPARC vector uses RegD which could be misaligned so it is not |
|
612 // processes as vector in RA. |
|
613 if (RegMask::is_vector(ireg)) |
|
614 lrg._is_vector = 1; |
|
615 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD, |
|
616 "vector must be in vector registers"); |
|
617 |
|
618 // Check for bound register masks |
|
619 const RegMask &lrgmask = lrg.mask(); |
|
620 if (lrgmask.is_bound(ireg)) |
|
621 lrg._is_bound = 1; |
|
622 |
|
623 // Check for maximum frequency value |
|
624 if (lrg._maxfreq < b->_freq) |
|
625 lrg._maxfreq = b->_freq; |
|
626 |
614 // Check for oop-iness, or long/double |
627 // Check for oop-iness, or long/double |
615 // Check for multi-kill projection |
628 // Check for multi-kill projection |
616 switch( ireg ) { |
629 switch( ireg ) { |
617 case MachProjNode::fat_proj: |
630 case MachProjNode::fat_proj: |
618 // Fat projections have size equal to number of registers killed |
631 // Fat projections have size equal to number of registers killed |
687 // If this def of a double forces a mis-aligned double, |
700 // If this def of a double forces a mis-aligned double, |
688 // flag as '_fat_proj' - really flag as allowing misalignment |
701 // flag as '_fat_proj' - really flag as allowing misalignment |
689 // AND changes how we count interferences. A mis-aligned |
702 // AND changes how we count interferences. A mis-aligned |
690 // double can interfere with TWO aligned pairs, or effectively |
703 // double can interfere with TWO aligned pairs, or effectively |
691 // FOUR registers! |
704 // FOUR registers! |
692 if( rm.is_misaligned_Pair() ) { |
705 if (rm.is_misaligned_pair()) { |
693 lrg._fat_proj = 1; |
706 lrg._fat_proj = 1; |
694 lrg._is_bound = 1; |
707 lrg._is_bound = 1; |
695 } |
708 } |
696 break; |
709 break; |
697 case Op_RegF: |
710 case Op_RegF: |
704 lrg.set_reg_pressure(2); |
717 lrg.set_reg_pressure(2); |
705 #else |
718 #else |
706 lrg.set_reg_pressure(1); |
719 lrg.set_reg_pressure(1); |
707 #endif |
720 #endif |
708 break; |
721 break; |
|
722 case Op_VecS: |
|
723 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity"); |
|
724 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity"); |
|
725 lrg.set_num_regs(RegMask::SlotsPerVecS); |
|
726 lrg.set_reg_pressure(1); |
|
727 break; |
|
728 case Op_VecD: |
|
729 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity"); |
|
730 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity"); |
|
731 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned"); |
|
732 lrg.set_num_regs(RegMask::SlotsPerVecD); |
|
733 lrg.set_reg_pressure(1); |
|
734 break; |
|
735 case Op_VecX: |
|
736 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity"); |
|
737 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity"); |
|
738 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned"); |
|
739 lrg.set_num_regs(RegMask::SlotsPerVecX); |
|
740 lrg.set_reg_pressure(1); |
|
741 break; |
|
742 case Op_VecY: |
|
743 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity"); |
|
744 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity"); |
|
745 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned"); |
|
746 lrg.set_num_regs(RegMask::SlotsPerVecY); |
|
747 lrg.set_reg_pressure(1); |
|
748 break; |
709 default: |
749 default: |
710 ShouldNotReachHere(); |
750 ShouldNotReachHere(); |
711 } |
751 } |
712 } |
752 } |
713 |
753 |
761 // Later, AFTER aggressive, this live range will have to spill |
801 // Later, AFTER aggressive, this live range will have to spill |
762 // but the spiller handles slow-path calls very nicely. |
802 // but the spiller handles slow-path calls very nicely. |
763 } else { |
803 } else { |
764 lrg.AND( rm ); |
804 lrg.AND( rm ); |
765 } |
805 } |
|
806 |
766 // Check for bound register masks |
807 // Check for bound register masks |
767 const RegMask &lrgmask = lrg.mask(); |
808 const RegMask &lrgmask = lrg.mask(); |
768 if( lrgmask.is_bound1() || lrgmask.is_bound2() ) |
809 int kreg = n->in(k)->ideal_reg(); |
|
810 bool is_vect = RegMask::is_vector(kreg); |
|
811 assert(n->in(k)->bottom_type()->isa_vect() == NULL || |
|
812 is_vect || kreg == Op_RegD, |
|
813 "vector must be in vector registers"); |
|
814 if (lrgmask.is_bound(kreg)) |
769 lrg._is_bound = 1; |
815 lrg._is_bound = 1; |
|
816 |
770 // If this use of a double forces a mis-aligned double, |
817 // If this use of a double forces a mis-aligned double, |
771 // flag as '_fat_proj' - really flag as allowing misalignment |
818 // flag as '_fat_proj' - really flag as allowing misalignment |
772 // AND changes how we count interferences. A mis-aligned |
819 // AND changes how we count interferences. A mis-aligned |
773 // double can interfere with TWO aligned pairs, or effectively |
820 // double can interfere with TWO aligned pairs, or effectively |
774 // FOUR registers! |
821 // FOUR registers! |
775 if( lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_Pair() ) { |
822 #ifdef ASSERT |
|
823 if (is_vect) { |
|
824 assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned"); |
|
825 assert(!lrg._fat_proj, "sanity"); |
|
826 assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity"); |
|
827 } |
|
828 #endif |
|
829 if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) { |
776 lrg._fat_proj = 1; |
830 lrg._fat_proj = 1; |
777 lrg._is_bound = 1; |
831 lrg._is_bound = 1; |
778 } |
832 } |
779 // if the LRG is an unaligned pair, we will have to spill |
833 // if the LRG is an unaligned pair, we will have to spill |
780 // so clear the LRG's register mask if it is not already spilled |
834 // so clear the LRG's register mask if it is not already spilled |
781 if ( !n->is_SpillCopy() && |
835 if (!is_vect && !n->is_SpillCopy() && |
782 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) && |
836 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) && |
783 lrgmask.is_misaligned_Pair()) { |
837 lrgmask.is_misaligned_pair()) { |
784 lrg.Clear(); |
838 lrg.Clear(); |
785 } |
839 } |
786 |
840 |
787 // Check for maximum frequency value |
841 // Check for maximum frequency value |
788 if( lrg._maxfreq < b->_freq ) |
842 if( lrg._maxfreq < b->_freq ) |
791 } // End for all allocated inputs |
845 } // End for all allocated inputs |
792 } // end for all instructions |
846 } // end for all instructions |
793 } // end for all blocks |
847 } // end for all blocks |
794 |
848 |
795 // Final per-liverange setup |
849 // Final per-liverange setup |
796 for( uint i2=0; i2<_maxlrg; i2++ ) { |
850 for (uint i2=0; i2<_maxlrg; i2++) { |
797 LRG &lrg = lrgs(i2); |
851 LRG &lrg = lrgs(i2); |
798 if( lrg.num_regs() == 2 && !lrg._fat_proj ) |
852 assert(!lrg._is_vector || !lrg._fat_proj, "sanity"); |
799 lrg.ClearToPairs(); |
853 if (lrg.num_regs() > 1 && !lrg._fat_proj) { |
|
854 lrg.clear_to_sets(); |
|
855 } |
800 lrg.compute_set_mask_size(); |
856 lrg.compute_set_mask_size(); |
801 if( lrg.not_free() ) { // Handle case where we lose from the start |
857 if (lrg.not_free()) { // Handle case where we lose from the start |
802 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG)); |
858 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG)); |
803 lrg._direct_conflict = 1; |
859 lrg._direct_conflict = 1; |
804 } |
860 } |
805 lrg.set_degree(0); // no neighbors in IFG yet |
861 lrg.set_degree(0); // no neighbors in IFG yet |
806 } |
862 } |
1102 return reg; |
1158 return reg; |
1103 } else if( chunk == 0 ) { |
1159 } else if( chunk == 0 ) { |
1104 // Choose a color which is legal for him |
1160 // Choose a color which is legal for him |
1105 RegMask tempmask = lrg.mask(); |
1161 RegMask tempmask = lrg.mask(); |
1106 tempmask.AND(lrgs(copy_lrg).mask()); |
1162 tempmask.AND(lrgs(copy_lrg).mask()); |
1107 OptoReg::Name reg; |
1163 tempmask.clear_to_sets(lrg.num_regs()); |
1108 if( lrg.num_regs() == 1 ) { |
1164 OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs()); |
1109 reg = tempmask.find_first_elem(); |
1165 if (OptoReg::is_valid(reg)) |
1110 } else { |
|
1111 tempmask.ClearToPairs(); |
|
1112 reg = tempmask.find_first_pair(); |
|
1113 } |
|
1114 if( OptoReg::is_valid(reg) ) |
|
1115 return reg; |
1166 return reg; |
1116 } |
1167 } |
1117 } |
1168 } |
1118 |
1169 |
1119 // If no bias info exists, just go with the register selection ordering |
1170 // If no bias info exists, just go with the register selection ordering |
1120 if( lrg.num_regs() == 2 ) { |
1171 if (lrg._is_vector || lrg.num_regs() == 2) { |
1121 // Find an aligned pair |
1172 // Find an aligned set |
1122 return OptoReg::add(lrg.mask().find_first_pair(),chunk); |
1173 return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk); |
1123 } |
1174 } |
1124 |
1175 |
1125 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate |
1176 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate |
1126 // copy removal to remove many more copies, by preventing a just-assigned |
1177 // copy removal to remove many more copies, by preventing a just-assigned |
1127 // register from being repeatedly assigned. |
1178 // register from being repeatedly assigned. |
1147 if( lrg.num_regs() == 1 || // Common Case |
1198 if( lrg.num_regs() == 1 || // Common Case |
1148 !lrg._fat_proj ) // Aligned+adjacent pairs ok |
1199 !lrg._fat_proj ) // Aligned+adjacent pairs ok |
1149 // Use a heuristic to "bias" the color choice |
1200 // Use a heuristic to "bias" the color choice |
1150 return bias_color(lrg, chunk); |
1201 return bias_color(lrg, chunk); |
1151 |
1202 |
|
1203 assert(!lrg._is_vector, "should be not vector here" ); |
1152 assert( lrg.num_regs() >= 2, "dead live ranges do not color" ); |
1204 assert( lrg.num_regs() >= 2, "dead live ranges do not color" ); |
1153 |
1205 |
1154 // Fat-proj case or misaligned double argument. |
1206 // Fat-proj case or misaligned double argument. |
1155 assert(lrg.compute_mask_size() == lrg.num_regs() || |
1207 assert(lrg.compute_mask_size() == lrg.num_regs() || |
1156 lrg.num_regs() == 2,"fat projs exactly color" ); |
1208 lrg.num_regs() == 2,"fat projs exactly color" ); |
1236 #endif |
1288 #endif |
1237 } |
1289 } |
1238 } |
1290 } |
1239 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness"); |
1291 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness"); |
1240 // Aligned pairs need aligned masks |
1292 // Aligned pairs need aligned masks |
1241 if( lrg->num_regs() == 2 && !lrg->_fat_proj ) |
1293 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); |
1242 lrg->ClearToPairs(); |
1294 if (lrg->num_regs() > 1 && !lrg->_fat_proj) { |
|
1295 lrg->clear_to_sets(); |
|
1296 } |
1243 |
1297 |
1244 // Check if a color is available and if so pick the color |
1298 // Check if a color is available and if so pick the color |
1245 OptoReg::Name reg = choose_color( *lrg, chunk ); |
1299 OptoReg::Name reg = choose_color( *lrg, chunk ); |
1246 #ifdef SPARC |
1300 #ifdef SPARC |
1247 debug_only(lrg->compute_set_mask_size()); |
1301 debug_only(lrg->compute_set_mask_size()); |
1248 assert(lrg->num_regs() != 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned"); |
1302 assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned"); |
1249 #endif |
1303 #endif |
1250 |
1304 |
1251 //--------------- |
1305 //--------------- |
1252 // If we fail to color and the AllStack flag is set, trigger |
1306 // If we fail to color and the AllStack flag is set, trigger |
1253 // a chunk-rollover event |
1307 // a chunk-rollover event |
1275 reg = OptoReg::add(reg,-chunk); |
1329 reg = OptoReg::add(reg,-chunk); |
1276 |
1330 |
1277 // If the live range is not bound, then we actually had some choices |
1331 // If the live range is not bound, then we actually had some choices |
1278 // to make. In this case, the mask has more bits in it than the colors |
1332 // to make. In this case, the mask has more bits in it than the colors |
1279 // chosen. Restrict the mask to just what was picked. |
1333 // chosen. Restrict the mask to just what was picked. |
1280 if( lrg->num_regs() == 1 ) { // Size 1 live range |
1334 int n_regs = lrg->num_regs(); |
|
1335 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); |
|
1336 if (n_regs == 1 || !lrg->_fat_proj) { |
|
1337 assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecY, "sanity"); |
1281 lrg->Clear(); // Clear the mask |
1338 lrg->Clear(); // Clear the mask |
1282 lrg->Insert(reg); // Set regmask to match selected reg |
1339 lrg->Insert(reg); // Set regmask to match selected reg |
1283 lrg->set_mask_size(1); |
1340 // For vectors and pairs, also insert the low bit of the pair |
1284 } else if( !lrg->_fat_proj ) { |
1341 for (int i = 1; i < n_regs; i++) |
1285 // For pairs, also insert the low bit of the pair |
1342 lrg->Insert(OptoReg::add(reg,-i)); |
1286 assert( lrg->num_regs() == 2, "unbound fatproj???" ); |
1343 lrg->set_mask_size(n_regs); |
1287 lrg->Clear(); // Clear the mask |
|
1288 lrg->Insert(reg); // Set regmask to match selected reg |
|
1289 lrg->Insert(OptoReg::add(reg,-1)); |
|
1290 lrg->set_mask_size(2); |
|
1291 } else { // Else fatproj |
1344 } else { // Else fatproj |
1292 // mask must be equal to fatproj bits, by definition |
1345 // mask must be equal to fatproj bits, by definition |
1293 } |
1346 } |
1294 #ifndef PRODUCT |
1347 #ifndef PRODUCT |
1295 if (trace_spilling()) { |
1348 if (trace_spilling()) { |
1858 uint lidx = Find_const(n); // Grab LRG number |
1911 uint lidx = Find_const(n); // Grab LRG number |
1859 if( !_ifg ) { |
1912 if( !_ifg ) { |
1860 sprintf(buf,"L%d",lidx); // No register binding yet |
1913 sprintf(buf,"L%d",lidx); // No register binding yet |
1861 } else if( !lidx ) { // Special, not allocated value |
1914 } else if( !lidx ) { // Special, not allocated value |
1862 strcpy(buf,"Special"); |
1915 strcpy(buf,"Special"); |
1863 } else if( (lrgs(lidx).num_regs() == 1) |
1916 } else { |
1864 ? !lrgs(lidx).mask().is_bound1() |
1917 if (lrgs(lidx)._is_vector) { |
1865 : !lrgs(lidx).mask().is_bound2() ) { |
1918 if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs())) |
1866 sprintf(buf,"L%d",lidx); // No register binding yet |
1919 print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register |
1867 } else { // Hah! We have a bound machine register |
1920 else |
1868 print_reg( lrgs(lidx).reg(), this, buf ); |
1921 sprintf(buf,"L%d",lidx); // No register binding yet |
|
1922 } else if( (lrgs(lidx).num_regs() == 1) |
|
1923 ? lrgs(lidx).mask().is_bound1() |
|
1924 : lrgs(lidx).mask().is_bound_pair() ) { |
|
1925 // Hah! We have a bound machine register |
|
1926 print_reg( lrgs(lidx).reg(), this, buf ); |
|
1927 } else { |
|
1928 sprintf(buf,"L%d",lidx); // No register binding yet |
|
1929 } |
1869 } |
1930 } |
1870 } |
1931 } |
1871 return buf+strlen(buf); |
1932 return buf+strlen(buf); |
1872 } |
1933 } |
1873 |
1934 |