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1 /* |
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2 * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved. |
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3 * Copyright (c) 2016 SAP SE. All rights reserved. |
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4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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5 * |
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6 * This code is free software; you can redistribute it and/or modify it |
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7 * under the terms of the GNU General Public License version 2 only, as |
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8 * published by the Free Software Foundation. |
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9 * |
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10 * This code is distributed in the hope that it will be useful, but WITHOUT |
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11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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13 * version 2 for more details (a copy is included in the LICENSE file that |
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14 * accompanied this code). |
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15 * |
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16 * You should have received a copy of the GNU General Public License version |
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17 * 2 along with this work; if not, write to the Free Software Foundation, |
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18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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19 * |
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20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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21 * or visit www.oracle.com if you need additional information or have any |
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22 * questions. |
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23 * |
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24 */ |
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25 |
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26 #include "precompiled.hpp" |
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27 #include "c1/c1_FrameMap.hpp" |
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28 #include "c1/c1_LIR.hpp" |
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29 #include "runtime/sharedRuntime.hpp" |
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30 #include "vmreg_s390.inline.hpp" |
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31 |
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32 |
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33 const int FrameMap::pd_c_runtime_reserved_arg_size = 7; |
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34 |
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35 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) { |
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36 LIR_Opr opr = LIR_OprFact::illegalOpr; |
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37 VMReg r_1 = reg->first(); |
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38 VMReg r_2 = reg->second(); |
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39 if (r_1->is_stack()) { |
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40 // Convert stack slot to an SP offset. |
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41 // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value |
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42 // so we must add it in here. |
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43 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; |
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44 opr = LIR_OprFact::address(new LIR_Address(Z_SP_opr, st_off, type)); |
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45 } else if (r_1->is_Register()) { |
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46 Register reg = r_1->as_Register(); |
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47 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { |
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48 opr = as_long_opr(reg); |
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49 } else if (type == T_OBJECT || type == T_ARRAY) { |
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50 opr = as_oop_opr(reg); |
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51 } else if (type == T_METADATA) { |
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52 opr = as_metadata_opr(reg); |
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53 } else { |
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54 opr = as_opr(reg); |
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55 } |
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56 } else if (r_1->is_FloatRegister()) { |
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57 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); |
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58 FloatRegister f = r_1->as_FloatRegister(); |
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59 if (type == T_FLOAT) { |
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60 opr = as_float_opr(f); |
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61 } else { |
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62 opr = as_double_opr(f); |
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63 } |
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64 } else { |
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65 ShouldNotReachHere(); |
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66 } |
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67 return opr; |
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68 } |
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69 |
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70 // FrameMap |
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71 //-------------------------------------------------------- |
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72 |
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73 FloatRegister FrameMap::_fpu_rnr2reg [FrameMap::nof_fpu_regs]; // mapping c1 regnr. -> FloatRegister |
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74 int FrameMap::_fpu_reg2rnr [FrameMap::nof_fpu_regs]; // mapping assembler encoding -> c1 regnr. |
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75 |
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76 // Some useful constant RInfo's: |
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77 LIR_Opr FrameMap::Z_R0_opr; |
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78 LIR_Opr FrameMap::Z_R1_opr; |
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79 LIR_Opr FrameMap::Z_R2_opr; |
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80 LIR_Opr FrameMap::Z_R3_opr; |
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81 LIR_Opr FrameMap::Z_R4_opr; |
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82 LIR_Opr FrameMap::Z_R5_opr; |
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83 LIR_Opr FrameMap::Z_R6_opr; |
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84 LIR_Opr FrameMap::Z_R7_opr; |
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85 LIR_Opr FrameMap::Z_R8_opr; |
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86 LIR_Opr FrameMap::Z_R9_opr; |
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87 LIR_Opr FrameMap::Z_R10_opr; |
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88 LIR_Opr FrameMap::Z_R11_opr; |
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89 LIR_Opr FrameMap::Z_R12_opr; |
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90 LIR_Opr FrameMap::Z_R13_opr; |
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91 LIR_Opr FrameMap::Z_R14_opr; |
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92 LIR_Opr FrameMap::Z_R15_opr; |
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93 |
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94 LIR_Opr FrameMap::Z_R0_oop_opr; |
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95 LIR_Opr FrameMap::Z_R1_oop_opr; |
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96 LIR_Opr FrameMap::Z_R2_oop_opr; |
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97 LIR_Opr FrameMap::Z_R3_oop_opr; |
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98 LIR_Opr FrameMap::Z_R4_oop_opr; |
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99 LIR_Opr FrameMap::Z_R5_oop_opr; |
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100 LIR_Opr FrameMap::Z_R6_oop_opr; |
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101 LIR_Opr FrameMap::Z_R7_oop_opr; |
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102 LIR_Opr FrameMap::Z_R8_oop_opr; |
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103 LIR_Opr FrameMap::Z_R9_oop_opr; |
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104 LIR_Opr FrameMap::Z_R10_oop_opr; |
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105 LIR_Opr FrameMap::Z_R11_oop_opr; |
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106 LIR_Opr FrameMap::Z_R12_oop_opr; |
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107 LIR_Opr FrameMap::Z_R13_oop_opr; |
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108 LIR_Opr FrameMap::Z_R14_oop_opr; |
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109 LIR_Opr FrameMap::Z_R15_oop_opr; |
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110 |
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111 LIR_Opr FrameMap::Z_R0_metadata_opr; |
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112 LIR_Opr FrameMap::Z_R1_metadata_opr; |
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113 LIR_Opr FrameMap::Z_R2_metadata_opr; |
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114 LIR_Opr FrameMap::Z_R3_metadata_opr; |
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115 LIR_Opr FrameMap::Z_R4_metadata_opr; |
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116 LIR_Opr FrameMap::Z_R5_metadata_opr; |
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117 LIR_Opr FrameMap::Z_R6_metadata_opr; |
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118 LIR_Opr FrameMap::Z_R7_metadata_opr; |
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119 LIR_Opr FrameMap::Z_R8_metadata_opr; |
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120 LIR_Opr FrameMap::Z_R9_metadata_opr; |
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121 LIR_Opr FrameMap::Z_R10_metadata_opr; |
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122 LIR_Opr FrameMap::Z_R11_metadata_opr; |
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123 LIR_Opr FrameMap::Z_R12_metadata_opr; |
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124 LIR_Opr FrameMap::Z_R13_metadata_opr; |
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125 LIR_Opr FrameMap::Z_R14_metadata_opr; |
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126 LIR_Opr FrameMap::Z_R15_metadata_opr; |
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127 |
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128 LIR_Opr FrameMap::Z_SP_opr; |
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129 LIR_Opr FrameMap::Z_FP_opr; |
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130 |
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131 LIR_Opr FrameMap::Z_R2_long_opr; |
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132 LIR_Opr FrameMap::Z_R10_long_opr; |
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133 LIR_Opr FrameMap::Z_R11_long_opr; |
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134 |
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135 LIR_Opr FrameMap::Z_F0_opr; |
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136 LIR_Opr FrameMap::Z_F0_double_opr; |
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137 |
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138 |
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139 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; |
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140 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; |
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141 |
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142 |
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143 // c1 rnr -> FloatRegister |
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144 FloatRegister FrameMap::nr2floatreg (int rnr) { |
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145 assert(_init_done, "tables not initialized"); |
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146 debug_only(fpu_range_check(rnr);) |
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147 return _fpu_rnr2reg[rnr]; |
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148 } |
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149 |
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150 void FrameMap::map_float_register(int rnr, FloatRegister reg) { |
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151 debug_only(fpu_range_check(rnr);) |
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152 debug_only(fpu_range_check(reg->encoding());) |
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153 _fpu_rnr2reg[rnr] = reg; // mapping c1 regnr. -> FloatRegister |
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154 _fpu_reg2rnr[reg->encoding()] = rnr; // mapping assembler encoding -> c1 regnr. |
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155 } |
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156 |
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157 void FrameMap::initialize() { |
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158 assert(!_init_done, "once"); |
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159 |
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160 DEBUG_ONLY(int allocated = 0;) |
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161 DEBUG_ONLY(int unallocated = 0;) |
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162 |
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163 // Register usage: |
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164 // Z_thread (Z_R8) |
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165 // Z_fp (Z_R9) |
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166 // Z_SP (Z_R15) |
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167 DEBUG_ONLY(allocated++); map_register(0, Z_R2); |
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168 DEBUG_ONLY(allocated++); map_register(1, Z_R3); |
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169 DEBUG_ONLY(allocated++); map_register(2, Z_R4); |
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170 DEBUG_ONLY(allocated++); map_register(3, Z_R5); |
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171 DEBUG_ONLY(allocated++); map_register(4, Z_R6); |
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172 DEBUG_ONLY(allocated++); map_register(5, Z_R7); |
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173 DEBUG_ONLY(allocated++); map_register(6, Z_R10); |
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174 DEBUG_ONLY(allocated++); map_register(7, Z_R11); |
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175 DEBUG_ONLY(allocated++); map_register(8, Z_R12); |
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176 DEBUG_ONLY(allocated++); map_register(9, Z_R13); // <- last register visible in RegAlloc |
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177 DEBUG_ONLY(unallocated++); map_register(11, Z_R0); // Z_R0_scratch |
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178 DEBUG_ONLY(unallocated++); map_register(12, Z_R1); // Z_R1_scratch |
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179 DEBUG_ONLY(unallocated++); map_register(10, Z_R14); // return pc; TODO: Try to let c1/c2 allocate R14. |
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180 |
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181 // The following registers are usually unavailable. |
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182 DEBUG_ONLY(unallocated++); map_register(13, Z_R8); |
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183 DEBUG_ONLY(unallocated++); map_register(14, Z_R9); |
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184 DEBUG_ONLY(unallocated++); map_register(15, Z_R15); |
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185 assert(allocated-1 == pd_last_cpu_reg, "wrong number/mapping of allocated CPU registers"); |
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186 assert(unallocated == pd_nof_cpu_regs_unallocated, "wrong number of unallocated CPU registers"); |
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187 assert(nof_cpu_regs == allocated+unallocated, "wrong number of CPU registers"); |
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188 |
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189 int j = 0; |
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190 for (int i = 0; i < nof_fpu_regs; i++) { |
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191 if (as_FloatRegister(i) == Z_fscratch_1) continue; // unallocated |
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192 map_float_register(j++, as_FloatRegister(i)); |
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193 } |
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194 assert(j == nof_fpu_regs-1, "missed one fpu reg?"); |
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195 map_float_register(j++, Z_fscratch_1); |
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196 |
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197 _init_done = true; |
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198 |
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199 Z_R0_opr = as_opr(Z_R0); |
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200 Z_R1_opr = as_opr(Z_R1); |
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201 Z_R2_opr = as_opr(Z_R2); |
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202 Z_R3_opr = as_opr(Z_R3); |
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203 Z_R4_opr = as_opr(Z_R4); |
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204 Z_R5_opr = as_opr(Z_R5); |
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205 Z_R6_opr = as_opr(Z_R6); |
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206 Z_R7_opr = as_opr(Z_R7); |
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207 Z_R8_opr = as_opr(Z_R8); |
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208 Z_R9_opr = as_opr(Z_R9); |
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209 Z_R10_opr = as_opr(Z_R10); |
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210 Z_R11_opr = as_opr(Z_R11); |
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211 Z_R12_opr = as_opr(Z_R12); |
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212 Z_R13_opr = as_opr(Z_R13); |
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213 Z_R14_opr = as_opr(Z_R14); |
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214 Z_R15_opr = as_opr(Z_R15); |
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215 |
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216 Z_R0_oop_opr = as_oop_opr(Z_R0); |
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217 Z_R1_oop_opr = as_oop_opr(Z_R1); |
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218 Z_R2_oop_opr = as_oop_opr(Z_R2); |
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219 Z_R3_oop_opr = as_oop_opr(Z_R3); |
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220 Z_R4_oop_opr = as_oop_opr(Z_R4); |
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221 Z_R5_oop_opr = as_oop_opr(Z_R5); |
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222 Z_R6_oop_opr = as_oop_opr(Z_R6); |
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223 Z_R7_oop_opr = as_oop_opr(Z_R7); |
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224 Z_R8_oop_opr = as_oop_opr(Z_R8); |
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225 Z_R9_oop_opr = as_oop_opr(Z_R9); |
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226 Z_R10_oop_opr = as_oop_opr(Z_R10); |
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227 Z_R11_oop_opr = as_oop_opr(Z_R11); |
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228 Z_R12_oop_opr = as_oop_opr(Z_R12); |
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229 Z_R13_oop_opr = as_oop_opr(Z_R13); |
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230 Z_R14_oop_opr = as_oop_opr(Z_R14); |
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231 Z_R15_oop_opr = as_oop_opr(Z_R15); |
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232 |
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233 Z_R0_metadata_opr = as_metadata_opr(Z_R0); |
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234 Z_R1_metadata_opr = as_metadata_opr(Z_R1); |
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235 Z_R2_metadata_opr = as_metadata_opr(Z_R2); |
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236 Z_R3_metadata_opr = as_metadata_opr(Z_R3); |
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237 Z_R4_metadata_opr = as_metadata_opr(Z_R4); |
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238 Z_R5_metadata_opr = as_metadata_opr(Z_R5); |
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239 Z_R6_metadata_opr = as_metadata_opr(Z_R6); |
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240 Z_R7_metadata_opr = as_metadata_opr(Z_R7); |
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241 Z_R8_metadata_opr = as_metadata_opr(Z_R8); |
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242 Z_R9_metadata_opr = as_metadata_opr(Z_R9); |
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243 Z_R10_metadata_opr = as_metadata_opr(Z_R10); |
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244 Z_R11_metadata_opr = as_metadata_opr(Z_R11); |
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245 Z_R12_metadata_opr = as_metadata_opr(Z_R12); |
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246 Z_R13_metadata_opr = as_metadata_opr(Z_R13); |
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247 Z_R14_metadata_opr = as_metadata_opr(Z_R14); |
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248 Z_R15_metadata_opr = as_metadata_opr(Z_R15); |
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249 |
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250 // TODO: needed? Or can we make Z_R9 available for linear scan allocation. |
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251 Z_FP_opr = as_pointer_opr(Z_fp); |
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252 Z_SP_opr = as_pointer_opr(Z_SP); |
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253 |
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254 Z_R2_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(Z_R2), cpu_reg2rnr(Z_R2)); |
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255 Z_R10_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(Z_R10), cpu_reg2rnr(Z_R10)); |
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256 Z_R11_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(Z_R11), cpu_reg2rnr(Z_R11)); |
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257 |
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258 Z_F0_opr = as_float_opr(Z_F0); |
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259 Z_F0_double_opr = as_double_opr(Z_F0); |
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260 |
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261 // All allocated cpu regs are caller saved. |
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262 for (int c1rnr = 0; c1rnr < max_nof_caller_save_cpu_regs; c1rnr++) { |
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263 _caller_save_cpu_regs[c1rnr] = as_opr(cpu_rnr2reg(c1rnr)); |
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264 } |
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265 |
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266 // All allocated fpu regs are caller saved. |
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267 for (int c1rnr = 0; c1rnr < nof_caller_save_fpu_regs; c1rnr++) { |
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268 _caller_save_fpu_regs[c1rnr] = as_float_opr(nr2floatreg(c1rnr)); |
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269 } |
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270 } |
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271 |
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272 Address FrameMap::make_new_address(ByteSize sp_offset) const { |
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273 return Address(Z_SP, sp_offset); |
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274 } |
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275 |
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276 VMReg FrameMap::fpu_regname (int n) { |
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277 return nr2floatreg(n)->as_VMReg(); |
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278 } |
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279 |
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280 LIR_Opr FrameMap::stack_pointer() { |
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281 return Z_SP_opr; |
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282 } |
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283 |
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284 // JSR 292 |
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285 // On ZARCH_64, there is no need to save the SP, because neither |
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286 // method handle intrinsics nor compiled lambda forms modify it. |
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287 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { |
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288 return LIR_OprFact::illegalOpr; |
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289 } |
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290 |
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291 bool FrameMap::validate_frame() { |
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292 return true; |
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293 } |