equal
deleted
inserted
replaced
9488 // And Register with Immediate 255 |
9488 // And Register with Immediate 255 |
9489 instruct andL_rReg_imm255(rRegL dst, immL_255 src) |
9489 instruct andL_rReg_imm255(rRegL dst, immL_255 src) |
9490 %{ |
9490 %{ |
9491 match(Set dst (AndL dst src)); |
9491 match(Set dst (AndL dst src)); |
9492 |
9492 |
9493 format %{ "movzbq $dst, $src\t# long & 0xFF" %} |
9493 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
9494 opcode(0x0F, 0xB6); |
9494 opcode(0x0F, 0xB6); |
9495 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); |
9495 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); |
9496 ins_pipe(ialu_reg); |
9496 ins_pipe(ialu_reg); |
9497 %} |
9497 %} |
9498 |
9498 |
9499 // And Register with Immediate 65535 |
9499 // And Register with Immediate 65535 |
9500 instruct andL_rReg_imm65535(rRegI dst, immL_65535 src) |
9500 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
9501 %{ |
9501 %{ |
9502 match(Set dst (AndL dst src)); |
9502 match(Set dst (AndL dst src)); |
9503 |
9503 |
9504 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} |
9504 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} |
9505 opcode(0x0F, 0xB7); |
9505 opcode(0x0F, 0xB7); |