62 inline void OrderAccess::cross_modify_fence() { |
62 inline void OrderAccess::cross_modify_fence() { |
63 int idx = 0; |
63 int idx = 0; |
64 __asm__ volatile ("cpuid " : "+a" (idx) : : "ebx", "ecx", "edx", "memory"); |
64 __asm__ volatile ("cpuid " : "+a" (idx) : : "ebx", "ecx", "edx", "memory"); |
65 } |
65 } |
66 |
66 |
67 template<> |
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68 struct OrderAccess::PlatformOrderedStore<1, RELEASE_X_FENCE> |
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69 { |
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70 template <typename T> |
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71 void operator()(T v, volatile T* p) const { |
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72 __asm__ volatile ( "xchgb (%2),%0" |
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73 : "=q" (v) |
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74 : "0" (v), "r" (p) |
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75 : "memory"); |
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76 } |
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77 }; |
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78 |
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79 template<> |
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80 struct OrderAccess::PlatformOrderedStore<2, RELEASE_X_FENCE> |
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81 { |
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82 template <typename T> |
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83 void operator()(T v, volatile T* p) const { |
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84 __asm__ volatile ( "xchgw (%2),%0" |
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85 : "=r" (v) |
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86 : "0" (v), "r" (p) |
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87 : "memory"); |
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88 } |
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89 }; |
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90 |
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91 template<> |
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92 struct OrderAccess::PlatformOrderedStore<4, RELEASE_X_FENCE> |
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93 { |
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94 template <typename T> |
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95 void operator()(T v, volatile T* p) const { |
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96 __asm__ volatile ( "xchgl (%2),%0" |
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97 : "=r" (v) |
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98 : "0" (v), "r" (p) |
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99 : "memory"); |
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100 } |
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101 }; |
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102 |
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103 #ifdef AMD64 |
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104 template<> |
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105 struct OrderAccess::PlatformOrderedStore<8, RELEASE_X_FENCE> |
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106 { |
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107 template <typename T> |
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108 void operator()(T v, volatile T* p) const { |
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109 __asm__ volatile ( "xchgq (%2), %0" |
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110 : "=r" (v) |
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111 : "0" (v), "r" (p) |
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112 : "memory"); |
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113 } |
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114 }; |
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115 #endif // AMD64 |
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116 |
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117 #endif // OS_CPU_BSD_X86_ORDERACCESS_BSD_X86_HPP |
67 #endif // OS_CPU_BSD_X86_ORDERACCESS_BSD_X86_HPP |