5429 |
5429 |
5430 ins_pipe(ialu_reg_mem); |
5430 ins_pipe(ialu_reg_mem); |
5431 %} |
5431 %} |
5432 |
5432 |
5433 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register |
5433 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register |
5434 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ |
5434 instruct loadUB2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ |
5435 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); |
5435 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); |
5436 effect(KILL cr); |
5436 effect(KILL cr); |
5437 |
5437 |
5438 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" |
5438 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 32-bit mask -> long\n\t" |
5439 "XOR $dst.hi,$dst.hi\n\t" |
5439 "XOR $dst.hi,$dst.hi\n\t" |
5440 "AND $dst.lo,$mask" %} |
5440 "AND $dst.lo,right_n_bits($mask, 8)" %} |
5441 ins_encode %{ |
5441 ins_encode %{ |
5442 Register Rdst = $dst$$Register; |
5442 Register Rdst = $dst$$Register; |
5443 __ movzbl(Rdst, $mem$$Address); |
5443 __ movzbl(Rdst, $mem$$Address); |
5444 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); |
5444 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); |
5445 __ andl(Rdst, $mask$$constant); |
5445 __ andl(Rdst, $mask$$constant & right_n_bits(8)); |
5446 %} |
5446 %} |
5447 ins_pipe(ialu_reg_mem); |
5447 ins_pipe(ialu_reg_mem); |
5448 %} |
5448 %} |
5449 |
5449 |
5450 // Load Short (16bit signed) |
5450 // Load Short (16bit signed) |
5548 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); |
5548 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); |
5549 %} |
5549 %} |
5550 ins_pipe(ialu_reg_mem); |
5550 ins_pipe(ialu_reg_mem); |
5551 %} |
5551 %} |
5552 |
5552 |
5553 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register |
5553 // Load Unsigned Short/Char (16 bit UNsigned) with a 32-bit mask into Long Register |
5554 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ |
5554 instruct loadUS2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ |
5555 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); |
5555 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); |
5556 effect(KILL cr); |
5556 effect(KILL cr); |
5557 |
5557 |
5558 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" |
5558 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 32-bit mask -> long\n\t" |
5559 "XOR $dst.hi,$dst.hi\n\t" |
5559 "XOR $dst.hi,$dst.hi\n\t" |
5560 "AND $dst.lo,$mask" %} |
5560 "AND $dst.lo,right_n_bits($mask, 16)" %} |
5561 ins_encode %{ |
5561 ins_encode %{ |
5562 Register Rdst = $dst$$Register; |
5562 Register Rdst = $dst$$Register; |
5563 __ movzwl(Rdst, $mem$$Address); |
5563 __ movzwl(Rdst, $mem$$Address); |
5564 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); |
5564 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); |
5565 __ andl(Rdst, $mask$$constant); |
5565 __ andl(Rdst, $mask$$constant & right_n_bits(16)); |
5566 %} |
5566 %} |
5567 ins_pipe(ialu_reg_mem); |
5567 ins_pipe(ialu_reg_mem); |
5568 %} |
5568 %} |
5569 |
5569 |
5570 // Load Integer |
5570 // Load Integer |