1 /* |
1 /* |
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. |
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * |
4 * |
5 * This code is free software; you can redistribute it and/or modify it |
5 * This code is free software; you can redistribute it and/or modify it |
6 * under the terms of the GNU General Public License version 2 only, as |
6 * under the terms of the GNU General Public License version 2 only, as |
7 * published by the Free Software Foundation. |
7 * published by the Free Software Foundation. |
1076 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) |
1081 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) |
1077 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) |
1082 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) |
1078 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). |
1083 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). |
1079 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). |
1084 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). |
1080 |
1085 |
|
1086 |
|
1087 if (is_zx()) { // ZX cpus specific settings |
|
1088 if (FLAG_IS_DEFAULT(UseStoreImmI16)) { |
|
1089 UseStoreImmI16 = false; // don't use it on ZX cpus |
|
1090 } |
|
1091 if ((cpu_family() == 6) || (cpu_family() == 7)) { |
|
1092 if (FLAG_IS_DEFAULT(UseAddressNop)) { |
|
1093 // Use it on all ZX cpus |
|
1094 UseAddressNop = true; |
|
1095 } |
|
1096 } |
|
1097 if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) { |
|
1098 UseXmmLoadAndClearUpper = true; // use movsd on all ZX cpus |
|
1099 } |
|
1100 if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) { |
|
1101 if (supports_sse3()) { |
|
1102 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new ZX cpus |
|
1103 } else { |
|
1104 UseXmmRegToRegMoveAll = false; |
|
1105 } |
|
1106 } |
|
1107 if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) { // new ZX cpus |
|
1108 #ifdef COMPILER2 |
|
1109 if (FLAG_IS_DEFAULT(MaxLoopPad)) { |
|
1110 // For new ZX cpus do the next optimization: |
|
1111 // don't align the beginning of a loop if there are enough instructions |
|
1112 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) |
|
1113 // in current fetch line (OptoLoopAlignment) or the padding |
|
1114 // is big (> MaxLoopPad). |
|
1115 // Set MaxLoopPad to 11 for new ZX cpus to reduce number of |
|
1116 // generated NOP instructions. 11 is the largest size of one |
|
1117 // address NOP instruction '0F 1F' (see Assembler::nop(i)). |
|
1118 MaxLoopPad = 11; |
|
1119 } |
|
1120 #endif // COMPILER2 |
|
1121 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
|
1122 UseXMMForArrayCopy = true; // use SSE2 movq on new ZX cpus |
|
1123 } |
|
1124 if (supports_sse4_2()) { // new ZX cpus |
|
1125 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
|
1126 UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus |
|
1127 } |
|
1128 } |
|
1129 if (supports_sse4_2()) { |
|
1130 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { |
|
1131 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true); |
|
1132 } |
|
1133 } else { |
|
1134 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
|
1135 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled."); |
|
1136 } |
|
1137 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false); |
|
1138 } |
|
1139 } |
|
1140 |
|
1141 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { |
|
1142 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3); |
|
1143 } |
|
1144 } |
|
1145 |
1081 if( is_amd() ) { // AMD cpus specific settings |
1146 if( is_amd() ) { // AMD cpus specific settings |
1082 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { |
1147 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { |
1083 // Use it on new AMD cpus starting from Opteron. |
1148 // Use it on new AMD cpus starting from Opteron. |
1084 UseAddressNop = true; |
1149 UseAddressNop = true; |
1085 } |
1150 } |
1367 supports_sse4_2() && supports_ht()) { // Nehalem based cpus |
1432 supports_sse4_2() && supports_ht()) { // Nehalem based cpus |
1368 FLAG_SET_DEFAULT(AllocatePrefetchLines, 4); |
1433 FLAG_SET_DEFAULT(AllocatePrefetchLines, 4); |
1369 } |
1434 } |
1370 #ifdef COMPILER2 |
1435 #ifdef COMPILER2 |
1371 if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) { |
1436 if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) { |
|
1437 FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
|
1438 } |
|
1439 #endif |
|
1440 } |
|
1441 |
|
1442 if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) { |
|
1443 #ifdef COMPILER2 |
|
1444 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
1372 FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
1445 FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
1373 } |
1446 } |
1374 #endif |
1447 #endif |
1375 } |
1448 } |
1376 |
1449 |