430 XMMRegister as_xmm_float_reg() const; |
430 XMMRegister as_xmm_float_reg() const; |
431 XMMRegister as_xmm_double_reg() const; |
431 XMMRegister as_xmm_double_reg() const; |
432 // for compatibility with RInfo |
432 // for compatibility with RInfo |
433 int fpu () const { return lo_reg_half(); } |
433 int fpu () const { return lo_reg_half(); } |
434 #endif // X86 |
434 #endif // X86 |
435 |
435 #if defined(SPARC) || defined(ARM) || defined(PPC) |
436 #ifdef SPARC |
|
437 FloatRegister as_float_reg () const; |
436 FloatRegister as_float_reg () const; |
438 FloatRegister as_double_reg () const; |
437 FloatRegister as_double_reg () const; |
439 #endif |
438 #endif |
440 |
439 |
441 jint as_jint() const { return as_constant_ptr()->as_jint(); } |
440 jint as_jint() const { return as_constant_ptr()->as_jint(); } |
517 , _index(LIR_OprDesc::illegalOpr()) |
516 , _index(LIR_OprDesc::illegalOpr()) |
518 , _scale(times_1) |
517 , _scale(times_1) |
519 , _type(type) |
518 , _type(type) |
520 , _disp(0) { verify(); } |
519 , _disp(0) { verify(); } |
521 |
520 |
522 #ifdef X86 |
521 #if defined(X86) || defined(ARM) |
523 LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type): |
522 LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type): |
524 _base(base) |
523 _base(base) |
525 , _index(index) |
524 , _index(index) |
526 , _scale(scale) |
525 , _scale(scale) |
527 , _type(type) |
526 , _type(type) |
528 , _disp(disp) { verify(); } |
527 , _disp(disp) { verify(); } |
529 #endif // X86 |
528 #endif // X86 || ARM |
530 |
529 |
531 LIR_Opr base() const { return _base; } |
530 LIR_Opr base() const { return _base; } |
532 LIR_Opr index() const { return _index; } |
531 LIR_Opr index() const { return _index; } |
533 Scale scale() const { return _scale; } |
532 Scale scale() const { return _scale; } |
534 intx disp() const { return _disp; } |
533 intx disp() const { return _disp; } |
564 |
563 |
565 static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
564 static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
566 LIR_OprDesc::float_type | |
565 LIR_OprDesc::float_type | |
567 LIR_OprDesc::fpu_register | |
566 LIR_OprDesc::fpu_register | |
568 LIR_OprDesc::single_size); } |
567 LIR_OprDesc::single_size); } |
569 |
568 #if defined(ARM) |
|
569 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); } |
|
570 static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | LIR_OprDesc::float_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); } |
|
571 static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size); } |
|
572 #endif |
570 #ifdef SPARC |
573 #ifdef SPARC |
571 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) | |
574 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) | |
572 (reg2 << LIR_OprDesc::reg2_shift) | |
575 (reg2 << LIR_OprDesc::reg2_shift) | |
573 LIR_OprDesc::double_type | |
576 LIR_OprDesc::double_type | |
574 LIR_OprDesc::fpu_register | |
577 LIR_OprDesc::fpu_register | |
591 LIR_OprDesc::double_type | |
594 LIR_OprDesc::double_type | |
592 LIR_OprDesc::fpu_register | |
595 LIR_OprDesc::fpu_register | |
593 LIR_OprDesc::double_size | |
596 LIR_OprDesc::double_size | |
594 LIR_OprDesc::is_xmm_mask); } |
597 LIR_OprDesc::is_xmm_mask); } |
595 #endif // X86 |
598 #endif // X86 |
596 |
599 #ifdef PPC |
|
600 static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
|
601 (reg << LIR_OprDesc::reg2_shift) | |
|
602 LIR_OprDesc::double_type | |
|
603 LIR_OprDesc::fpu_register | |
|
604 LIR_OprDesc::double_size); } |
|
605 static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | |
|
606 LIR_OprDesc::float_type | |
|
607 LIR_OprDesc::cpu_register | |
|
608 LIR_OprDesc::single_size); } |
|
609 static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg2 << LIR_OprDesc::reg1_shift) | |
|
610 (reg1 << LIR_OprDesc::reg2_shift) | |
|
611 LIR_OprDesc::double_type | |
|
612 LIR_OprDesc::cpu_register | |
|
613 LIR_OprDesc::double_size); } |
|
614 #endif // PPC |
597 |
615 |
598 static LIR_Opr virtual_register(int index, BasicType type) { |
616 static LIR_Opr virtual_register(int index, BasicType type) { |
599 LIR_Opr res; |
617 LIR_Opr res; |
600 switch (type) { |
618 switch (type) { |
601 case T_OBJECT: // fall through |
619 case T_OBJECT: // fall through |
621 LIR_OprDesc::cpu_register | |
639 LIR_OprDesc::cpu_register | |
622 LIR_OprDesc::double_size | |
640 LIR_OprDesc::double_size | |
623 LIR_OprDesc::virtual_mask); |
641 LIR_OprDesc::virtual_mask); |
624 break; |
642 break; |
625 |
643 |
|
644 #ifdef __SOFTFP__ |
|
645 case T_FLOAT: |
|
646 res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
|
647 LIR_OprDesc::float_type | |
|
648 LIR_OprDesc::cpu_register | |
|
649 LIR_OprDesc::single_size | |
|
650 LIR_OprDesc::virtual_mask); |
|
651 break; |
|
652 case T_DOUBLE: |
|
653 res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
|
654 LIR_OprDesc::double_type | |
|
655 LIR_OprDesc::cpu_register | |
|
656 LIR_OprDesc::double_size | |
|
657 LIR_OprDesc::virtual_mask); |
|
658 break; |
|
659 #else // __SOFTFP__ |
626 case T_FLOAT: |
660 case T_FLOAT: |
627 res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
661 res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
628 LIR_OprDesc::float_type | |
662 LIR_OprDesc::float_type | |
629 LIR_OprDesc::fpu_register | |
663 LIR_OprDesc::fpu_register | |
630 LIR_OprDesc::single_size | |
664 LIR_OprDesc::single_size | |
648 assert(index >= LIR_OprDesc::vreg_base, "must start at vreg_base"); |
682 assert(index >= LIR_OprDesc::vreg_base, "must start at vreg_base"); |
649 assert(index <= (max_jint >> LIR_OprDesc::data_shift), "index is too big"); |
683 assert(index <= (max_jint >> LIR_OprDesc::data_shift), "index is too big"); |
650 |
684 |
651 // old-style calculation; check if old and new method are equal |
685 // old-style calculation; check if old and new method are equal |
652 LIR_OprDesc::OprType t = as_OprType(type); |
686 LIR_OprDesc::OprType t = as_OprType(type); |
|
687 #ifdef __SOFTFP__ |
|
688 LIR_Opr old_res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | |
|
689 t | |
|
690 LIR_OprDesc::cpu_register | |
|
691 LIR_OprDesc::size_for(type) | LIR_OprDesc::virtual_mask); |
|
692 #else // __SOFTFP__ |
653 LIR_Opr old_res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | t | |
693 LIR_Opr old_res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) | t | |
654 ((type == T_FLOAT || type == T_DOUBLE) ? LIR_OprDesc::fpu_register : LIR_OprDesc::cpu_register) | |
694 ((type == T_FLOAT || type == T_DOUBLE) ? LIR_OprDesc::fpu_register : LIR_OprDesc::cpu_register) | |
655 LIR_OprDesc::size_for(type) | LIR_OprDesc::virtual_mask); |
695 LIR_OprDesc::size_for(type) | LIR_OprDesc::virtual_mask); |
656 assert(res == old_res, "old and new method not equal"); |
696 assert(res == old_res, "old and new method not equal"); |
657 #endif |
697 #endif // __SOFTFP__ |
|
698 #endif // ASSERT |
658 |
699 |
659 return res; |
700 return res; |
660 } |
701 } |
661 |
702 |
662 // 'index' is computed by FrameMap::local_stack_pos(index); do not use other parameters as |
703 // 'index' is computed by FrameMap::local_stack_pos(index); do not use other parameters as |
1304 friend class LIR_OpVisitState; |
1345 friend class LIR_OpVisitState; |
1305 |
1346 |
1306 private: |
1347 private: |
1307 Bytecodes::Code _bytecode; |
1348 Bytecodes::Code _bytecode; |
1308 ConversionStub* _stub; |
1349 ConversionStub* _stub; |
|
1350 #ifdef PPC |
|
1351 LIR_Opr _tmp1; |
|
1352 LIR_Opr _tmp2; |
|
1353 #endif |
1309 |
1354 |
1310 public: |
1355 public: |
1311 LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub) |
1356 LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub) |
1312 : LIR_Op1(lir_convert, opr, result) |
1357 : LIR_Op1(lir_convert, opr, result) |
1313 , _stub(stub) |
1358 , _stub(stub) |
|
1359 #ifdef PPC |
|
1360 , _tmp1(LIR_OprDesc::illegalOpr()) |
|
1361 , _tmp2(LIR_OprDesc::illegalOpr()) |
|
1362 #endif |
1314 , _bytecode(code) {} |
1363 , _bytecode(code) {} |
|
1364 |
|
1365 #ifdef PPC |
|
1366 LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub |
|
1367 ,LIR_Opr tmp1, LIR_Opr tmp2) |
|
1368 : LIR_Op1(lir_convert, opr, result) |
|
1369 , _stub(stub) |
|
1370 , _tmp1(tmp1) |
|
1371 , _tmp2(tmp2) |
|
1372 , _bytecode(code) {} |
|
1373 #endif |
1315 |
1374 |
1316 Bytecodes::Code bytecode() const { return _bytecode; } |
1375 Bytecodes::Code bytecode() const { return _bytecode; } |
1317 ConversionStub* stub() const { return _stub; } |
1376 ConversionStub* stub() const { return _stub; } |
|
1377 #ifdef PPC |
|
1378 LIR_Opr tmp1() const { return _tmp1; } |
|
1379 LIR_Opr tmp2() const { return _tmp2; } |
|
1380 #endif |
1318 |
1381 |
1319 virtual void emit_code(LIR_Assembler* masm); |
1382 virtual void emit_code(LIR_Assembler* masm); |
1320 virtual LIR_OpConvert* as_OpConvert() { return this; } |
1383 virtual LIR_OpConvert* as_OpConvert() { return this; } |
1321 virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
1384 virtual void print_instr(outputStream* out) const PRODUCT_RETURN; |
1322 |
1385 |
1500 BasicType type() const { return _type; } |
1563 BasicType type() const { return _type; } |
1501 LIR_Opr tmp_opr() const { return _tmp; } |
1564 LIR_Opr tmp_opr() const { return _tmp; } |
1502 LIR_Condition condition() const { |
1565 LIR_Condition condition() const { |
1503 assert(code() == lir_cmp || code() == lir_cmove, "only valid for cmp and cmove"); return _condition; |
1566 assert(code() == lir_cmp || code() == lir_cmove, "only valid for cmp and cmove"); return _condition; |
1504 } |
1567 } |
|
1568 void set_condition(LIR_Condition condition) { |
|
1569 assert(code() == lir_cmp || code() == lir_cmove, "only valid for cmp and cmove"); _condition = condition; |
|
1570 } |
1505 |
1571 |
1506 void set_fpu_stack_size(int size) { _fpu_stack_size = size; } |
1572 void set_fpu_stack_size(int size) { _fpu_stack_size = size; } |
1507 int fpu_stack_size() const { return _fpu_stack_size; } |
1573 int fpu_stack_size() const { return _fpu_stack_size; } |
1508 |
1574 |
1509 void set_in_opr1(LIR_Opr opr) { _opr1 = opr; } |
1575 void set_in_opr1(LIR_Opr opr) { _opr1 = opr; } |
1648 LIR_Opr _new_value; |
1714 LIR_Opr _new_value; |
1649 LIR_Opr _tmp1; |
1715 LIR_Opr _tmp1; |
1650 LIR_Opr _tmp2; |
1716 LIR_Opr _tmp2; |
1651 |
1717 |
1652 public: |
1718 public: |
1653 LIR_OpCompareAndSwap(LIR_Code code, LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) |
1719 LIR_OpCompareAndSwap(LIR_Code code, LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
1654 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) // no result, no info |
1720 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) |
|
1721 : LIR_Op(code, result, NULL) // no result, no info |
1655 , _addr(addr) |
1722 , _addr(addr) |
1656 , _cmp_value(cmp_value) |
1723 , _cmp_value(cmp_value) |
1657 , _new_value(new_value) |
1724 , _new_value(new_value) |
1658 , _tmp1(t1) |
1725 , _tmp1(t1) |
1659 , _tmp2(t2) { } |
1726 , _tmp2(t2) { } |
1830 |
1897 |
1831 void return_op(LIR_Opr result) { append(new LIR_Op1(lir_return, result)); } |
1898 void return_op(LIR_Opr result) { append(new LIR_Op1(lir_return, result)); } |
1832 |
1899 |
1833 void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); } |
1900 void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); } |
1834 |
1901 |
|
1902 #ifdef PPC |
|
1903 void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_OpConvert(code, left, dst, NULL, tmp1, tmp2)); } |
|
1904 #endif |
1835 void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); } |
1905 void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); } |
1836 |
1906 |
1837 void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and, left, right, dst)); } |
1907 void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and, left, right, dst)); } |
1838 void logical_or (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_or, left, right, dst)); } |
1908 void logical_or (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_or, left, right, dst)); } |
1839 void logical_xor (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_xor, left, right, dst)); } |
1909 void logical_xor (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_xor, left, right, dst)); } |
1865 |
1935 |
1866 void cmove(LIR_Condition condition, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst) { |
1936 void cmove(LIR_Condition condition, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst) { |
1867 append(new LIR_Op2(lir_cmove, condition, src1, src2, dst)); |
1937 append(new LIR_Op2(lir_cmove, condition, src1, src2, dst)); |
1868 } |
1938 } |
1869 |
1939 |
1870 void cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2); |
1940 void cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
1871 void cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2); |
1941 LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr); |
1872 void cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2); |
1942 void cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
|
1943 LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr); |
|
1944 void cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
|
1945 LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr); |
1873 |
1946 |
1874 void abs (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_abs , from, tmp, to)); } |
1947 void abs (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_abs , from, tmp, to)); } |
1875 void sqrt(LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_sqrt, from, tmp, to)); } |
1948 void sqrt(LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_sqrt, from, tmp, to)); } |
1876 void log (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_log, from, LIR_OprFact::illegalOpr, to, tmp)); } |
1949 void log (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_log, from, LIR_OprFact::illegalOpr, to, tmp)); } |
1877 void log10 (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_log10, from, LIR_OprFact::illegalOpr, to, tmp)); } |
1950 void log10 (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_log10, from, LIR_OprFact::illegalOpr, to, tmp)); } |
1948 LIR_OprList* arguments, CodeEmitInfo* info) { |
2021 LIR_OprList* arguments, CodeEmitInfo* info) { |
1949 append(new LIR_OpRTCall(routine, tmp, result, arguments, info)); |
2022 append(new LIR_OpRTCall(routine, tmp, result, arguments, info)); |
1950 } |
2023 } |
1951 |
2024 |
1952 void load_stack_address_monitor(int monitor_ix, LIR_Opr dst) { append(new LIR_Op1(lir_monaddr, LIR_OprFact::intConst(monitor_ix), dst)); } |
2025 void load_stack_address_monitor(int monitor_ix, LIR_Opr dst) { append(new LIR_Op1(lir_monaddr, LIR_OprFact::intConst(monitor_ix), dst)); } |
1953 void unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, CodeStub* stub); |
2026 void unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub); |
1954 void lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info); |
2027 void lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info); |
1955 |
2028 |
1956 void set_24bit_fpu() { append(new LIR_Op0(lir_24bit_FPU )); } |
2029 void set_24bit_fpu() { append(new LIR_Op0(lir_24bit_FPU )); } |
1957 void restore_fpu() { append(new LIR_Op0(lir_reset_FPU )); } |
2030 void restore_fpu() { append(new LIR_Op0(lir_reset_FPU )); } |
1958 void breakpoint() { append(new LIR_Op0(lir_breakpoint)); } |
2031 void breakpoint() { append(new LIR_Op0(lir_breakpoint)); } |