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1 /* |
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2 * Copyright 1999-2006 Sun Microsystems, Inc. All Rights Reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
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20 * CA 95054 USA or visit www.sun.com if you need additional information or |
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21 * have any questions. |
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22 * |
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23 */ |
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24 |
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25 # include "incls/_precompiled.incl" |
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26 # include "incls/_c1_FrameMap_sparc.cpp.incl" |
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27 |
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28 |
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29 const int FrameMap::pd_c_runtime_reserved_arg_size = 7; |
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30 |
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31 |
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32 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) { |
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33 LIR_Opr opr = LIR_OprFact::illegalOpr; |
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34 VMReg r_1 = reg->first(); |
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35 VMReg r_2 = reg->second(); |
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36 if (r_1->is_stack()) { |
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37 // Convert stack slot to an SP offset |
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38 // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value |
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39 // so we must add it in here. |
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40 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; |
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41 opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type)); |
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42 } else if (r_1->is_Register()) { |
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43 Register reg = r_1->as_Register(); |
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44 if (outgoing) { |
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45 assert(!reg->is_in(), "should be using I regs"); |
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46 } else { |
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47 assert(!reg->is_out(), "should be using O regs"); |
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48 } |
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49 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { |
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50 opr = as_long_opr(reg); |
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51 } else if (type == T_OBJECT || type == T_ARRAY) { |
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52 opr = as_oop_opr(reg); |
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53 } else { |
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54 opr = as_opr(reg); |
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55 } |
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56 } else if (r_1->is_FloatRegister()) { |
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57 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); |
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58 FloatRegister f = r_1->as_FloatRegister(); |
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59 if (type == T_DOUBLE) { |
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60 opr = as_double_opr(f); |
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61 } else { |
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62 opr = as_float_opr(f); |
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63 } |
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64 } |
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65 return opr; |
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66 } |
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67 |
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68 // FrameMap |
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69 //-------------------------------------------------------- |
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70 |
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71 FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs]; |
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72 |
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73 // some useful constant RInfo's: |
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74 LIR_Opr FrameMap::in_long_opr; |
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75 LIR_Opr FrameMap::out_long_opr; |
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76 |
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77 LIR_Opr FrameMap::F0_opr; |
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78 LIR_Opr FrameMap::F0_double_opr; |
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79 |
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80 LIR_Opr FrameMap::G0_opr; |
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81 LIR_Opr FrameMap::G1_opr; |
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82 LIR_Opr FrameMap::G2_opr; |
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83 LIR_Opr FrameMap::G3_opr; |
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84 LIR_Opr FrameMap::G4_opr; |
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85 LIR_Opr FrameMap::G5_opr; |
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86 LIR_Opr FrameMap::G6_opr; |
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87 LIR_Opr FrameMap::G7_opr; |
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88 LIR_Opr FrameMap::O0_opr; |
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89 LIR_Opr FrameMap::O1_opr; |
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90 LIR_Opr FrameMap::O2_opr; |
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91 LIR_Opr FrameMap::O3_opr; |
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92 LIR_Opr FrameMap::O4_opr; |
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93 LIR_Opr FrameMap::O5_opr; |
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94 LIR_Opr FrameMap::O6_opr; |
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95 LIR_Opr FrameMap::O7_opr; |
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96 LIR_Opr FrameMap::L0_opr; |
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97 LIR_Opr FrameMap::L1_opr; |
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98 LIR_Opr FrameMap::L2_opr; |
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99 LIR_Opr FrameMap::L3_opr; |
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100 LIR_Opr FrameMap::L4_opr; |
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101 LIR_Opr FrameMap::L5_opr; |
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102 LIR_Opr FrameMap::L6_opr; |
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103 LIR_Opr FrameMap::L7_opr; |
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104 LIR_Opr FrameMap::I0_opr; |
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105 LIR_Opr FrameMap::I1_opr; |
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106 LIR_Opr FrameMap::I2_opr; |
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107 LIR_Opr FrameMap::I3_opr; |
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108 LIR_Opr FrameMap::I4_opr; |
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109 LIR_Opr FrameMap::I5_opr; |
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110 LIR_Opr FrameMap::I6_opr; |
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111 LIR_Opr FrameMap::I7_opr; |
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112 |
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113 LIR_Opr FrameMap::G0_oop_opr; |
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114 LIR_Opr FrameMap::G1_oop_opr; |
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115 LIR_Opr FrameMap::G2_oop_opr; |
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116 LIR_Opr FrameMap::G3_oop_opr; |
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117 LIR_Opr FrameMap::G4_oop_opr; |
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118 LIR_Opr FrameMap::G5_oop_opr; |
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119 LIR_Opr FrameMap::G6_oop_opr; |
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120 LIR_Opr FrameMap::G7_oop_opr; |
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121 LIR_Opr FrameMap::O0_oop_opr; |
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122 LIR_Opr FrameMap::O1_oop_opr; |
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123 LIR_Opr FrameMap::O2_oop_opr; |
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124 LIR_Opr FrameMap::O3_oop_opr; |
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125 LIR_Opr FrameMap::O4_oop_opr; |
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126 LIR_Opr FrameMap::O5_oop_opr; |
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127 LIR_Opr FrameMap::O6_oop_opr; |
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128 LIR_Opr FrameMap::O7_oop_opr; |
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129 LIR_Opr FrameMap::L0_oop_opr; |
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130 LIR_Opr FrameMap::L1_oop_opr; |
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131 LIR_Opr FrameMap::L2_oop_opr; |
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132 LIR_Opr FrameMap::L3_oop_opr; |
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133 LIR_Opr FrameMap::L4_oop_opr; |
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134 LIR_Opr FrameMap::L5_oop_opr; |
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135 LIR_Opr FrameMap::L6_oop_opr; |
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136 LIR_Opr FrameMap::L7_oop_opr; |
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137 LIR_Opr FrameMap::I0_oop_opr; |
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138 LIR_Opr FrameMap::I1_oop_opr; |
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139 LIR_Opr FrameMap::I2_oop_opr; |
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140 LIR_Opr FrameMap::I3_oop_opr; |
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141 LIR_Opr FrameMap::I4_oop_opr; |
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142 LIR_Opr FrameMap::I5_oop_opr; |
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143 LIR_Opr FrameMap::I6_oop_opr; |
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144 LIR_Opr FrameMap::I7_oop_opr; |
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145 |
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146 LIR_Opr FrameMap::SP_opr; |
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147 LIR_Opr FrameMap::FP_opr; |
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148 |
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149 LIR_Opr FrameMap::Oexception_opr; |
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150 LIR_Opr FrameMap::Oissuing_pc_opr; |
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151 |
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152 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; |
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153 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; |
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154 |
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155 |
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156 FloatRegister FrameMap::nr2floatreg (int rnr) { |
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157 assert(_init_done, "tables not initialized"); |
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158 debug_only(fpu_range_check(rnr);) |
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159 return _fpu_regs[rnr]; |
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160 } |
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161 |
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162 |
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163 // returns true if reg could be smashed by a callee. |
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164 bool FrameMap::is_caller_save_register (LIR_Opr reg) { |
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165 if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; } |
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166 if (reg->is_double_cpu()) { |
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167 return is_caller_save_register(reg->as_register_lo()) || |
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168 is_caller_save_register(reg->as_register_hi()); |
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169 } |
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170 return is_caller_save_register(reg->as_register()); |
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171 } |
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172 |
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173 |
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174 NEEDS_CLEANUP // once the new calling convention is enabled, we no |
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175 // longer need to treat I5, I4 and L0 specially |
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176 // Because the interpreter destroys caller's I5, I4 and L0, |
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177 // we must spill them before doing a Java call as we may land in |
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178 // interpreter. |
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179 bool FrameMap::is_caller_save_register (Register r) { |
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180 return (r->is_global() && (r != G0)) || r->is_out(); |
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181 } |
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182 |
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183 |
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184 void FrameMap::init () { |
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185 if (_init_done) return; |
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186 |
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187 int i=0; |
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188 // Register usage: |
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189 // O6: sp |
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190 // I6: fp |
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191 // I7: return address |
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192 // G0: zero |
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193 // G2: thread |
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194 // G7: not available |
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195 // G6: not available |
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196 /* 0 */ map_register(i++, L0); |
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197 /* 1 */ map_register(i++, L1); |
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198 /* 2 */ map_register(i++, L2); |
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199 /* 3 */ map_register(i++, L3); |
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200 /* 4 */ map_register(i++, L4); |
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201 /* 5 */ map_register(i++, L5); |
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202 /* 6 */ map_register(i++, L6); |
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203 /* 7 */ map_register(i++, L7); |
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204 |
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205 /* 8 */ map_register(i++, I0); |
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206 /* 9 */ map_register(i++, I1); |
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207 /* 10 */ map_register(i++, I2); |
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208 /* 11 */ map_register(i++, I3); |
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209 /* 12 */ map_register(i++, I4); |
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210 /* 13 */ map_register(i++, I5); |
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211 /* 14 */ map_register(i++, O0); |
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212 /* 15 */ map_register(i++, O1); |
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213 /* 16 */ map_register(i++, O2); |
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214 /* 17 */ map_register(i++, O3); |
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215 /* 18 */ map_register(i++, O4); |
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216 /* 19 */ map_register(i++, O5); // <- last register visible in RegAlloc (RegAlloc::nof+cpu_regs) |
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217 /* 20 */ map_register(i++, G1); |
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218 /* 21 */ map_register(i++, G3); |
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219 /* 22 */ map_register(i++, G4); |
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220 /* 23 */ map_register(i++, G5); |
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221 /* 24 */ map_register(i++, G0); |
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222 |
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223 // the following registers are not normally available |
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224 /* 25 */ map_register(i++, O7); |
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225 /* 26 */ map_register(i++, G2); |
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226 /* 27 */ map_register(i++, O6); |
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227 /* 28 */ map_register(i++, I6); |
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228 /* 29 */ map_register(i++, I7); |
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229 /* 30 */ map_register(i++, G6); |
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230 /* 31 */ map_register(i++, G7); |
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231 assert(i == nof_cpu_regs, "number of CPU registers"); |
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232 |
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233 for (i = 0; i < nof_fpu_regs; i++) { |
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234 _fpu_regs[i] = as_FloatRegister(i); |
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235 } |
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236 |
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237 _init_done = true; |
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238 |
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239 in_long_opr = as_long_opr(I0); |
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240 out_long_opr = as_long_opr(O0); |
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241 |
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242 G0_opr = as_opr(G0); |
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243 G1_opr = as_opr(G1); |
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244 G2_opr = as_opr(G2); |
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245 G3_opr = as_opr(G3); |
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246 G4_opr = as_opr(G4); |
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247 G5_opr = as_opr(G5); |
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248 G6_opr = as_opr(G6); |
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249 G7_opr = as_opr(G7); |
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250 O0_opr = as_opr(O0); |
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251 O1_opr = as_opr(O1); |
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252 O2_opr = as_opr(O2); |
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253 O3_opr = as_opr(O3); |
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254 O4_opr = as_opr(O4); |
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255 O5_opr = as_opr(O5); |
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256 O6_opr = as_opr(O6); |
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257 O7_opr = as_opr(O7); |
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258 L0_opr = as_opr(L0); |
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259 L1_opr = as_opr(L1); |
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260 L2_opr = as_opr(L2); |
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261 L3_opr = as_opr(L3); |
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262 L4_opr = as_opr(L4); |
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263 L5_opr = as_opr(L5); |
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264 L6_opr = as_opr(L6); |
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265 L7_opr = as_opr(L7); |
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266 I0_opr = as_opr(I0); |
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267 I1_opr = as_opr(I1); |
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268 I2_opr = as_opr(I2); |
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269 I3_opr = as_opr(I3); |
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270 I4_opr = as_opr(I4); |
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271 I5_opr = as_opr(I5); |
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272 I6_opr = as_opr(I6); |
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273 I7_opr = as_opr(I7); |
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274 |
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275 G0_oop_opr = as_oop_opr(G0); |
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276 G1_oop_opr = as_oop_opr(G1); |
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277 G2_oop_opr = as_oop_opr(G2); |
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278 G3_oop_opr = as_oop_opr(G3); |
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279 G4_oop_opr = as_oop_opr(G4); |
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280 G5_oop_opr = as_oop_opr(G5); |
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281 G6_oop_opr = as_oop_opr(G6); |
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282 G7_oop_opr = as_oop_opr(G7); |
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283 O0_oop_opr = as_oop_opr(O0); |
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284 O1_oop_opr = as_oop_opr(O1); |
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285 O2_oop_opr = as_oop_opr(O2); |
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286 O3_oop_opr = as_oop_opr(O3); |
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287 O4_oop_opr = as_oop_opr(O4); |
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288 O5_oop_opr = as_oop_opr(O5); |
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289 O6_oop_opr = as_oop_opr(O6); |
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290 O7_oop_opr = as_oop_opr(O7); |
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291 L0_oop_opr = as_oop_opr(L0); |
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292 L1_oop_opr = as_oop_opr(L1); |
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293 L2_oop_opr = as_oop_opr(L2); |
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294 L3_oop_opr = as_oop_opr(L3); |
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295 L4_oop_opr = as_oop_opr(L4); |
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296 L5_oop_opr = as_oop_opr(L5); |
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297 L6_oop_opr = as_oop_opr(L6); |
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298 L7_oop_opr = as_oop_opr(L7); |
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299 I0_oop_opr = as_oop_opr(I0); |
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300 I1_oop_opr = as_oop_opr(I1); |
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301 I2_oop_opr = as_oop_opr(I2); |
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302 I3_oop_opr = as_oop_opr(I3); |
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303 I4_oop_opr = as_oop_opr(I4); |
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304 I5_oop_opr = as_oop_opr(I5); |
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305 I6_oop_opr = as_oop_opr(I6); |
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306 I7_oop_opr = as_oop_opr(I7); |
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307 |
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308 FP_opr = as_pointer_opr(FP); |
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309 SP_opr = as_pointer_opr(SP); |
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310 |
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311 F0_opr = as_float_opr(F0); |
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312 F0_double_opr = as_double_opr(F0); |
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313 |
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314 Oexception_opr = as_oop_opr(Oexception); |
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315 Oissuing_pc_opr = as_opr(Oissuing_pc); |
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316 |
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317 _caller_save_cpu_regs[0] = FrameMap::O0_opr; |
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318 _caller_save_cpu_regs[1] = FrameMap::O1_opr; |
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319 _caller_save_cpu_regs[2] = FrameMap::O2_opr; |
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320 _caller_save_cpu_regs[3] = FrameMap::O3_opr; |
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321 _caller_save_cpu_regs[4] = FrameMap::O4_opr; |
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322 _caller_save_cpu_regs[5] = FrameMap::O5_opr; |
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323 for (int i = 0; i < nof_caller_save_fpu_regs; i++) { |
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324 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i); |
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325 } |
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326 } |
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327 |
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328 |
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329 Address FrameMap::make_new_address(ByteSize sp_offset) const { |
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330 return Address(SP, 0, STACK_BIAS + in_bytes(sp_offset)); |
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331 } |
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332 |
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333 |
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334 VMReg FrameMap::fpu_regname (int n) { |
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335 return as_FloatRegister(n)->as_VMReg(); |
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336 } |
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337 |
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338 |
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339 LIR_Opr FrameMap::stack_pointer() { |
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340 return SP_opr; |
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341 } |
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342 |
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343 |
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344 bool FrameMap::validate_frame() { |
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345 int max_offset = in_bytes(framesize_in_bytes()); |
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346 int java_index = 0; |
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347 for (int i = 0; i < _incoming_arguments->length(); i++) { |
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348 LIR_Opr opr = _incoming_arguments->at(i); |
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349 if (opr->is_stack()) { |
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350 max_offset = MAX2(_argument_locations->at(java_index), max_offset); |
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351 } |
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352 java_index += type2size[opr->type()]; |
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353 } |
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354 return Assembler::is_simm13(max_offset + STACK_BIAS); |
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355 } |