src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.hotspot.aarch64/src/org/graalvm/compiler/hotspot/aarch64/AArch64HotSpotLIRGenerator.java
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82 import org.graalvm.compiler.lir.aarch64.AArch64Move; |
82 import org.graalvm.compiler.lir.aarch64.AArch64Move; |
83 import org.graalvm.compiler.lir.aarch64.AArch64Move.StoreOp; |
83 import org.graalvm.compiler.lir.aarch64.AArch64Move.StoreOp; |
84 import org.graalvm.compiler.lir.aarch64.AArch64PrefetchOp; |
84 import org.graalvm.compiler.lir.aarch64.AArch64PrefetchOp; |
85 import org.graalvm.compiler.lir.aarch64.AArch64RestoreRegistersOp; |
85 import org.graalvm.compiler.lir.aarch64.AArch64RestoreRegistersOp; |
86 import org.graalvm.compiler.lir.aarch64.AArch64SaveRegistersOp; |
86 import org.graalvm.compiler.lir.aarch64.AArch64SaveRegistersOp; |
87 import org.graalvm.compiler.lir.aarch64.AArch64ZeroMemoryOp; |
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88 import org.graalvm.compiler.lir.gen.LIRGenerationResult; |
87 import org.graalvm.compiler.lir.gen.LIRGenerationResult; |
89 import org.graalvm.compiler.options.OptionValues; |
88 import org.graalvm.compiler.options.OptionValues; |
90 |
89 |
91 import jdk.vm.ci.aarch64.AArch64; |
90 import jdk.vm.ci.aarch64.AArch64; |
92 import jdk.vm.ci.aarch64.AArch64Kind; |
91 import jdk.vm.ci.aarch64.AArch64Kind; |
542 public LIRInstruction createZapArgumentSpace(StackSlot[] zappedStack, JavaConstant[] zapValues) { |
541 public LIRInstruction createZapArgumentSpace(StackSlot[] zappedStack, JavaConstant[] zapValues) { |
543 throw GraalError.unimplemented(); |
542 throw GraalError.unimplemented(); |
544 } |
543 } |
545 |
544 |
546 @Override |
545 @Override |
547 public void emitZeroMemory(Value address, Value length) { |
546 public void emitZeroMemory(Value address, Value length, boolean isAligned) { |
548 int dczidValue = config.psrInfoDczidValue; |
547 int dczidValue = config.psrInfoDczidValue; |
549 EnumSet<AArch64.Flag> flags = ((AArch64) target().arch).getFlags(); |
548 EnumSet<AArch64.Flag> flags = ((AArch64) target().arch).getFlags(); |
550 |
549 |
551 // ARMv8-A architecture reference manual D12.2.35 Data Cache Zero ID register says: |
550 // ARMv8-A architecture reference manual D12.2.35 Data Cache Zero ID register says: |
552 // * BS, bits [3:0] indicate log2 of the DC ZVA block size in (4-byte) words. |
551 // * BS, bits [3:0] indicate log2 of the DC ZVA block size in (4-byte) words. |
561 // could be different on different AArch64 CPU implementations. |
560 // could be different on different AArch64 CPU implementations. |
562 if (GraalOptions.ImmutableCode.getValue(getResult().getLIR().getOptions())) { |
561 if (GraalOptions.ImmutableCode.getValue(getResult().getLIR().getOptions())) { |
563 useDcZva = false; |
562 useDcZva = false; |
564 } |
563 } |
565 |
564 |
566 // Value address is 8-byte aligned; Value length is multiple of 8. |
565 emitZeroMemory(address, length, isAligned, useDcZva, zvaLength); |
567 append(new AArch64ZeroMemoryOp(asAllocatable(address), asAllocatable(length), useDcZva, zvaLength)); |
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568 } |
566 } |
569 } |
567 } |