hotspot/src/share/vm/opto/divnode.cpp
changeset 1432 44f076e3d2a4
parent 1067 f82e0a8cd438
child 1436 6869d58f4f58
equal deleted inserted replaced
1404:4a969f79e3e6 1432:44f076e3d2a4
   108       // we don't need to round a positive dividend
   108       // we don't need to round a positive dividend
   109       needs_rounding = false;
   109       needs_rounding = false;
   110     } else if( dividend->Opcode() == Op_AndI ) {
   110     } else if( dividend->Opcode() == Op_AndI ) {
   111       // An AND mask of sufficient size clears the low bits and
   111       // An AND mask of sufficient size clears the low bits and
   112       // I can avoid rounding.
   112       // I can avoid rounding.
   113       const TypeInt *andconi = phase->type( dividend->in(2) )->isa_int();
   113       const TypeInt *andconi_t = phase->type( dividend->in(2) )->isa_int();
   114       if( andconi && andconi->is_con(-d) ) {
   114       if( andconi_t && andconi_t->is_con() ) {
   115         dividend = dividend->in(1);
   115         jint andconi = andconi_t->get_con();
   116         needs_rounding = false;
   116         if( andconi < 0 && is_power_of_2(-andconi) && (-andconi) >= d ) {
       
   117           dividend = dividend->in(1);
       
   118           needs_rounding = false;
       
   119         }
   117       }
   120       }
   118     }
   121     }
   119 
   122 
   120     // Add rounding to the shift to handle the sign bit
   123     // Add rounding to the shift to handle the sign bit
   121     int l = log2_intptr(d-1)+1;
   124     int l = log2_intptr(d-1)+1;
   314       // we don't need to round a positive dividend
   317       // we don't need to round a positive dividend
   315       needs_rounding = false;
   318       needs_rounding = false;
   316     } else if( dividend->Opcode() == Op_AndL ) {
   319     } else if( dividend->Opcode() == Op_AndL ) {
   317       // An AND mask of sufficient size clears the low bits and
   320       // An AND mask of sufficient size clears the low bits and
   318       // I can avoid rounding.
   321       // I can avoid rounding.
   319       const TypeLong *andconl = phase->type( dividend->in(2) )->isa_long();
   322       const TypeLong *andconl_t = phase->type( dividend->in(2) )->isa_long();
   320       if( andconl && andconl->is_con(-d)) {
   323       if( andconl_t && andconl_t->is_con() ) {
   321         dividend = dividend->in(1);
   324         jlong andconl = andconl_t->get_con();
   322         needs_rounding = false;
   325         if( andconl < 0 && is_power_of_2_long(-andconl) && (-andconl) >= d ) {
       
   326           dividend = dividend->in(1);
       
   327           needs_rounding = false;
       
   328         }
   323       }
   329       }
   324     }
   330     }
   325 
   331 
   326     // Add rounding to the shift to handle the sign bit
   332     // Add rounding to the shift to handle the sign bit
   327     int l = log2_long(d-1)+1;
   333     int l = log2_long(d-1)+1;