3357 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
3357 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
3358 } |
3358 } |
3359 |
3359 |
3360 |
3360 |
3361 // Integer vector arithmetic |
3361 // Integer vector arithmetic |
|
3362 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
3363 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
3364 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
|
3365 emit_int8(0x01); |
|
3366 emit_int8((unsigned char)(0xC0 | encode)); |
|
3367 } |
|
3368 |
|
3369 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
3370 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
3371 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
|
3372 emit_int8(0x02); |
|
3373 emit_int8((unsigned char)(0xC0 | encode)); |
|
3374 } |
|
3375 |
3362 void Assembler::paddb(XMMRegister dst, XMMRegister src) { |
3376 void Assembler::paddb(XMMRegister dst, XMMRegister src) { |
3363 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3377 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3364 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66); |
3378 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66); |
3365 } |
3379 } |
3366 |
3380 |
3375 } |
3389 } |
3376 |
3390 |
3377 void Assembler::paddq(XMMRegister dst, XMMRegister src) { |
3391 void Assembler::paddq(XMMRegister dst, XMMRegister src) { |
3378 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3392 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3379 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66); |
3393 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66); |
|
3394 } |
|
3395 |
|
3396 void Assembler::phaddw(XMMRegister dst, XMMRegister src) { |
|
3397 NOT_LP64(assert(VM_Version::supports_sse3(), "")); |
|
3398 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
|
3399 emit_int8(0x01); |
|
3400 emit_int8((unsigned char)(0xC0 | encode)); |
|
3401 } |
|
3402 |
|
3403 void Assembler::phaddd(XMMRegister dst, XMMRegister src) { |
|
3404 NOT_LP64(assert(VM_Version::supports_sse3(), "")); |
|
3405 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
|
3406 emit_int8(0x02); |
|
3407 emit_int8((unsigned char)(0xC0 | encode)); |
3380 } |
3408 } |
3381 |
3409 |
3382 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
3410 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
3383 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3411 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3384 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
3412 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
3798 int dst_enc = dst->encoding(); |
3826 int dst_enc = dst->encoding(); |
3799 // swap src<->dst for encoding |
3827 // swap src<->dst for encoding |
3800 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
3828 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
3801 emit_int8(0x18); |
3829 emit_int8(0x18); |
3802 emit_operand(dst, src); |
3830 emit_operand(dst, src); |
|
3831 // 0x01 - insert into upper 128 bits |
|
3832 emit_int8(0x01); |
|
3833 } |
|
3834 |
|
3835 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) { |
|
3836 assert(VM_Version::supports_avx(), ""); |
|
3837 bool vector256 = true; |
|
3838 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
|
3839 emit_int8(0x19); |
|
3840 emit_int8((unsigned char)(0xC0 | encode)); |
|
3841 // 0x00 - insert into lower 128 bits |
3803 // 0x01 - insert into upper 128 bits |
3842 // 0x01 - insert into upper 128 bits |
3804 emit_int8(0x01); |
3843 emit_int8(0x01); |
3805 } |
3844 } |
3806 |
3845 |
3807 void Assembler::vextractf128h(Address dst, XMMRegister src) { |
3846 void Assembler::vextractf128h(Address dst, XMMRegister src) { |