8356 instruct vshift4B(vecS dst, vecS src, vecS shift, vecS tmp, rRegI scratch) %{ |
8356 instruct vshift4B(vecS dst, vecS src, vecS shift, vecS tmp, rRegI scratch) %{ |
8357 predicate(UseSSE > 3 && n->as_Vector()->length() == 4); |
8357 predicate(UseSSE > 3 && n->as_Vector()->length() == 4); |
8358 match(Set dst (LShiftVB src shift)); |
8358 match(Set dst (LShiftVB src shift)); |
8359 match(Set dst (RShiftVB src shift)); |
8359 match(Set dst (RShiftVB src shift)); |
8360 match(Set dst (URShiftVB src shift)); |
8360 match(Set dst (URShiftVB src shift)); |
8361 effect(TEMP dst, TEMP tmp, TEMP scratch); |
8361 effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch); |
8362 format %{"vextendbw $tmp,$src\n\t" |
8362 format %{"vextendbw $tmp,$src\n\t" |
8363 "vshiftw $tmp,$shift\n\t" |
8363 "vshiftw $tmp,$shift\n\t" |
8364 "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" |
8364 "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" |
8365 "pand $dst,$tmp\n\t" |
8365 "pand $dst,$tmp\n\t" |
8366 "packuswb $dst,$dst\n\t ! packed4B shift" %} |
8366 "packuswb $dst,$dst\n\t ! packed4B shift" %} |
8379 instruct vshift8B(vecD dst, vecD src, vecS shift, vecD tmp, rRegI scratch) %{ |
8379 instruct vshift8B(vecD dst, vecD src, vecS shift, vecD tmp, rRegI scratch) %{ |
8380 predicate(UseSSE > 3 && n->as_Vector()->length() == 8); |
8380 predicate(UseSSE > 3 && n->as_Vector()->length() == 8); |
8381 match(Set dst (LShiftVB src shift)); |
8381 match(Set dst (LShiftVB src shift)); |
8382 match(Set dst (RShiftVB src shift)); |
8382 match(Set dst (RShiftVB src shift)); |
8383 match(Set dst (URShiftVB src shift)); |
8383 match(Set dst (URShiftVB src shift)); |
8384 effect(TEMP dst, TEMP tmp, TEMP scratch); |
8384 effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch); |
8385 format %{"vextendbw $tmp,$src\n\t" |
8385 format %{"vextendbw $tmp,$src\n\t" |
8386 "vshiftw $tmp,$shift\n\t" |
8386 "vshiftw $tmp,$shift\n\t" |
8387 "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" |
8387 "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" |
8388 "pand $dst,$tmp\n\t" |
8388 "pand $dst,$tmp\n\t" |
8389 "packuswb $dst,$dst\n\t ! packed8B shift" %} |
8389 "packuswb $dst,$dst\n\t ! packed8B shift" %} |
8402 instruct vshift16B(vecX dst, vecX src, vecS shift, vecX tmp1, vecX tmp2, rRegI scratch) %{ |
8402 instruct vshift16B(vecX dst, vecX src, vecS shift, vecX tmp1, vecX tmp2, rRegI scratch) %{ |
8403 predicate(UseSSE > 3 && UseAVX <= 1 && n->as_Vector()->length() == 16); |
8403 predicate(UseSSE > 3 && UseAVX <= 1 && n->as_Vector()->length() == 16); |
8404 match(Set dst (LShiftVB src shift)); |
8404 match(Set dst (LShiftVB src shift)); |
8405 match(Set dst (RShiftVB src shift)); |
8405 match(Set dst (RShiftVB src shift)); |
8406 match(Set dst (URShiftVB src shift)); |
8406 match(Set dst (URShiftVB src shift)); |
8407 effect(TEMP dst, TEMP tmp1, TEMP tmp2, TEMP scratch); |
8407 effect(TEMP dst, USE src, USE shift, TEMP tmp1, TEMP tmp2, TEMP scratch); |
8408 format %{"vextendbw $tmp1,$src\n\t" |
8408 format %{"vextendbw $tmp1,$src\n\t" |
8409 "vshiftw $tmp1,$shift\n\t" |
8409 "vshiftw $tmp1,$shift\n\t" |
8410 "pshufd $tmp2,$src\n\t" |
8410 "pshufd $tmp2,$src\n\t" |
8411 "vextendbw $tmp2,$tmp2\n\t" |
8411 "vextendbw $tmp2,$tmp2\n\t" |
8412 "vshiftw $tmp2,$shift\n\t" |
8412 "vshiftw $tmp2,$shift\n\t" |
8433 instruct vshift16B_avx(vecX dst, vecX src, vecS shift, vecX tmp, rRegI scratch) %{ |
8433 instruct vshift16B_avx(vecX dst, vecX src, vecS shift, vecX tmp, rRegI scratch) %{ |
8434 predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
8434 predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
8435 match(Set dst (LShiftVB src shift)); |
8435 match(Set dst (LShiftVB src shift)); |
8436 match(Set dst (RShiftVB src shift)); |
8436 match(Set dst (RShiftVB src shift)); |
8437 match(Set dst (URShiftVB src shift)); |
8437 match(Set dst (URShiftVB src shift)); |
8438 effect(TEMP dst, TEMP tmp, TEMP scratch); |
8438 effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch); |
8439 format %{"vextendbw $tmp,$src\n\t" |
8439 format %{"vextendbw $tmp,$src\n\t" |
8440 "vshiftw $tmp,$tmp,$shift\n\t" |
8440 "vshiftw $tmp,$tmp,$shift\n\t" |
8441 "vpand $tmp,$tmp,[0x00ff00ff0x00ff00ff]\n\t" |
8441 "vpand $tmp,$tmp,[0x00ff00ff0x00ff00ff]\n\t" |
8442 "vextracti128_high $dst,$tmp\n\t" |
8442 "vextracti128_high $dst,$tmp\n\t" |
8443 "vpackuswb $dst,$tmp,$dst\n\t! packed16B shift" %} |
8443 "vpackuswb $dst,$tmp,$dst\n\t! packed16B shift" %} |
8457 instruct vshift32B_avx(vecY dst, vecY src, vecS shift, vecY tmp, rRegI scratch) %{ |
8457 instruct vshift32B_avx(vecY dst, vecY src, vecS shift, vecY tmp, rRegI scratch) %{ |
8458 predicate(UseAVX > 1 && n->as_Vector()->length() == 32); |
8458 predicate(UseAVX > 1 && n->as_Vector()->length() == 32); |
8459 match(Set dst (LShiftVB src shift)); |
8459 match(Set dst (LShiftVB src shift)); |
8460 match(Set dst (RShiftVB src shift)); |
8460 match(Set dst (RShiftVB src shift)); |
8461 match(Set dst (URShiftVB src shift)); |
8461 match(Set dst (URShiftVB src shift)); |
8462 effect(TEMP dst, TEMP tmp, TEMP scratch); |
8462 effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch); |
8463 format %{"vextracti128_high $tmp,$src\n\t" |
8463 format %{"vextracti128_high $tmp,$src\n\t" |
8464 "vextendbw $tmp,$tmp\n\t" |
8464 "vextendbw $tmp,$tmp\n\t" |
8465 "vextendbw $dst,$src\n\t" |
8465 "vextendbw $dst,$src\n\t" |
8466 "vshiftw $tmp,$tmp,$shift\n\t" |
8466 "vshiftw $tmp,$tmp,$shift\n\t" |
8467 "vshiftw $dst,$dst,$shift\n\t" |
8467 "vshiftw $dst,$dst,$shift\n\t" |
8489 instruct vshift64B_avx(vecZ dst, vecZ src, vecS shift, vecZ tmp1, vecZ tmp2, rRegI scratch) %{ |
8489 instruct vshift64B_avx(vecZ dst, vecZ src, vecS shift, vecZ tmp1, vecZ tmp2, rRegI scratch) %{ |
8490 predicate(UseAVX > 2 && n->as_Vector()->length() == 64); |
8490 predicate(UseAVX > 2 && n->as_Vector()->length() == 64); |
8491 match(Set dst (LShiftVB src shift)); |
8491 match(Set dst (LShiftVB src shift)); |
8492 match(Set dst (RShiftVB src shift)); |
8492 match(Set dst (RShiftVB src shift)); |
8493 match(Set dst (URShiftVB src shift)); |
8493 match(Set dst (URShiftVB src shift)); |
8494 effect(TEMP dst, TEMP tmp1, TEMP tmp2, TEMP scratch); |
8494 effect(TEMP dst, USE src, USE shift, TEMP tmp1, TEMP tmp2, TEMP scratch); |
8495 format %{"vextracti64x4 $tmp1,$src\n\t" |
8495 format %{"vextracti64x4 $tmp1,$src\n\t" |
8496 "vextendbw $tmp1,$tmp1\n\t" |
8496 "vextendbw $tmp1,$tmp1\n\t" |
8497 "vextendbw $tmp2,$src\n\t" |
8497 "vextendbw $tmp2,$src\n\t" |
8498 "vshiftw $tmp1,$tmp1,$shift\n\t" |
8498 "vshiftw $tmp1,$tmp1,$shift\n\t" |
8499 "vshiftw $tmp2,$tmp2,$shift\n\t" |
8499 "vshiftw $tmp2,$tmp2,$shift\n\t" |
8532 instruct vshist2S(vecS dst, vecS src, vecS shift) %{ |
8532 instruct vshist2S(vecS dst, vecS src, vecS shift) %{ |
8533 predicate(n->as_Vector()->length() == 2); |
8533 predicate(n->as_Vector()->length() == 2); |
8534 match(Set dst (LShiftVS src shift)); |
8534 match(Set dst (LShiftVS src shift)); |
8535 match(Set dst (RShiftVS src shift)); |
8535 match(Set dst (RShiftVS src shift)); |
8536 match(Set dst (URShiftVS src shift)); |
8536 match(Set dst (URShiftVS src shift)); |
|
8537 effect(TEMP dst, USE src, USE shift); |
8537 format %{ "vshiftw $dst,$src,$shift\t! shift packed2S" %} |
8538 format %{ "vshiftw $dst,$src,$shift\t! shift packed2S" %} |
8538 ins_encode %{ |
8539 ins_encode %{ |
8539 int opcode = this->as_Mach()->ideal_Opcode(); |
8540 int opcode = this->as_Mach()->ideal_Opcode(); |
8540 if (UseAVX == 0) { |
8541 if (UseAVX == 0) { |
8541 if ($dst$$XMMRegister != $src$$XMMRegister) |
8542 if ($dst$$XMMRegister != $src$$XMMRegister) |
8552 instruct vshift4S(vecD dst, vecD src, vecS shift) %{ |
8553 instruct vshift4S(vecD dst, vecD src, vecS shift) %{ |
8553 predicate(n->as_Vector()->length() == 4); |
8554 predicate(n->as_Vector()->length() == 4); |
8554 match(Set dst (LShiftVS src shift)); |
8555 match(Set dst (LShiftVS src shift)); |
8555 match(Set dst (RShiftVS src shift)); |
8556 match(Set dst (RShiftVS src shift)); |
8556 match(Set dst (URShiftVS src shift)); |
8557 match(Set dst (URShiftVS src shift)); |
|
8558 effect(TEMP dst, USE src, USE shift); |
8557 format %{ "vshiftw $dst,$src,$shift\t! shift packed4S" %} |
8559 format %{ "vshiftw $dst,$src,$shift\t! shift packed4S" %} |
8558 ins_encode %{ |
8560 ins_encode %{ |
8559 int opcode = this->as_Mach()->ideal_Opcode(); |
8561 int opcode = this->as_Mach()->ideal_Opcode(); |
8560 if (UseAVX == 0) { |
8562 if (UseAVX == 0) { |
8561 if ($dst$$XMMRegister != $src$$XMMRegister) |
8563 if ($dst$$XMMRegister != $src$$XMMRegister) |
8573 instruct vshift8S(vecX dst, vecX src, vecS shift) %{ |
8575 instruct vshift8S(vecX dst, vecX src, vecS shift) %{ |
8574 predicate(n->as_Vector()->length() == 8); |
8576 predicate(n->as_Vector()->length() == 8); |
8575 match(Set dst (LShiftVS src shift)); |
8577 match(Set dst (LShiftVS src shift)); |
8576 match(Set dst (RShiftVS src shift)); |
8578 match(Set dst (RShiftVS src shift)); |
8577 match(Set dst (URShiftVS src shift)); |
8579 match(Set dst (URShiftVS src shift)); |
|
8580 effect(TEMP dst, USE src, USE shift); |
8578 format %{ "vshiftw $dst,$src,$shift\t! shift packed8S" %} |
8581 format %{ "vshiftw $dst,$src,$shift\t! shift packed8S" %} |
8579 ins_encode %{ |
8582 ins_encode %{ |
8580 int opcode = this->as_Mach()->ideal_Opcode(); |
8583 int opcode = this->as_Mach()->ideal_Opcode(); |
8581 if (UseAVX == 0) { |
8584 if (UseAVX == 0) { |
8582 if ($dst$$XMMRegister != $src$$XMMRegister) |
8585 if ($dst$$XMMRegister != $src$$XMMRegister) |
8593 instruct vshift16S(vecY dst, vecY src, vecS shift) %{ |
8596 instruct vshift16S(vecY dst, vecY src, vecS shift) %{ |
8594 predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
8597 predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
8595 match(Set dst (LShiftVS src shift)); |
8598 match(Set dst (LShiftVS src shift)); |
8596 match(Set dst (RShiftVS src shift)); |
8599 match(Set dst (RShiftVS src shift)); |
8597 match(Set dst (URShiftVS src shift)); |
8600 match(Set dst (URShiftVS src shift)); |
|
8601 effect(DEF dst, USE src, USE shift); |
8598 format %{ "vshiftw $dst,$src,$shift\t! shift packed16S" %} |
8602 format %{ "vshiftw $dst,$src,$shift\t! shift packed16S" %} |
8599 ins_encode %{ |
8603 ins_encode %{ |
8600 int vector_len = 1; |
8604 int vector_len = 1; |
8601 int opcode = this->as_Mach()->ideal_Opcode(); |
8605 int opcode = this->as_Mach()->ideal_Opcode(); |
8602 __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
8606 __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
8607 instruct vshift32S(vecZ dst, vecZ src, vecS shift) %{ |
8611 instruct vshift32S(vecZ dst, vecZ src, vecS shift) %{ |
8608 predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 32); |
8612 predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 32); |
8609 match(Set dst (LShiftVS src shift)); |
8613 match(Set dst (LShiftVS src shift)); |
8610 match(Set dst (RShiftVS src shift)); |
8614 match(Set dst (RShiftVS src shift)); |
8611 match(Set dst (URShiftVS src shift)); |
8615 match(Set dst (URShiftVS src shift)); |
|
8616 effect(DEF dst, USE src, USE shift); |
8612 format %{ "vshiftw $dst,$src,$shift\t! shift packed32S" %} |
8617 format %{ "vshiftw $dst,$src,$shift\t! shift packed32S" %} |
8613 ins_encode %{ |
8618 ins_encode %{ |
8614 int vector_len = 2; |
8619 int vector_len = 2; |
8615 int opcode = this->as_Mach()->ideal_Opcode(); |
8620 int opcode = this->as_Mach()->ideal_Opcode(); |
8616 __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
8621 __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
8622 instruct vshift2I(vecD dst, vecD src, vecS shift) %{ |
8627 instruct vshift2I(vecD dst, vecD src, vecS shift) %{ |
8623 predicate(n->as_Vector()->length() == 2); |
8628 predicate(n->as_Vector()->length() == 2); |
8624 match(Set dst (LShiftVI src shift)); |
8629 match(Set dst (LShiftVI src shift)); |
8625 match(Set dst (RShiftVI src shift)); |
8630 match(Set dst (RShiftVI src shift)); |
8626 match(Set dst (URShiftVI src shift)); |
8631 match(Set dst (URShiftVI src shift)); |
|
8632 effect(TEMP dst, USE src, USE shift); |
8627 format %{ "vshiftd $dst,$src,$shift\t! shift packed2I" %} |
8633 format %{ "vshiftd $dst,$src,$shift\t! shift packed2I" %} |
8628 ins_encode %{ |
8634 ins_encode %{ |
8629 int opcode = this->as_Mach()->ideal_Opcode(); |
8635 int opcode = this->as_Mach()->ideal_Opcode(); |
8630 if (UseAVX == 0) { |
8636 if (UseAVX == 0) { |
8631 if ($dst$$XMMRegister != $src$$XMMRegister) |
8637 if ($dst$$XMMRegister != $src$$XMMRegister) |
8642 instruct vshift4I(vecX dst, vecX src, vecS shift) %{ |
8648 instruct vshift4I(vecX dst, vecX src, vecS shift) %{ |
8643 predicate(n->as_Vector()->length() == 4); |
8649 predicate(n->as_Vector()->length() == 4); |
8644 match(Set dst (LShiftVI src shift)); |
8650 match(Set dst (LShiftVI src shift)); |
8645 match(Set dst (RShiftVI src shift)); |
8651 match(Set dst (RShiftVI src shift)); |
8646 match(Set dst (URShiftVI src shift)); |
8652 match(Set dst (URShiftVI src shift)); |
|
8653 effect(TEMP dst, USE src, USE shift); |
8647 format %{ "vshiftd $dst,$src,$shift\t! shift packed4I" %} |
8654 format %{ "vshiftd $dst,$src,$shift\t! shift packed4I" %} |
8648 ins_encode %{ |
8655 ins_encode %{ |
8649 int opcode = this->as_Mach()->ideal_Opcode(); |
8656 int opcode = this->as_Mach()->ideal_Opcode(); |
8650 if (UseAVX == 0) { |
8657 if (UseAVX == 0) { |
8651 if ($dst$$XMMRegister != $src$$XMMRegister) |
8658 if ($dst$$XMMRegister != $src$$XMMRegister) |
8662 instruct vshift8I(vecY dst, vecY src, vecS shift) %{ |
8669 instruct vshift8I(vecY dst, vecY src, vecS shift) %{ |
8663 predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
8670 predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
8664 match(Set dst (LShiftVI src shift)); |
8671 match(Set dst (LShiftVI src shift)); |
8665 match(Set dst (RShiftVI src shift)); |
8672 match(Set dst (RShiftVI src shift)); |
8666 match(Set dst (URShiftVI src shift)); |
8673 match(Set dst (URShiftVI src shift)); |
|
8674 effect(DEF dst, USE src, USE shift); |
8667 format %{ "vshiftd $dst,$src,$shift\t! shift packed8I" %} |
8675 format %{ "vshiftd $dst,$src,$shift\t! shift packed8I" %} |
8668 ins_encode %{ |
8676 ins_encode %{ |
8669 int vector_len = 1; |
8677 int vector_len = 1; |
8670 int opcode = this->as_Mach()->ideal_Opcode(); |
8678 int opcode = this->as_Mach()->ideal_Opcode(); |
8671 __ vshiftd(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
8679 __ vshiftd(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
8676 instruct vshift16I(vecZ dst, vecZ src, vecS shift) %{ |
8684 instruct vshift16I(vecZ dst, vecZ src, vecS shift) %{ |
8677 predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
8685 predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
8678 match(Set dst (LShiftVI src shift)); |
8686 match(Set dst (LShiftVI src shift)); |
8679 match(Set dst (RShiftVI src shift)); |
8687 match(Set dst (RShiftVI src shift)); |
8680 match(Set dst (URShiftVI src shift)); |
8688 match(Set dst (URShiftVI src shift)); |
|
8689 effect(DEF dst, USE src, USE shift); |
8681 format %{ "vshiftd $dst,$src,$shift\t! shift packed16I" %} |
8690 format %{ "vshiftd $dst,$src,$shift\t! shift packed16I" %} |
8682 ins_encode %{ |
8691 ins_encode %{ |
8683 int vector_len = 2; |
8692 int vector_len = 2; |
8684 int opcode = this->as_Mach()->ideal_Opcode(); |
8693 int opcode = this->as_Mach()->ideal_Opcode(); |
8685 __ vshiftd(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
8694 __ vshiftd(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
8690 // Longs vector shift |
8699 // Longs vector shift |
8691 instruct vshift2L(vecX dst, vecX src, vecS shift) %{ |
8700 instruct vshift2L(vecX dst, vecX src, vecS shift) %{ |
8692 predicate(n->as_Vector()->length() == 2); |
8701 predicate(n->as_Vector()->length() == 2); |
8693 match(Set dst (LShiftVL src shift)); |
8702 match(Set dst (LShiftVL src shift)); |
8694 match(Set dst (URShiftVL src shift)); |
8703 match(Set dst (URShiftVL src shift)); |
|
8704 effect(TEMP dst, USE src, USE shift); |
8695 format %{ "vshiftq $dst,$src,$shift\t! shift packed2L" %} |
8705 format %{ "vshiftq $dst,$src,$shift\t! shift packed2L" %} |
8696 ins_encode %{ |
8706 ins_encode %{ |
8697 int opcode = this->as_Mach()->ideal_Opcode(); |
8707 int opcode = this->as_Mach()->ideal_Opcode(); |
8698 if (UseAVX == 0) { |
8708 if (UseAVX == 0) { |
8699 if ($dst$$XMMRegister != $src$$XMMRegister) |
8709 if ($dst$$XMMRegister != $src$$XMMRegister) |
8709 |
8719 |
8710 instruct vshift4L(vecY dst, vecY src, vecS shift) %{ |
8720 instruct vshift4L(vecY dst, vecY src, vecS shift) %{ |
8711 predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
8721 predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
8712 match(Set dst (LShiftVL src shift)); |
8722 match(Set dst (LShiftVL src shift)); |
8713 match(Set dst (URShiftVL src shift)); |
8723 match(Set dst (URShiftVL src shift)); |
|
8724 effect(DEF dst, USE src, USE shift); |
8714 format %{ "vshiftq $dst,$src,$shift\t! left shift packed4L" %} |
8725 format %{ "vshiftq $dst,$src,$shift\t! left shift packed4L" %} |
8715 ins_encode %{ |
8726 ins_encode %{ |
8716 int vector_len = 1; |
8727 int vector_len = 1; |
8717 int opcode = this->as_Mach()->ideal_Opcode(); |
8728 int opcode = this->as_Mach()->ideal_Opcode(); |
8718 __ vshiftq(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
8729 __ vshiftq(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
8723 instruct vshift8L(vecZ dst, vecZ src, vecS shift) %{ |
8734 instruct vshift8L(vecZ dst, vecZ src, vecS shift) %{ |
8724 predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
8735 predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
8725 match(Set dst (LShiftVL src shift)); |
8736 match(Set dst (LShiftVL src shift)); |
8726 match(Set dst (RShiftVL src shift)); |
8737 match(Set dst (RShiftVL src shift)); |
8727 match(Set dst (URShiftVL src shift)); |
8738 match(Set dst (URShiftVL src shift)); |
|
8739 effect(DEF dst, USE src, USE shift); |
8728 format %{ "vshiftq $dst,$src,$shift\t! shift packed8L" %} |
8740 format %{ "vshiftq $dst,$src,$shift\t! shift packed8L" %} |
8729 ins_encode %{ |
8741 ins_encode %{ |
8730 int vector_len = 2; |
8742 int vector_len = 2; |
8731 int opcode = this->as_Mach()->ideal_Opcode(); |
8743 int opcode = this->as_Mach()->ideal_Opcode(); |
8732 __ vshiftq(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
8744 __ vshiftq(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |