87 UseSSE = 0; // Only on x86 and x64 |
87 UseSSE = 0; // Only on x86 and x64 |
88 |
88 |
89 _supports_cx8 = has_v9(); |
89 _supports_cx8 = has_v9(); |
90 _supports_atomic_getset4 = true; // swap instruction |
90 _supports_atomic_getset4 = true; // swap instruction |
91 |
91 |
92 if (is_niagara()) { |
92 // There are Fujitsu Sparc64 CPUs which support blk_init as well so |
93 // Indirect branch is the same cost as direct |
93 // we have to take this check out of the 'is_niagara()' block below. |
94 if (FLAG_IS_DEFAULT(UseInlineCaches)) { |
94 if (has_blk_init()) { |
95 FLAG_SET_DEFAULT(UseInlineCaches, false); |
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96 } |
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97 // Align loops on a single instruction boundary. |
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98 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { |
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99 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); |
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100 } |
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101 // When using CMS or G1, we cannot use memset() in BOT updates |
95 // When using CMS or G1, we cannot use memset() in BOT updates |
102 // because the sun4v/CMT version in libc_psr uses BIS which |
96 // because the sun4v/CMT version in libc_psr uses BIS which |
103 // exposes "phantom zeros" to concurrent readers. See 6948537. |
97 // exposes "phantom zeros" to concurrent readers. See 6948537. |
104 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { |
98 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { |
105 FLAG_SET_DEFAULT(UseMemSetInBOT, false); |
99 FLAG_SET_DEFAULT(UseMemSetInBOT, false); |
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100 } |
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101 // Issue a stern warning if the user has explicitly set |
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102 // UseMemSetInBOT (it is known to cause issues), but allow |
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103 // use for experimentation and debugging. |
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104 if (UseConcMarkSweepGC || UseG1GC) { |
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105 if (UseMemSetInBOT) { |
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106 assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error"); |
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107 warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability" |
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108 " on sun4v; please understand that you are using at your own risk!"); |
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109 } |
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110 } |
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111 } |
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112 |
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113 if (is_niagara()) { |
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114 // Indirect branch is the same cost as direct |
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115 if (FLAG_IS_DEFAULT(UseInlineCaches)) { |
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116 FLAG_SET_DEFAULT(UseInlineCaches, false); |
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117 } |
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118 // Align loops on a single instruction boundary. |
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119 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { |
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120 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); |
106 } |
121 } |
107 #ifdef _LP64 |
122 #ifdef _LP64 |
108 // 32-bit oops don't make sense for the 64-bit VM on sparc |
123 // 32-bit oops don't make sense for the 64-bit VM on sparc |
109 // since the 32-bit VM has the same registers and smaller objects. |
124 // since the 32-bit VM has the same registers and smaller objects. |
110 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
125 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |