equal
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inserted
replaced
444 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } |
444 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } |
445 static bool supports_3dnow2() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.tdnow2 != 0; } |
445 static bool supports_3dnow2() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.tdnow2 != 0; } |
446 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } |
446 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } |
447 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } |
447 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } |
448 |
448 |
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449 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). |
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450 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && |
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451 supports_sse3() && _model != 0x1C; } |
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452 |
449 static bool supports_compare_and_exchange() { return true; } |
453 static bool supports_compare_and_exchange() { return true; } |
450 |
454 |
451 static const char* cpu_features() { return _features_str; } |
455 static const char* cpu_features() { return _features_str; } |
452 |
456 |
453 static intx allocate_prefetch_distance() { |
457 static intx allocate_prefetch_distance() { |