254 get_cache_and_index_at_bcp(cache, index, bcp_offset, index_size); |
254 get_cache_and_index_at_bcp(cache, index, bcp_offset, index_size); |
255 // We use a 32-bit load here since the layout of 64-bit words on |
255 // We use a 32-bit load here since the layout of 64-bit words on |
256 // little-endian machines allow us that. |
256 // little-endian machines allow us that. |
257 movl(bytecode, Address(cache, index, Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset())); |
257 movl(bytecode, Address(cache, index, Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset())); |
258 const int shift_count = (1 + byte_no) * BitsPerByte; |
258 const int shift_count = (1 + byte_no) * BitsPerByte; |
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259 assert((byte_no == TemplateTable::f1_byte && shift_count == ConstantPoolCacheEntry::bytecode_1_shift) || |
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260 (byte_no == TemplateTable::f2_byte && shift_count == ConstantPoolCacheEntry::bytecode_2_shift), |
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261 "correct shift count"); |
259 shrl(bytecode, shift_count); |
262 shrl(bytecode, shift_count); |
260 andl(bytecode, 0xFF); |
263 assert(ConstantPoolCacheEntry::bytecode_1_mask == ConstantPoolCacheEntry::bytecode_2_mask, "common mask"); |
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264 andl(bytecode, ConstantPoolCacheEntry::bytecode_1_mask); |
261 } |
265 } |
262 |
266 |
263 |
267 |
264 void InterpreterMacroAssembler::get_cache_entry_pointer_at_bcp(Register cache, |
268 void InterpreterMacroAssembler::get_cache_entry_pointer_at_bcp(Register cache, |
265 Register tmp, |
269 Register tmp, |