1 //

     2 // Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.

     3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4 //

     5 // This code is free software; you can redistribute it and/or modify it

     6 // under the terms of the GNU General Public License version 2 only, as

     7 // published by the Free Software Foundation.

     8 //

     9 // This code is distributed in the hope that it will be useful, but WITHOUT

    10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12 // version 2 for more details (a copy is included in the LICENSE file that

    13 // accompanied this code).

    14 //

    15 // You should have received a copy of the GNU General Public License version

    16 // 2 along with this work; if not, write to the Free Software Foundation,

    17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18 //

    19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

    20 // or visit www.oracle.com if you need additional information or have any

    21 // questions.

    22 //

    23 //

    24 

    25 // AMD64 Win32 Architecture Description File

    26 

    27 //----------OS-DEPENDENT ENCODING BLOCK-----------------------------------------------------

    28 // This block specifies the encoding classes used by the compiler to output

    29 // byte streams.  Encoding classes generate functions which are called by

    30 // Machine Instruction Nodes in order to generate the bit encoding of the

    31 // instruction.  Operands specify their base encoding interface with the

    32 // interface keyword.  There are currently supported four interfaces,

    33 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an

    34 // operand to generate a function which returns its register number when

    35 // queried.   CONST_INTER causes an operand to generate a function which

    36 // returns the value of the constant when queried.  MEMORY_INTER causes an

    37 // operand to generate four functions which return the Base Register, the

    38 // Index Register, the Scale Value, and the Offset Value of the operand when

    39 // queried.  COND_INTER causes an operand to generate six functions which

    40 // return the encoding code (ie - encoding bits for the instruction)

    41 // associated with each basic boolean condition for a conditional instruction.

    42 // Instructions specify two basic values for encoding.  They use the

    43 // ins_encode keyword to specify their encoding class (which must be one of

    44 // the class names specified in the encoding block), and they use the

    45 // opcode keyword to specify, in order, their primary, secondary, and

    46 // tertiary opcode.  Only the opcode sections which a particular instruction

    47 // needs for encoding need to be specified.

    48 encode %{

    49   // Build emit functions for each basic byte or larger field in the intel

    50   // encoding scheme (opcode, rm, sib, immediate), and call them from C++

    51   // code in the enc_class source block.  Emit functions will live in the

    52   // main source block for now.  In future, we can generalize this by

    53   // adding a syntax that specifies the sizes of fields in an order,

    54   // so that the adlc can build the emit functions automagically

    55 

    56 %}

    57 

    58 

    59 // Platform dependent source

    60 

    61 source %{

    62 

    63 %}