5484 #endif |
5484 #endif |
5485 ins_encode( form3_mem_reg( mem, dst ) ); |
5485 ins_encode( form3_mem_reg( mem, dst ) ); |
5486 ins_pipe(iload_mem); |
5486 ins_pipe(iload_mem); |
5487 %} |
5487 %} |
5488 |
5488 |
5489 // Load Klass Pointer |
5489 // Load narrow Klass Pointer |
5490 instruct loadKlassComp(iRegP dst, memory mem) %{ |
5490 instruct loadNKlass(iRegN dst, memory mem) %{ |
5491 match(Set dst (LoadKlass mem)); |
5491 match(Set dst (LoadNKlass mem)); |
5492 predicate(n->in(MemNode::Address)->bottom_type()->is_ptr_to_narrowoop()); |
|
5493 ins_cost(MEMORY_REF_COST); |
5492 ins_cost(MEMORY_REF_COST); |
5494 |
5493 |
5495 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
5494 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
5496 |
5495 |
5497 ins_encode %{ |
5496 ins_encode %{ |
5501 if (index != G0) { |
5500 if (index != G0) { |
5502 __ lduw(base, index, dst); |
5501 __ lduw(base, index, dst); |
5503 } else { |
5502 } else { |
5504 __ lduw(base, $mem$$disp, dst); |
5503 __ lduw(base, $mem$$disp, dst); |
5505 } |
5504 } |
5506 // klass oop never null but this is generated for nonheader klass loads |
|
5507 // too which can be null. |
|
5508 __ decode_heap_oop(dst); |
|
5509 %} |
5505 %} |
5510 ins_pipe(iload_mem); |
5506 ins_pipe(iload_mem); |
5511 %} |
5507 %} |
5512 |
5508 |
5513 // Load Short (16bit signed) |
5509 // Load Short (16bit signed) |
5607 __ sethi(polling_page, false ); |
5603 __ sethi(polling_page, false ); |
5608 %} |
5604 %} |
5609 ins_pipe(loadConP_poll); |
5605 ins_pipe(loadConP_poll); |
5610 %} |
5606 %} |
5611 |
5607 |
|
5608 instruct loadConN0(iRegN dst, immN0 src) %{ |
|
5609 match(Set dst src); |
|
5610 |
|
5611 size(4); |
|
5612 format %{ "CLR $dst\t! compressed NULL ptr" %} |
|
5613 ins_encode( SetNull( dst ) ); |
|
5614 ins_pipe(ialu_imm); |
|
5615 %} |
|
5616 |
5612 instruct loadConN(iRegN dst, immN src) %{ |
5617 instruct loadConN(iRegN dst, immN src) %{ |
5613 match(Set dst src); |
5618 match(Set dst src); |
5614 ins_cost(DEFAULT_COST * 2); |
5619 ins_cost(DEFAULT_COST * 3/2); |
5615 format %{ "SET $src,$dst\t!ptr" %} |
5620 format %{ "SET $src,$dst\t! compressed ptr" %} |
5616 ins_encode %{ |
5621 ins_encode %{ |
5617 address con = (address)$src$$constant; |
|
5618 Register dst = $dst$$Register; |
5622 Register dst = $dst$$Register; |
5619 if (con == NULL) { |
5623 __ set_narrow_oop((jobject)$src$$constant, dst); |
5620 __ mov(G0, dst); |
5624 %} |
5621 } else { |
5625 ins_pipe(ialu_hi_lo_reg); |
5622 __ set_oop((jobject)$src$$constant, dst); |
|
5623 __ encode_heap_oop(dst); |
|
5624 } |
|
5625 %} |
|
5626 ins_pipe(loadConP); |
|
5627 |
|
5628 %} |
5626 %} |
5629 |
5627 |
5630 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ |
5628 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ |
5631 // %%% maybe this should work like loadConD |
5629 // %%% maybe this should work like loadConD |
5632 match(Set dst src); |
5630 match(Set dst src); |
6256 format %{ "MOV$cmp $fcc,$src,$dst" %} |
6254 format %{ "MOV$cmp $fcc,$src,$dst" %} |
6257 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); |
6255 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); |
6258 ins_pipe(ialu_imm); |
6256 ins_pipe(ialu_imm); |
6259 %} |
6257 %} |
6260 |
6258 |
|
6259 // Conditional move for RegN. Only cmov(reg,reg). |
|
6260 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
|
6261 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
|
6262 ins_cost(150); |
|
6263 format %{ "MOV$cmp $pcc,$src,$dst" %} |
|
6264 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
6265 ins_pipe(ialu_reg); |
|
6266 %} |
|
6267 |
|
6268 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
6269 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
|
6270 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
6271 ins_cost(150); |
|
6272 size(4); |
|
6273 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
6274 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
6275 ins_pipe(ialu_reg); |
|
6276 %} |
|
6277 |
|
6278 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
|
6279 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
|
6280 ins_cost(150); |
|
6281 size(4); |
|
6282 format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
6283 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
|
6284 ins_pipe(ialu_reg); |
|
6285 %} |
|
6286 |
6261 // Conditional move |
6287 // Conditional move |
6262 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ |
6288 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ |
6263 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); |
6289 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); |
6264 ins_cost(150); |
6290 ins_cost(150); |
6265 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} |
6291 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} |
6273 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} |
6299 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} |
6274 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); |
6300 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); |
6275 ins_pipe(ialu_imm); |
6301 ins_pipe(ialu_imm); |
6276 %} |
6302 %} |
6277 |
6303 |
|
6304 // This instruction also works with CmpN so we don't need cmovPN_reg. |
6278 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
6305 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
6279 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
6306 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
6280 ins_cost(150); |
6307 ins_cost(150); |
6281 |
6308 |
6282 size(4); |
6309 size(4); |
8258 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ |
8285 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ |
8259 match(Set pcc (CmpP op1 op2)); |
8286 match(Set pcc (CmpP op1 op2)); |
8260 |
8287 |
8261 size(4); |
8288 size(4); |
8262 format %{ "CMP $op1,$op2\t! ptr" %} |
8289 format %{ "CMP $op1,$op2\t! ptr" %} |
|
8290 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
8291 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
|
8292 ins_pipe(ialu_cconly_reg_imm); |
|
8293 %} |
|
8294 |
|
8295 // Compare Narrow oops |
|
8296 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
|
8297 match(Set icc (CmpN op1 op2)); |
|
8298 |
|
8299 size(4); |
|
8300 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
8301 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
8302 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
8303 ins_pipe(ialu_cconly_reg_reg); |
|
8304 %} |
|
8305 |
|
8306 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
|
8307 match(Set icc (CmpN op1 op2)); |
|
8308 |
|
8309 size(4); |
|
8310 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
8263 opcode(Assembler::subcc_op3, Assembler::arith_op); |
8311 opcode(Assembler::subcc_op3, Assembler::arith_op); |
8264 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
8312 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
8265 ins_pipe(ialu_cconly_reg_imm); |
8313 ins_pipe(ialu_cconly_reg_imm); |
8266 %} |
8314 %} |
8267 |
8315 |
8593 format %{ "MOV$cmp $xcc,$src,$dst" %} |
8641 format %{ "MOV$cmp $xcc,$src,$dst" %} |
8594 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); |
8642 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); |
8595 ins_pipe(ialu_imm); |
8643 ins_pipe(ialu_imm); |
8596 %} |
8644 %} |
8597 |
8645 |
|
8646 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
|
8647 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
|
8648 ins_cost(150); |
|
8649 format %{ "MOV$cmp $xcc,$src,$dst" %} |
|
8650 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
|
8651 ins_pipe(ialu_reg); |
|
8652 %} |
|
8653 |
8598 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
8654 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
8599 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); |
8655 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); |
8600 ins_cost(150); |
8656 ins_cost(150); |
8601 format %{ "MOV$cmp $xcc,$src,$dst" %} |
8657 format %{ "MOV$cmp $xcc,$src,$dst" %} |
8602 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
8658 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
8823 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} |
8879 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} |
8824 ins_encode( enc_PartialSubtypeCheck() ); |
8880 ins_encode( enc_PartialSubtypeCheck() ); |
8825 ins_pipe(partial_subtype_check_pipe); |
8881 ins_pipe(partial_subtype_check_pipe); |
8826 %} |
8882 %} |
8827 |
8883 |
8828 |
|
8829 instruct compP_iRegN_immN0(flagsRegP pcc, iRegN op1, immN0 op2 ) %{ |
|
8830 match(Set pcc (CmpN op1 op2)); |
|
8831 |
|
8832 size(4); |
|
8833 format %{ "CMP $op1,$op2\t! ptr" %} |
|
8834 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
8835 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
|
8836 ins_pipe(ialu_cconly_reg_imm); |
|
8837 %} |
|
8838 |
8884 |
8839 // ============================================================================ |
8885 // ============================================================================ |
8840 // inlined locking and unlocking |
8886 // inlined locking and unlocking |
8841 |
8887 |
8842 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ |
8888 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ |