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1 /* |
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2 * Copyright (c) 2008, 2015, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #ifndef CPU_ARM_VM_REGISTER_ARM_HPP |
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26 #define CPU_ARM_VM_REGISTER_ARM_HPP |
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27 |
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28 #include "asm/register.hpp" |
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29 #include "vm_version_arm.hpp" |
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30 |
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31 class VMRegImpl; |
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32 typedef VMRegImpl* VMReg; |
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33 |
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34 // These are declared ucontext.h |
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35 #undef R0 |
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36 #undef R1 |
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37 #undef R2 |
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38 #undef R3 |
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39 #undef R4 |
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40 #undef R5 |
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41 #undef R6 |
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42 #undef R7 |
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43 #undef R8 |
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44 #undef R9 |
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45 #undef R10 |
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46 #undef R11 |
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47 #undef R12 |
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48 #undef R13 |
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49 #undef R14 |
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50 #undef R15 |
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51 |
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52 #define R(r) ((Register)(r)) |
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53 |
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54 ///////////////////////////////// |
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55 // Support for different ARM ABIs |
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56 // Note: default ABI is for linux |
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57 |
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58 |
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59 // R9_IS_SCRATCHED |
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60 // |
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61 // The ARM ABI does not guarantee that R9 is callee saved. |
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62 // Set R9_IS_SCRATCHED to 1 to ensure it is properly saved/restored by |
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63 // the caller. |
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64 #ifndef R9_IS_SCRATCHED |
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65 // Default: R9 is callee saved |
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66 #define R9_IS_SCRATCHED 0 |
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67 #endif |
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68 |
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69 #ifndef AARCH64 |
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70 // FP_REG_NUM |
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71 // |
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72 // The ARM ABI does not state which register is used for the frame pointer. |
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73 // Note: for the ABIs we are currently aware of, FP is currently |
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74 // either R7 or R11. Code may have to be extended if a third register |
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75 // register must be supported (see altFP_7_11). |
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76 #ifndef FP_REG_NUM |
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77 // Default: FP is R11 |
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78 #define FP_REG_NUM 11 |
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79 #endif |
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80 #endif // AARCH64 |
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81 |
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82 // ALIGN_WIDE_ARGUMENTS |
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83 // |
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84 // The ARM ABI requires 64-bits arguments to be aligned on 4 words |
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85 // or on even registers. Set ALIGN_WIDE_ARGUMENTS to 1 for that behavior. |
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86 // |
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87 // Unfortunately, some platforms do not endorse that part of the ABI. |
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88 // |
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89 // We are aware of one which expects 64-bit arguments to only be 4 |
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90 // bytes aligned and can for instance use R3 + a stack slot for such |
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91 // an argument. |
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92 // |
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93 // This is the behavor implemented if (ALIGN_WIDE_ARGUMENTS == 0) |
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94 #ifndef ALIGN_WIDE_ARGUMENTS |
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95 // Default: align on 8 bytes and avoid using <r3+stack> |
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96 #define ALIGN_WIDE_ARGUMENTS 1 |
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97 #endif |
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98 |
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99 #define R0 ((Register)0) |
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100 #define R1 ((Register)1) |
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101 #define R2 ((Register)2) |
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102 #define R3 ((Register)3) |
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103 #define R4 ((Register)4) |
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104 #define R5 ((Register)5) |
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105 #define R6 ((Register)6) |
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106 #define R7 ((Register)7) |
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107 #define R8 ((Register)8) |
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108 #define R9 ((Register)9) |
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109 #define R10 ((Register)10) |
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110 #define R11 ((Register)11) |
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111 #define R12 ((Register)12) |
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112 #define R13 ((Register)13) |
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113 #define R14 ((Register)14) |
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114 #define R15 ((Register)15) |
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115 |
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116 #ifdef AARCH64 |
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117 |
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118 #define R16 ((Register)16) |
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119 #define R17 ((Register)17) |
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120 #define R18 ((Register)18) |
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121 #define R19 ((Register)19) |
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122 #define R20 ((Register)20) |
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123 #define R21 ((Register)21) |
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124 #define R22 ((Register)22) |
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125 #define R23 ((Register)23) |
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126 #define R24 ((Register)24) |
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127 #define R25 ((Register)25) |
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128 #define R26 ((Register)26) |
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129 #define R27 ((Register)27) |
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130 #define R28 ((Register)28) |
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131 #define R29 ((Register)29) |
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132 #define R30 ((Register)30) |
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133 #define ZR ((Register)31) |
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134 #define SP ((Register)32) |
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135 |
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136 #define FP R29 |
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137 #define LR R30 |
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138 |
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139 #define altFP_7_11 R7 |
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140 |
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141 #else // !AARCH64 |
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142 |
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143 #define FP ((Register)FP_REG_NUM) |
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144 |
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145 // Safe use of registers which may be FP on some platforms. |
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146 // |
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147 // altFP_7_11: R7 if not equal to FP, else R11 (the default FP) |
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148 // |
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149 // Note: add additional altFP_#_11 for each register potentially used |
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150 // as FP on supported ABIs (and replace R# by altFP_#_11). altFP_#_11 |
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151 // must be #define to R11 if and only if # is FP_REG_NUM. |
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152 #if (FP_REG_NUM == 7) |
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153 #define altFP_7_11 ((Register)11) |
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154 #else |
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155 #define altFP_7_11 ((Register)7) |
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156 #endif |
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157 #define SP R13 |
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158 #define LR R14 |
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159 #define PC R15 |
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160 |
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161 #endif // !AARCH64 |
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162 |
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163 |
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164 class RegisterImpl; |
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165 typedef RegisterImpl* Register; |
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166 |
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167 inline Register as_Register(int encoding) { |
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168 return (Register)(intptr_t)encoding; |
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169 } |
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170 |
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171 class RegisterImpl : public AbstractRegisterImpl { |
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172 public: |
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173 enum { |
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174 #ifdef AARCH64 |
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175 number_of_gprs = 31, |
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176 zr_sp_encoding = 31, |
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177 #endif |
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178 number_of_registers = AARCH64_ONLY(number_of_gprs + 2) NOT_AARCH64(16) |
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179 }; |
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180 |
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181 Register successor() const { return as_Register(encoding() + 1); } |
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182 |
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183 inline friend Register as_Register(int encoding); |
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184 |
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185 VMReg as_VMReg(); |
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186 |
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187 // accessors |
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188 int encoding() const { assert(is_valid(), "invalid register"); return value(); } |
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189 const char* name() const; |
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190 |
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191 #ifdef AARCH64 |
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192 int encoding_with_zr() const { assert (is_valid_gpr_or_zr(), "invalid register"); return (this == ZR) ? zr_sp_encoding : value(); } |
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193 int encoding_with_sp() const { assert (is_valid_gpr_or_sp(), "invalid register"); return (this == SP) ? zr_sp_encoding : value(); } |
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194 #endif |
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195 |
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196 // testers |
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197 bool is_valid() const { return 0 <= value() && value() < number_of_registers; } |
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198 |
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199 #ifdef AARCH64 |
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200 bool is_valid_gpr() const { return (0 <= value() && value() < number_of_gprs); } |
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201 bool is_valid_gpr_or_zr() const { return is_valid_gpr() || (this == ZR); } |
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202 bool is_valid_gpr_or_sp() const { return is_valid_gpr() || (this == SP); } |
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203 #endif |
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204 }; |
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205 |
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206 CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1)); |
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207 |
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208 |
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209 // Use FloatRegister as shortcut |
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210 class FloatRegisterImpl; |
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211 typedef FloatRegisterImpl* FloatRegister; |
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212 |
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213 inline FloatRegister as_FloatRegister(int encoding) { |
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214 return (FloatRegister)(intptr_t)encoding; |
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215 } |
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216 |
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217 class FloatRegisterImpl : public AbstractRegisterImpl { |
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218 public: |
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219 enum { |
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220 #ifdef AARCH64 |
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221 number_of_registers = 32 |
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222 #else |
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223 number_of_registers = NOT_COMPILER2(32) COMPILER2_PRESENT(64) |
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224 #endif |
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225 }; |
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226 |
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227 inline friend FloatRegister as_FloatRegister(int encoding); |
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228 |
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229 VMReg as_VMReg(); |
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230 |
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231 int encoding() const { assert(is_valid(), "invalid register"); return value(); } |
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232 bool is_valid() const { return 0 <= (intx)this && (intx)this < number_of_registers; } |
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233 FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } |
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234 |
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235 const char* name() const; |
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236 |
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237 #ifndef AARCH64 |
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238 int hi_bits() const { |
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239 return (encoding() >> 1) & 0xf; |
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240 } |
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241 |
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242 int lo_bit() const { |
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243 return encoding() & 1; |
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244 } |
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245 |
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246 int hi_bit() const { |
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247 return encoding() >> 5; |
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248 } |
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249 #endif // !AARCH64 |
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250 }; |
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251 |
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252 CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg, (-1)); |
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253 |
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254 #ifdef AARCH64 |
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255 |
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256 CONSTANT_REGISTER_DECLARATION(FloatRegister, V0, ( 0)); |
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257 CONSTANT_REGISTER_DECLARATION(FloatRegister, V1, ( 1)); |
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258 CONSTANT_REGISTER_DECLARATION(FloatRegister, V2, ( 2)); |
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259 CONSTANT_REGISTER_DECLARATION(FloatRegister, V3, ( 3)); |
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260 CONSTANT_REGISTER_DECLARATION(FloatRegister, V4, ( 4)); |
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261 CONSTANT_REGISTER_DECLARATION(FloatRegister, V5, ( 5)); |
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262 CONSTANT_REGISTER_DECLARATION(FloatRegister, V6, ( 6)); |
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263 CONSTANT_REGISTER_DECLARATION(FloatRegister, V7, ( 7)); |
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264 CONSTANT_REGISTER_DECLARATION(FloatRegister, V8, ( 8)); |
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265 CONSTANT_REGISTER_DECLARATION(FloatRegister, V9, ( 9)); |
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266 CONSTANT_REGISTER_DECLARATION(FloatRegister, V10, (10)); |
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267 CONSTANT_REGISTER_DECLARATION(FloatRegister, V11, (11)); |
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268 CONSTANT_REGISTER_DECLARATION(FloatRegister, V12, (12)); |
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269 CONSTANT_REGISTER_DECLARATION(FloatRegister, V13, (13)); |
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270 CONSTANT_REGISTER_DECLARATION(FloatRegister, V14, (14)); |
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271 CONSTANT_REGISTER_DECLARATION(FloatRegister, V15, (15)); |
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272 CONSTANT_REGISTER_DECLARATION(FloatRegister, V16, (16)); |
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273 CONSTANT_REGISTER_DECLARATION(FloatRegister, V17, (17)); |
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274 CONSTANT_REGISTER_DECLARATION(FloatRegister, V18, (18)); |
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275 CONSTANT_REGISTER_DECLARATION(FloatRegister, V19, (19)); |
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276 CONSTANT_REGISTER_DECLARATION(FloatRegister, V20, (20)); |
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277 CONSTANT_REGISTER_DECLARATION(FloatRegister, V21, (21)); |
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278 CONSTANT_REGISTER_DECLARATION(FloatRegister, V22, (22)); |
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279 CONSTANT_REGISTER_DECLARATION(FloatRegister, V23, (23)); |
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280 CONSTANT_REGISTER_DECLARATION(FloatRegister, V24, (24)); |
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281 CONSTANT_REGISTER_DECLARATION(FloatRegister, V25, (25)); |
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282 CONSTANT_REGISTER_DECLARATION(FloatRegister, V26, (26)); |
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283 CONSTANT_REGISTER_DECLARATION(FloatRegister, V27, (27)); |
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284 CONSTANT_REGISTER_DECLARATION(FloatRegister, V28, (28)); |
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285 CONSTANT_REGISTER_DECLARATION(FloatRegister, V29, (29)); |
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286 CONSTANT_REGISTER_DECLARATION(FloatRegister, V30, (30)); |
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287 CONSTANT_REGISTER_DECLARATION(FloatRegister, V31, (31)); |
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288 |
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289 #define S0 V0 |
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290 #define S1_reg V1 |
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291 #define Stemp V31 |
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292 |
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293 #define D0 V0 |
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294 #define D1 V1 |
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295 |
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296 #else // AARCH64 |
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297 |
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298 /* |
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299 * S1-S6 are named with "_reg" suffix to avoid conflict with |
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300 * constants defined in sharedRuntimeTrig.cpp |
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301 */ |
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302 CONSTANT_REGISTER_DECLARATION(FloatRegister, S0, ( 0)); |
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303 CONSTANT_REGISTER_DECLARATION(FloatRegister, S1_reg, ( 1)); |
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304 CONSTANT_REGISTER_DECLARATION(FloatRegister, S2_reg, ( 2)); |
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305 CONSTANT_REGISTER_DECLARATION(FloatRegister, S3_reg, ( 3)); |
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306 CONSTANT_REGISTER_DECLARATION(FloatRegister, S4_reg, ( 4)); |
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307 CONSTANT_REGISTER_DECLARATION(FloatRegister, S5_reg, ( 5)); |
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308 CONSTANT_REGISTER_DECLARATION(FloatRegister, S6_reg, ( 6)); |
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309 CONSTANT_REGISTER_DECLARATION(FloatRegister, S7, ( 7)); |
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310 CONSTANT_REGISTER_DECLARATION(FloatRegister, S8, ( 8)); |
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311 CONSTANT_REGISTER_DECLARATION(FloatRegister, S9, ( 9)); |
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312 CONSTANT_REGISTER_DECLARATION(FloatRegister, S10, (10)); |
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313 CONSTANT_REGISTER_DECLARATION(FloatRegister, S11, (11)); |
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314 CONSTANT_REGISTER_DECLARATION(FloatRegister, S12, (12)); |
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315 CONSTANT_REGISTER_DECLARATION(FloatRegister, S13, (13)); |
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316 CONSTANT_REGISTER_DECLARATION(FloatRegister, S14, (14)); |
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317 CONSTANT_REGISTER_DECLARATION(FloatRegister, S15, (15)); |
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318 CONSTANT_REGISTER_DECLARATION(FloatRegister, S16, (16)); |
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319 CONSTANT_REGISTER_DECLARATION(FloatRegister, S17, (17)); |
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320 CONSTANT_REGISTER_DECLARATION(FloatRegister, S18, (18)); |
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321 CONSTANT_REGISTER_DECLARATION(FloatRegister, S19, (19)); |
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322 CONSTANT_REGISTER_DECLARATION(FloatRegister, S20, (20)); |
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323 CONSTANT_REGISTER_DECLARATION(FloatRegister, S21, (21)); |
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324 CONSTANT_REGISTER_DECLARATION(FloatRegister, S22, (22)); |
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325 CONSTANT_REGISTER_DECLARATION(FloatRegister, S23, (23)); |
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326 CONSTANT_REGISTER_DECLARATION(FloatRegister, S24, (24)); |
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327 CONSTANT_REGISTER_DECLARATION(FloatRegister, S25, (25)); |
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328 CONSTANT_REGISTER_DECLARATION(FloatRegister, S26, (26)); |
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329 CONSTANT_REGISTER_DECLARATION(FloatRegister, S27, (27)); |
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330 CONSTANT_REGISTER_DECLARATION(FloatRegister, S28, (28)); |
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331 CONSTANT_REGISTER_DECLARATION(FloatRegister, S29, (29)); |
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332 CONSTANT_REGISTER_DECLARATION(FloatRegister, S30, (30)); |
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333 CONSTANT_REGISTER_DECLARATION(FloatRegister, S31, (31)); |
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334 CONSTANT_REGISTER_DECLARATION(FloatRegister, Stemp, (30)); |
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335 |
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336 CONSTANT_REGISTER_DECLARATION(FloatRegister, D0, ( 0)); |
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337 CONSTANT_REGISTER_DECLARATION(FloatRegister, D1, ( 2)); |
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338 CONSTANT_REGISTER_DECLARATION(FloatRegister, D2, ( 4)); |
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339 CONSTANT_REGISTER_DECLARATION(FloatRegister, D3, ( 6)); |
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340 CONSTANT_REGISTER_DECLARATION(FloatRegister, D4, ( 8)); |
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341 CONSTANT_REGISTER_DECLARATION(FloatRegister, D5, ( 10)); |
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342 CONSTANT_REGISTER_DECLARATION(FloatRegister, D6, ( 12)); |
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343 CONSTANT_REGISTER_DECLARATION(FloatRegister, D7, ( 14)); |
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344 CONSTANT_REGISTER_DECLARATION(FloatRegister, D8, ( 16)); |
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345 CONSTANT_REGISTER_DECLARATION(FloatRegister, D9, ( 18)); |
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346 CONSTANT_REGISTER_DECLARATION(FloatRegister, D10, ( 20)); |
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347 CONSTANT_REGISTER_DECLARATION(FloatRegister, D11, ( 22)); |
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348 CONSTANT_REGISTER_DECLARATION(FloatRegister, D12, ( 24)); |
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349 CONSTANT_REGISTER_DECLARATION(FloatRegister, D13, ( 26)); |
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350 CONSTANT_REGISTER_DECLARATION(FloatRegister, D14, ( 28)); |
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351 CONSTANT_REGISTER_DECLARATION(FloatRegister, D15, (30)); |
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352 CONSTANT_REGISTER_DECLARATION(FloatRegister, D16, (32)); |
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353 CONSTANT_REGISTER_DECLARATION(FloatRegister, D17, (34)); |
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354 CONSTANT_REGISTER_DECLARATION(FloatRegister, D18, (36)); |
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355 CONSTANT_REGISTER_DECLARATION(FloatRegister, D19, (38)); |
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356 CONSTANT_REGISTER_DECLARATION(FloatRegister, D20, (40)); |
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357 CONSTANT_REGISTER_DECLARATION(FloatRegister, D21, (42)); |
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358 CONSTANT_REGISTER_DECLARATION(FloatRegister, D22, (44)); |
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359 CONSTANT_REGISTER_DECLARATION(FloatRegister, D23, (46)); |
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360 CONSTANT_REGISTER_DECLARATION(FloatRegister, D24, (48)); |
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361 CONSTANT_REGISTER_DECLARATION(FloatRegister, D25, (50)); |
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362 CONSTANT_REGISTER_DECLARATION(FloatRegister, D26, (52)); |
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363 CONSTANT_REGISTER_DECLARATION(FloatRegister, D27, (54)); |
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364 CONSTANT_REGISTER_DECLARATION(FloatRegister, D28, (56)); |
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365 CONSTANT_REGISTER_DECLARATION(FloatRegister, D29, (58)); |
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366 CONSTANT_REGISTER_DECLARATION(FloatRegister, D30, (60)); |
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367 CONSTANT_REGISTER_DECLARATION(FloatRegister, D31, (62)); |
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368 |
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369 #endif // AARCH64 |
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370 |
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371 class ConcreteRegisterImpl : public AbstractRegisterImpl { |
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372 public: |
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373 enum { |
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374 log_vmregs_per_word = LogBytesPerWord - LogBytesPerInt, // VMRegs are of 4-byte size |
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375 #ifdef COMPILER2 |
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376 log_bytes_per_fpr = AARCH64_ONLY(4) NOT_AARCH64(2), // quad vectors |
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377 #else |
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378 log_bytes_per_fpr = AARCH64_ONLY(3) NOT_AARCH64(2), // double vectors |
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379 #endif |
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380 log_words_per_fpr = log_bytes_per_fpr - LogBytesPerWord, |
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381 words_per_fpr = 1 << log_words_per_fpr, |
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382 log_vmregs_per_fpr = log_bytes_per_fpr - LogBytesPerInt, |
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383 log_vmregs_per_gpr = log_vmregs_per_word, |
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384 vmregs_per_gpr = 1 << log_vmregs_per_gpr, |
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385 vmregs_per_fpr = 1 << log_vmregs_per_fpr, |
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386 |
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387 num_gpr = RegisterImpl::number_of_registers << log_vmregs_per_gpr, |
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388 max_gpr0 = num_gpr, |
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389 num_fpr = FloatRegisterImpl::number_of_registers << log_vmregs_per_fpr, |
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390 max_fpr0 = max_gpr0 + num_fpr, |
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391 number_of_registers = num_gpr + num_fpr + |
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392 // TODO-AARCH64 revise |
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393 1+1 // APSR and FPSCR so that c2's REG_COUNT <= ConcreteRegisterImpl::number_of_registers |
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394 }; |
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395 |
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396 static const int max_gpr; |
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397 static const int max_fpr; |
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398 }; |
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399 |
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400 // TODO-AARCH64 revise the following definitions |
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401 |
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402 class VFPSystemRegisterImpl; |
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403 typedef VFPSystemRegisterImpl* VFPSystemRegister; |
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404 class VFPSystemRegisterImpl : public AbstractRegisterImpl { |
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405 public: |
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406 int encoding() const { return value(); } |
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407 }; |
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408 |
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409 #define FPSID ((VFPSystemRegister)0) |
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410 #define FPSCR ((VFPSystemRegister)1) |
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411 #define MVFR0 ((VFPSystemRegister)0x6) |
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412 #define MVFR1 ((VFPSystemRegister)0x7) |
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413 |
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414 /* |
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415 * Register definitions shared across interpreter and compiler |
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416 */ |
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417 #define Rexception_obj AARCH64_ONLY(R19) NOT_AARCH64(R4) |
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418 #define Rexception_pc AARCH64_ONLY(R20) NOT_AARCH64(R5) |
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419 |
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420 #ifdef AARCH64 |
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421 #define Rheap_base R27 |
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422 #endif // AARCH64 |
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423 |
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424 /* |
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425 * Interpreter register definitions common to C++ and template interpreters. |
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426 */ |
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427 #ifdef AARCH64 |
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428 #define Rlocals R23 |
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429 #define Rmethod R26 |
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430 #define Rthread R28 |
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431 #define Rtemp R16 |
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432 #define Rtemp2 R17 |
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433 #else |
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434 #define Rlocals R8 |
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435 #define Rmethod R9 |
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436 #define Rthread R10 |
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437 #define Rtemp R12 |
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438 #endif // AARCH64 |
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439 |
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440 // Interpreter calling conventions |
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441 |
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442 #define Rparams AARCH64_ONLY(R8) NOT_AARCH64(SP) |
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443 #define Rsender_sp AARCH64_ONLY(R19) NOT_AARCH64(R4) |
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444 |
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445 // JSR292 |
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446 // Note: R5_mh is needed only during the call setup, including adapters |
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447 // This does not seem to conflict with Rexception_pc |
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448 // In case of issues, R3 might be OK but adapters calling the runtime would have to save it |
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449 #define R5_mh R5 // MethodHandle register, used during the call setup |
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450 #define Rmh_SP_save FP // for C1 |
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451 |
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452 /* |
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453 * C++ Interpreter Register Defines |
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454 */ |
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455 #define Rsave0 R4 |
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456 #define Rsave1 R5 |
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457 #define Rsave2 R6 |
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458 #define Rstate altFP_7_11 // R7 or R11 |
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459 #define Ricklass R8 |
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460 |
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461 /* |
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462 * TemplateTable Interpreter Register Usage |
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463 */ |
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464 |
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465 // Temporary registers |
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466 #define R0_tmp R0 |
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467 #define R1_tmp R1 |
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468 #define R2_tmp R2 |
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469 #define R3_tmp R3 |
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470 #define R4_tmp R4 |
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471 #define R5_tmp R5 |
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472 #define R12_tmp R12 |
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473 #define LR_tmp LR |
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474 |
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475 #define S0_tmp S0 |
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476 #define S1_tmp S1_reg |
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477 |
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478 #define D0_tmp D0 |
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479 #define D1_tmp D1 |
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480 |
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481 // Temporary registers saved across VM calls (according to C calling conventions) |
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482 #define Rtmp_save0 AARCH64_ONLY(R19) NOT_AARCH64(R4) |
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483 #define Rtmp_save1 AARCH64_ONLY(R20) NOT_AARCH64(R5) |
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484 |
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485 // Cached TOS value |
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486 #define R0_tos R0 |
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487 |
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488 #ifndef AARCH64 |
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489 #define R0_tos_lo R0 |
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490 #define R1_tos_hi R1 |
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491 #endif |
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492 |
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493 #define S0_tos S0 |
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494 #define D0_tos D0 |
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495 |
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496 // Dispatch table |
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497 #define RdispatchTable AARCH64_ONLY(R22) NOT_AARCH64(R6) |
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498 |
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499 // Bytecode pointer |
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500 #define Rbcp AARCH64_ONLY(R24) NOT_AARCH64(altFP_7_11) |
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501 |
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502 // Pre-loaded next bytecode for the dispatch |
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503 #define R3_bytecode R3 |
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504 |
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505 // Conventions between bytecode templates and stubs |
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506 #define R2_ClassCastException_obj R2 |
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507 #define R4_ArrayIndexOutOfBounds_index R4 |
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508 |
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509 // Interpreter expression stack top |
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510 #define Rstack_top AARCH64_ONLY(R25) NOT_AARCH64(SP) |
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511 |
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512 /* |
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513 * Linux 32-bit ARM C ABI Register calling conventions |
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514 * |
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515 * REG use callee/caller saved |
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516 * |
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517 * R0 First argument reg caller |
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518 * result register |
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519 * R1 Second argument reg caller |
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520 * result register |
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521 * R2 Third argument reg caller |
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522 * R3 Fourth argument reg caller |
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523 * |
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524 * R4 - R8 Local variable registers callee |
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525 * R9 |
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526 * R10, R11 Local variable registers callee |
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527 * |
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528 * R12 (IP) Scratch register used in inter-procedural calling |
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529 * R13 (SP) Stack Pointer callee |
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530 * R14 (LR) Link register |
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531 * R15 (PC) Program Counter |
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532 * |
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533 * TODO-AARCH64: document AArch64 ABI |
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534 * |
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535 */ |
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536 #define c_rarg0 R0 |
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537 #define c_rarg1 R1 |
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538 #define c_rarg2 R2 |
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539 #define c_rarg3 R3 |
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540 |
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541 #ifdef AARCH64 |
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542 #define c_rarg4 R4 |
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543 #define c_rarg5 R5 |
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544 #define c_rarg6 R6 |
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545 #define c_rarg7 R7 |
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546 #endif |
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547 |
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548 #ifdef AARCH64 |
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549 #define GPR_PARAMS 8 |
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550 #define FPR_PARAMS 8 |
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551 #else |
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552 #define GPR_PARAMS 4 |
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553 #endif |
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554 |
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555 |
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556 // Java ABI |
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557 // XXX Is this correct? |
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558 #define j_rarg0 c_rarg0 |
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559 #define j_rarg1 c_rarg1 |
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560 #define j_rarg2 c_rarg2 |
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561 #define j_rarg3 c_rarg3 |
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562 |
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563 #ifdef AARCH64 |
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564 #define j_rarg4 c_rarg4 |
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565 #define j_rarg5 c_rarg5 |
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566 #define j_rarg6 c_rarg6 |
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567 #define j_rarg7 c_rarg7 |
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568 #endif |
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569 |
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570 #endif // CPU_ARM_VM_REGISTER_ARM_HPP |