1 /*

     2  * Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

    20  * or visit www.oracle.com if you need additional information or have any

    21  * questions.

    22  *

    23  */

    24 

    25 #include "precompiled.hpp"

    26 #include "asm/macroAssembler.hpp"

    27 #include "assembler_arm.inline.hpp"

    28 #include "runtime/icache.hpp"

    29 

    30 #define __ _masm->

    31 

    32 #ifdef AARCH64

    33 

    34 static int icache_flush(address addr, int lines, int magic) {

    35   // TODO-AARCH64 Figure out actual cache line size (mrs Xt, CTR_EL0)

    36 

    37   address p = addr;

    38   for (int i = 0; i < lines; i++, p += ICache::line_size) {

    39     __asm__ volatile(

    40       " dc cvau, %[p]"

    41       :

    42       : [p] "r" (p)

    43       : "memory");

    44   }

    45 

    46   __asm__ volatile(

    47     " dsb ish"

    48     : : : "memory");

    49 

    50   p = addr;

    51   for (int i = 0; i < lines; i++, p += ICache::line_size) {

    52     __asm__ volatile(

    53       " ic ivau, %[p]"

    54       :

    55       : [p] "r" (p)

    56       : "memory");

    57   }

    58 

    59   __asm__ volatile(

    60     " dsb ish\n\t"

    61     " isb\n\t"

    62     : : : "memory");

    63 

    64   return magic;

    65 }

    66 

    67 #else

    68 

    69 static int icache_flush(address addr, int lines, int magic) {

    70   __builtin___clear_cache(addr, addr + (lines << ICache::log2_line_size));

    71   return magic;

    72 }

    73 

    74 #endif // AARCH64

    75 

    76 void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) {

    77   address start = (address)icache_flush;

    78 

    79   *flush_icache_stub = (ICache::flush_icache_stub_t)start;

    80 

    81   // ICache::invalidate_range() contains explicit condition that the first

    82   // call is invoked on the generated icache flush stub code range.

    83   ICache::invalidate_range(start, 0);

    84 

    85   {

    86     // dummy code mark to make the shared code happy

    87     // (fields that would need to be modified to emulate the correct

    88     // mark are not accessible)

    89     StubCodeMark mark(this, "ICache", "fake_stub_for_inlined_icache_flush");

    90     __ ret();

    91   }

    92 }

    93 

    94 #undef __