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1 /* |
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2 * Copyright (c) 2010, 2016, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #include "precompiled.hpp" |
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26 #include "c1/c1_LIR.hpp" |
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27 |
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28 FloatRegister LIR_OprDesc::as_float_reg() const { |
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29 return as_FloatRegister(fpu_regnr()); |
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30 } |
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31 |
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32 FloatRegister LIR_OprDesc::as_double_reg() const { |
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33 return as_FloatRegister(fpu_regnrLo()); |
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34 } |
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35 |
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36 #ifdef AARCH64 |
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37 // Reg2 unused. |
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38 LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) { |
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39 assert(as_FloatRegister(reg2) == fnoreg, "Not used on this platform"); |
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40 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) | |
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41 (reg1 << LIR_OprDesc::reg2_shift) | |
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42 LIR_OprDesc::double_type | |
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43 LIR_OprDesc::fpu_register | |
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44 LIR_OprDesc::double_size); |
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45 } |
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46 #else |
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47 LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) { |
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48 assert(as_FloatRegister(reg2) != fnoreg, "Arm32 holds double in two regs."); |
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49 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) | |
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50 (reg2 << LIR_OprDesc::reg2_shift) | |
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51 LIR_OprDesc::double_type | |
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52 LIR_OprDesc::fpu_register | |
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53 LIR_OprDesc::double_size); |
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54 } |
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55 #endif |
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56 |
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57 #ifndef PRODUCT |
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58 void LIR_Address::verify() const { |
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59 #ifdef _LP64 |
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60 assert(base()->is_cpu_register(), "wrong base operand"); |
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61 #endif |
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62 #ifdef AARCH64 |
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63 if (base()->type() == T_INT) { |
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64 assert(index()->is_single_cpu() && (index()->type() == T_INT), "wrong index operand"); |
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65 } else { |
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66 assert(index()->is_illegal() || index()->is_double_cpu() || |
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67 (index()->is_single_cpu() && (index()->is_oop_register() || index()->type() == T_INT)), "wrong index operand"); |
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68 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, "wrong type for addresses"); |
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69 } |
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70 #else |
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71 assert(disp() == 0 || index()->is_illegal(), "can't have both"); |
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72 // Note: offsets higher than 4096 must not be rejected here. They can |
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73 // be handled by the back-end or will be rejected if not. |
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74 #ifdef _LP64 |
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75 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); |
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76 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, |
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77 "wrong type for addresses"); |
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78 #else |
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79 assert(base()->is_single_cpu(), "wrong base operand"); |
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80 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); |
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81 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, |
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82 "wrong type for addresses"); |
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83 #endif |
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84 #endif // AARCH64 |
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85 } |
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86 #endif // PRODUCT |