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hotspot/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
changeset 5046 27e801a857cb
parent 4898 b5bbb74def0b
child 5048 c31b6243f37e
equal deleted inserted replaced
5044:7e40acdf2163 5046:27e801a857cb 
   376     return -1;
 
   376     return -1;
 
   377   }
 
   377   }
 
   378 
   378 
   379   int offset = code_offset();
 
   379   int offset = code_offset();
 
   380 
   380 
   381   if (compilation()->has_exception_handlers() || compilation()->env()->jvmti_can_post_on_exceptions()) {
 
   381   __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
 
   382     __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
 
       
   383     __ delayed()->nop();
 
       
   384   }
 
       
   385 
       
   386   __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
 
       
   387   __ delayed()->nop();
 
   382   __ delayed()->nop();
 
   388   debug_only(__ stop("should have gone to the caller");)
 
   383   debug_only(__ stop("should have gone to the caller");)
 
   389   assert(code_offset() - offset <= exception_handler_size, "overflow");
 
   384   assert(code_offset() - offset <= exception_handler_size, "overflow");
 
   390   __ end_a_stub();
 
   385   __ end_a_stub();
 
   391 
   386 
   683 void LIR_Assembler::align_call(LIR_Code) {
 
   678 void LIR_Assembler::align_call(LIR_Code) {
 
   684   // do nothing since all instructions are word aligned on sparc
 
   679   // do nothing since all instructions are word aligned on sparc
 
   685 }
 
   680 }
 
   686 
   681 
   687 
   682 
   688 void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) {
 
   683 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 
   689   __ call(entry, rtype);
 
   684   __ call(op->addr(), rtype);
 
   690   // the peephole pass fills the delay slot
 
   685   // the peephole pass fills the delay slot
 
   691 }
 
   686 }
 
   692 
   687 
   693 
   688 
   694 void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) {
 
   689 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 
   695   RelocationHolder rspec = virtual_call_Relocation::spec(pc());
 
   690   RelocationHolder rspec = virtual_call_Relocation::spec(pc());
 
   696   __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
 
   691   __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
 
   697   __ relocate(rspec);
 
   692   __ relocate(rspec);
 
   698   __ call(entry, relocInfo::none);
 
   693   __ call(op->addr(), relocInfo::none);
 
   699   // the peephole pass fills the delay slot
 
   694   // the peephole pass fills the delay slot
 
   700 }
 
   695 }
 
   701 
   696 
   702 
   697 
   703 void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) {
 
   698 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
 
   704   add_debug_info_for_null_check_here(info);
 
   699   add_debug_info_for_null_check_here(op->info());
 
   705   __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
 
   700   __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
 
   706   if (__ is_simm13(vtable_offset) ) {
 
   701   if (__ is_simm13(op->vtable_offset())) {
 
   707     __ ld_ptr(G3_scratch, vtable_offset, G5_method);
 
   702     __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
 
   708   } else {
 
   703   } else {
 
   709     // This will generate 2 instructions
 
   704     // This will generate 2 instructions
 
   710     __ set(vtable_offset, G5_method);
 
   705     __ set(op->vtable_offset(), G5_method);
 
   711     // ld_ptr, set_hi, set
 
   706     // ld_ptr, set_hi, set
 
   712     __ ld_ptr(G3_scratch, G5_method, G5_method);
 
   707     __ ld_ptr(G3_scratch, G5_method, G5_method);
 
   713   }
 
   708   }
 
   714   __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
 
   709   __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
 
   715   __ callr(G3_scratch, G0);
 
   710   __ callr(G3_scratch, G0);
 
   716   // the peephole pass fills the delay slot
 
   711   // the peephole pass fills the delay slot
 
       
   712 }
 
       
   713 
       
   714 
       
   715 void LIR_Assembler::preserve_SP() {
 
       
   716   Unimplemented();
 
       
   717 }
 
       
   718 
       
   719 
       
   720 void LIR_Assembler::restore_SP() {
 
       
   721   Unimplemented();
 
   717 }
 
   722 }
 
   718 
   723 
   719 
   724 
   720 // load with 32-bit displacement
 
   725 // load with 32-bit displacement
 
   721 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
 
   726 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
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