1 /*

     2  * Copyright (c) 2018, Red Hat, Inc. All rights reserved.

     3  *

     4  * This code is free software; you can redistribute it and/or modify it

     5  * under the terms of the GNU General Public License version 2 only, as

     6  * published by the Free Software Foundation.

     7  *

     8  * This code is distributed in the hope that it will be useful, but WITHOUT

     9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    11  * version 2 for more details (a copy is included in the LICENSE file that

    12  * accompanied this code).

    13  *

    14  * You should have received a copy of the GNU General Public License version

    15  * 2 along with this work; if not, write to the Free Software Foundation,

    16  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    17  *

    18  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

    19  * or visit www.oracle.com if you need additional information or have any

    20  * questions.

    21  *

    22  */

    23 

    24 #include "precompiled.hpp"

    25 #include "c1/c1_LIRAssembler.hpp"

    26 #include "c1/c1_MacroAssembler.hpp"

    27 #include "gc/shenandoah/shenandoahBarrierSet.hpp"

    28 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"

    29 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"

    30 

    31 #define __ masm->masm()->

    32 

    33 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) {

    34   Register addr = _addr->as_register_lo();

    35   Register newval = _new_value->as_register();

    36   Register cmpval = _cmp_value->as_register();

    37   Register tmp1 = _tmp1->as_register();

    38   Register tmp2 = _tmp2->as_register();

    39   Register result = result_opr()->as_register();

    40   assert(cmpval == rax, "wrong register");

    41   assert(newval != NULL, "new val must be register");

    42   assert(cmpval != newval, "cmp and new values must be in different registers");

    43   assert(cmpval != addr, "cmp and addr must be in different registers");

    44   assert(newval != addr, "new value and addr must be in different registers");

    45 

    46   // Apply storeval barrier to newval.

    47   ShenandoahBarrierSet::assembler()->storeval_barrier(masm->masm(), newval, tmp1);

    48 

    49 #ifdef _LP64

    50   if (UseCompressedOops) {

    51     __ encode_heap_oop(cmpval);

    52     __ mov(rscratch1, newval);

    53     __ encode_heap_oop(rscratch1);

    54     newval = rscratch1;

    55   }

    56 #endif

    57 

    58   ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), result, Address(addr, 0), cmpval, newval, false, tmp1, tmp2);

    59 }

    60 

    61 #undef __

    62 

    63 #ifdef ASSERT

    64 #define __ gen->lir(__FILE__, __LINE__)->

    65 #else

    66 #define __ gen->lir()->

    67 #endif

    68 

    69 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {

    70 

    71   if (access.is_oop()) {

    72     LIRGenerator* gen = access.gen();

    73     if (ShenandoahSATBBarrier) {

    74       pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),

    75                   LIR_OprFact::illegalOpr /* pre_val */);

    76     }

    77     if (ShenandoahCASBarrier) {

    78       cmp_value.load_item_force(FrameMap::rax_oop_opr);

    79       new_value.load_item();

    80 

    81       LIR_Opr t1 = gen->new_register(T_OBJECT);

    82       LIR_Opr t2 = gen->new_register(T_OBJECT);

    83       LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();

    84       LIR_Opr result = gen->new_register(T_INT);

    85 

    86       __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));

    87       return result;

    88     }

    89   }

    90   return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);

    91 }

    92 

    93 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {

    94   LIRGenerator* gen = access.gen();

    95   BasicType type = access.type();

    96 

    97   LIR_Opr result = gen->new_register(type);

    98   value.load_item();

    99   LIR_Opr value_opr = value.result();

   100 

   101   if (access.is_oop()) {

   102     value_opr = storeval_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());

   103   }

   104 

   105   // Because we want a 2-arg form of xchg and xadd

   106   __ move(value_opr, result);

   107 

   108   assert(type == T_INT || type == T_OBJECT || type == T_ARRAY LP64_ONLY( || type == T_LONG ), "unexpected type");

   109   __ xchg(access.resolved_addr(), result, result, LIR_OprFact::illegalOpr);

   110 

   111   if (access.is_oop()) {

   112     result = load_reference_barrier(access.gen(), result, access.access_emit_info(), true);

   113     if (ShenandoahSATBBarrier) {

   114       pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr,

   115                   result /* pre_val */);

   116     }

   117   }

   118 

   119   return result;

   120 }