src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetC1_aarch64.cpp
changeset 54763 2584e5772546
parent 54762 64d9a4d582bc
child 54764 865ec913f916
equal deleted inserted replaced
54762:64d9a4d582bc 54763:2584e5772546
     1 /*
       
     2  * Copyright (c) 2018, Red Hat, Inc. All rights reserved.
       
     3  *
       
     4  * This code is free software; you can redistribute it and/or modify it
       
     5  * under the terms of the GNU General Public License version 2 only, as
       
     6  * published by the Free Software Foundation.
       
     7  *
       
     8  * This code is distributed in the hope that it will be useful, but WITHOUT
       
     9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
       
    10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
       
    11  * version 2 for more details (a copy is included in the LICENSE file that
       
    12  * accompanied this code).
       
    13  *
       
    14  * You should have received a copy of the GNU General Public License version
       
    15  * 2 along with this work; if not, write to the Free Software Foundation,
       
    16  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
       
    17  *
       
    18  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
       
    19  * or visit www.oracle.com if you need additional information or have any
       
    20  * questions.
       
    21  *
       
    22  */
       
    23 
       
    24 #include "precompiled.hpp"
       
    25 #include "c1/c1_LIRAssembler.hpp"
       
    26 #include "c1/c1_MacroAssembler.hpp"
       
    27 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
       
    28 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
       
    29 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
       
    30 
       
    31 #define __ masm->masm()->
       
    32 
       
    33 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) {
       
    34   Register addr = _addr->as_register_lo();
       
    35   Register newval = _new_value->as_register();
       
    36   Register cmpval = _cmp_value->as_register();
       
    37   Register tmp1 = _tmp1->as_register();
       
    38   Register tmp2 = _tmp2->as_register();
       
    39   Register result = result_opr()->as_register();
       
    40 
       
    41   ShenandoahBarrierSet::assembler()->storeval_barrier(masm->masm(), newval, rscratch2);
       
    42 
       
    43   if (UseCompressedOops) {
       
    44     __ encode_heap_oop(tmp1, cmpval);
       
    45     cmpval = tmp1;
       
    46     __ encode_heap_oop(tmp2, newval);
       
    47     newval = tmp2;
       
    48   }
       
    49 
       
    50   ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmpval, newval, /*acquire*/ false, /*release*/ true, /*weak*/ false, /*is_cae*/ false, result);
       
    51 }
       
    52 
       
    53 #undef __
       
    54 
       
    55 #ifdef ASSERT
       
    56 #define __ gen->lir(__FILE__, __LINE__)->
       
    57 #else
       
    58 #define __ gen->lir()->
       
    59 #endif
       
    60 
       
    61 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
       
    62   BasicType bt = access.type();
       
    63   if (access.is_oop()) {
       
    64     LIRGenerator *gen = access.gen();
       
    65     if (ShenandoahSATBBarrier) {
       
    66       pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
       
    67                   LIR_OprFact::illegalOpr /* pre_val */);
       
    68     }
       
    69     if (ShenandoahCASBarrier) {
       
    70       cmp_value.load_item();
       
    71       new_value.load_item();
       
    72 
       
    73       LIR_Opr t1 = gen->new_register(T_OBJECT);
       
    74       LIR_Opr t2 = gen->new_register(T_OBJECT);
       
    75       LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
       
    76       LIR_Opr result = gen->new_register(T_INT);
       
    77 
       
    78       __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
       
    79       return result;
       
    80     }
       
    81   }
       
    82   return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
       
    83 }
       
    84 
       
    85 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {
       
    86   LIRGenerator* gen = access.gen();
       
    87   BasicType type = access.type();
       
    88 
       
    89   LIR_Opr result = gen->new_register(type);
       
    90   value.load_item();
       
    91   LIR_Opr value_opr = value.result();
       
    92 
       
    93   if (access.is_oop()) {
       
    94     value_opr = storeval_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
       
    95   }
       
    96 
       
    97   assert(type == T_INT || type == T_OBJECT || type == T_ARRAY LP64_ONLY( || type == T_LONG ), "unexpected type");
       
    98   LIR_Opr tmp = gen->new_register(T_INT);
       
    99   __ xchg(access.resolved_addr(), value_opr, result, tmp);
       
   100 
       
   101   if (access.is_oop()) {
       
   102     result = load_reference_barrier(access.gen(), result, access.access_emit_info(), true);
       
   103     if (ShenandoahSATBBarrier) {
       
   104       pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr,
       
   105                   result /* pre_val */);
       
   106     }
       
   107   }
       
   108 
       
   109   return result;
       
   110 }