80 idealreg2debugmask[Op_RegN] = NULL; |
80 idealreg2debugmask[Op_RegN] = NULL; |
81 idealreg2debugmask[Op_RegL] = NULL; |
81 idealreg2debugmask[Op_RegL] = NULL; |
82 idealreg2debugmask[Op_RegF] = NULL; |
82 idealreg2debugmask[Op_RegF] = NULL; |
83 idealreg2debugmask[Op_RegD] = NULL; |
83 idealreg2debugmask[Op_RegD] = NULL; |
84 idealreg2debugmask[Op_RegP] = NULL; |
84 idealreg2debugmask[Op_RegP] = NULL; |
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85 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node |
85 } |
86 } |
86 |
87 |
87 //------------------------------warp_incoming_stk_arg------------------------ |
88 //------------------------------warp_incoming_stk_arg------------------------ |
88 // This warps a VMReg into an OptoReg::Name |
89 // This warps a VMReg into an OptoReg::Name |
89 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) { |
90 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) { |
1151 |
1152 |
1152 LabelRootDepth = 0; |
1153 LabelRootDepth = 0; |
1153 |
1154 |
1154 // StoreNodes require their Memory input to match any LoadNodes |
1155 // StoreNodes require their Memory input to match any LoadNodes |
1155 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ; |
1156 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ; |
1156 |
1157 #ifdef ASSERT |
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1158 Node* save_mem_node = _mem_node; |
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1159 _mem_node = n->is_Store() ? (Node*)n : NULL; |
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1160 #endif |
1157 // State object for root node of match tree |
1161 // State object for root node of match tree |
1158 // Allocate it on _states_arena - stack allocation can cause stack overflow. |
1162 // Allocate it on _states_arena - stack allocation can cause stack overflow. |
1159 State *s = new (&_states_arena) State; |
1163 State *s = new (&_states_arena) State; |
1160 s->_kids[0] = NULL; |
1164 s->_kids[0] = NULL; |
1161 s->_kids[1] = NULL; |
1165 s->_kids[1] = NULL; |
1443 mach->add_req(0); // Set initial control to none |
1448 mach->add_req(0); // Set initial control to none |
1444 ReduceInst_Chain_Rule( s, rule, mem, mach ); |
1449 ReduceInst_Chain_Rule( s, rule, mem, mach ); |
1445 } |
1450 } |
1446 |
1451 |
1447 // If a Memory was used, insert a Memory edge |
1452 // If a Memory was used, insert a Memory edge |
1448 if( mem != (Node*)1 ) |
1453 if( mem != (Node*)1 ) { |
1449 mach->ins_req(MemNode::Memory,mem); |
1454 mach->ins_req(MemNode::Memory,mem); |
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1455 #ifdef ASSERT |
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1456 // Verify adr type after matching memory operation |
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1457 const MachOper* oper = mach->memory_operand(); |
|
1458 if (oper != NULL && oper != (MachOper*)-1 && |
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1459 mach->adr_type() != TypeRawPtr::BOTTOM) { // non-direct addressing mode |
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1460 // It has a unique memory operand. Find corresponding ideal mem node. |
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1461 Node* m = NULL; |
|
1462 if (leaf->is_Mem()) { |
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1463 m = leaf; |
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1464 } else { |
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1465 m = _mem_node; |
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1466 assert(m != NULL && m->is_Mem(), "expecting memory node"); |
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1467 } |
|
1468 if (m->adr_type() != mach->adr_type()) { |
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1469 m->dump(); |
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1470 tty->print_cr("mach:"); |
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1471 mach->dump(1); |
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1472 } |
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1473 assert(m->adr_type() == mach->adr_type(), "matcher should not change adr type"); |
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1474 } |
|
1475 #endif |
|
1476 } |
1450 |
1477 |
1451 // If the _leaf is an AddP, insert the base edge |
1478 // If the _leaf is an AddP, insert the base edge |
1452 if( leaf->is_AddP() ) |
1479 if( leaf->is_AddP() ) |
1453 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base)); |
1480 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base)); |
1454 |
1481 |
1508 } else { |
1535 } else { |
1509 // Chain from the result of an instruction |
1536 // Chain from the result of an instruction |
1510 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand"); |
1537 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand"); |
1511 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C ); |
1538 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C ); |
1512 Node *mem1 = (Node*)1; |
1539 Node *mem1 = (Node*)1; |
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1540 debug_only(Node *save_mem_node = _mem_node;) |
1513 mach->add_req( ReduceInst(s, newrule, mem1) ); |
1541 mach->add_req( ReduceInst(s, newrule, mem1) ); |
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1542 debug_only(_mem_node = save_mem_node;) |
1514 } |
1543 } |
1515 return; |
1544 return; |
1516 } |
1545 } |
1517 |
1546 |
1518 |
1547 |
1519 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) { |
1548 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) { |
1520 if( s->_leaf->is_Load() ) { |
1549 if( s->_leaf->is_Load() ) { |
1521 Node *mem2 = s->_leaf->in(MemNode::Memory); |
1550 Node *mem2 = s->_leaf->in(MemNode::Memory); |
1522 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" ); |
1551 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" ); |
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1552 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;) |
1523 mem = mem2; |
1553 mem = mem2; |
1524 } |
1554 } |
1525 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) { |
1555 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) { |
1526 if( mach->in(0) == NULL ) |
1556 if( mach->in(0) == NULL ) |
1527 mach->set_req(0, s->_leaf->in(0)); |
1557 mach->set_req(0, s->_leaf->in(0)); |
1561 } else { |
1591 } else { |
1562 // instruction --> call build operand( ) to catch result |
1592 // instruction --> call build operand( ) to catch result |
1563 // --> ReduceInst( newrule ) |
1593 // --> ReduceInst( newrule ) |
1564 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C ); |
1594 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C ); |
1565 Node *mem1 = (Node*)1; |
1595 Node *mem1 = (Node*)1; |
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1596 debug_only(Node *save_mem_node = _mem_node;) |
1566 mach->add_req( ReduceInst( newstate, newrule, mem1 ) ); |
1597 mach->add_req( ReduceInst( newstate, newrule, mem1 ) ); |
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1598 debug_only(_mem_node = save_mem_node;) |
1567 } |
1599 } |
1568 } |
1600 } |
1569 assert( mach->_opnds[num_opnds-1], "" ); |
1601 assert( mach->_opnds[num_opnds-1], "" ); |
1570 } |
1602 } |
1571 return num_opnds; |
1603 return num_opnds; |
1592 } |
1624 } |
1593 |
1625 |
1594 if( s->_leaf->is_Load() ) { |
1626 if( s->_leaf->is_Load() ) { |
1595 assert( mem == (Node*)1, "multiple Memories being matched at once?" ); |
1627 assert( mem == (Node*)1, "multiple Memories being matched at once?" ); |
1596 mem = s->_leaf->in(MemNode::Memory); |
1628 mem = s->_leaf->in(MemNode::Memory); |
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1629 debug_only(_mem_node = s->_leaf;) |
1597 } |
1630 } |
1598 if( s->_leaf->in(0) && s->_leaf->req() > 1) { |
1631 if( s->_leaf->in(0) && s->_leaf->req() > 1) { |
1599 if( !mach->in(0) ) |
1632 if( !mach->in(0) ) |
1600 mach->set_req(0,s->_leaf->in(0)); |
1633 mach->set_req(0,s->_leaf->in(0)); |
1601 else { |
1634 else { |
1616 |
1649 |
1617 } else { // Child is a new instruction |
1650 } else { // Child is a new instruction |
1618 // Reduce the instruction, and add a direct pointer from this |
1651 // Reduce the instruction, and add a direct pointer from this |
1619 // machine instruction to the newly reduced one. |
1652 // machine instruction to the newly reduced one. |
1620 Node *mem1 = (Node*)1; |
1653 Node *mem1 = (Node*)1; |
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1654 debug_only(Node *save_mem_node = _mem_node;) |
1621 mach->add_req( ReduceInst( kid, newrule, mem1 ) ); |
1655 mach->add_req( ReduceInst( kid, newrule, mem1 ) ); |
|
1656 debug_only(_mem_node = save_mem_node;) |
1622 } |
1657 } |
1623 } |
1658 } |
1624 } |
1659 } |
1625 |
1660 |
1626 |
1661 |