7452 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {

  7453   assert(VM_Version::supports_avx(), "");

  7454   assert(!VM_Version::supports_evex(), "");

  7455   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);

  7456   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);

  7457   emit_int8((unsigned char)0xC2);

  7458   emit_int8((unsigned char)(0xC0 | encode));

  7459   emit_int8((unsigned char)(0xF & cop));

  7460 }

  7461 

  7462 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {

  7463   assert(VM_Version::supports_avx(), "");

  7464   assert(!VM_Version::supports_evex(), "");

  7465   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);

  7466   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);

  7467   emit_int8((unsigned char)0x4A);

  7468   emit_int8((unsigned char)(0xC0 | encode));

  7469   int src2_enc = src2->encoding();

  7470   emit_int8((unsigned char)(0xF0 & src2_enc<<4));

  7471 }

  7472