47 LIR_Opr FrameMap::R2_metadata_opr; |
47 LIR_Opr FrameMap::R2_metadata_opr; |
48 LIR_Opr FrameMap::R3_metadata_opr; |
48 LIR_Opr FrameMap::R3_metadata_opr; |
49 LIR_Opr FrameMap::R4_metadata_opr; |
49 LIR_Opr FrameMap::R4_metadata_opr; |
50 LIR_Opr FrameMap::R5_metadata_opr; |
50 LIR_Opr FrameMap::R5_metadata_opr; |
51 |
51 |
52 #ifdef AARCH64 |
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53 LIR_Opr FrameMap::ZR_opr; |
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54 #endif // AARCH64 |
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55 |
52 |
56 LIR_Opr FrameMap::LR_opr; |
53 LIR_Opr FrameMap::LR_opr; |
57 LIR_Opr FrameMap::LR_oop_opr; |
54 LIR_Opr FrameMap::LR_oop_opr; |
58 LIR_Opr FrameMap::LR_ptr_opr; |
55 LIR_Opr FrameMap::LR_ptr_opr; |
59 LIR_Opr FrameMap::FP_opr; |
56 LIR_Opr FrameMap::FP_opr; |
80 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; |
77 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; |
81 opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off, type)); |
78 opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off, type)); |
82 } else if (r_1->is_Register()) { |
79 } else if (r_1->is_Register()) { |
83 Register reg = r_1->as_Register(); |
80 Register reg = r_1->as_Register(); |
84 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { |
81 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { |
85 #ifdef AARCH64 |
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86 assert(r_1->next() == r_2, "should be the same"); |
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87 opr = as_long_opr(reg); |
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88 #else |
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89 opr = as_long_opr(reg, r_2->as_Register()); |
82 opr = as_long_opr(reg, r_2->as_Register()); |
90 #endif |
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91 } else if (type == T_OBJECT || type == T_ARRAY) { |
83 } else if (type == T_OBJECT || type == T_ARRAY) { |
92 opr = as_oop_opr(reg); |
84 opr = as_oop_opr(reg); |
93 } else if (type == T_METADATA) { |
85 } else if (type == T_METADATA) { |
94 opr = as_metadata_opr(reg); |
86 opr = as_metadata_opr(reg); |
95 } else { |
87 } else { |
113 |
105 |
114 int i; |
106 int i; |
115 int rnum = 0; |
107 int rnum = 0; |
116 |
108 |
117 // Registers used for allocation |
109 // Registers used for allocation |
118 #ifdef AARCH64 |
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119 assert(Rthread == R28 && Rheap_base == R27 && Rtemp == R16, "change the code here"); |
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120 for (i = 0; i < 16; i++) { |
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121 map_register(rnum++, as_Register(i)); |
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122 } |
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123 for (i = 17; i < 28; i++) { |
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124 map_register(rnum++, as_Register(i)); |
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125 } |
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126 #else |
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127 assert(Rthread == R10 && Rtemp == R12, "change the code here"); |
110 assert(Rthread == R10 && Rtemp == R12, "change the code here"); |
128 for (i = 0; i < 10; i++) { |
111 for (i = 0; i < 10; i++) { |
129 map_register(rnum++, as_Register(i)); |
112 map_register(rnum++, as_Register(i)); |
130 } |
113 } |
131 #endif // AARCH64 |
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132 assert(rnum == pd_nof_cpu_regs_reg_alloc, "should be"); |
114 assert(rnum == pd_nof_cpu_regs_reg_alloc, "should be"); |
133 |
115 |
134 // Registers not used for allocation |
116 // Registers not used for allocation |
135 map_register(rnum++, LR); // LR register should be listed first, see c1_LinearScan_arm.hpp::is_processed_reg_num. |
117 map_register(rnum++, LR); // LR register should be listed first, see c1_LinearScan_arm.hpp::is_processed_reg_num. |
136 assert(rnum == pd_nof_cpu_regs_processed_in_linearscan, "should be"); |
118 assert(rnum == pd_nof_cpu_regs_processed_in_linearscan, "should be"); |
137 |
119 |
138 map_register(rnum++, Rtemp); |
120 map_register(rnum++, Rtemp); |
139 map_register(rnum++, Rthread); |
121 map_register(rnum++, Rthread); |
140 map_register(rnum++, FP); // ARM32: R7 or R11 |
122 map_register(rnum++, FP); // ARM32: R7 or R11 |
141 map_register(rnum++, SP); |
123 map_register(rnum++, SP); |
142 #ifdef AARCH64 |
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143 map_register(rnum++, ZR); |
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144 #else |
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145 map_register(rnum++, PC); |
124 map_register(rnum++, PC); |
146 #endif |
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147 assert(rnum == pd_nof_cpu_regs_frame_map, "should be"); |
125 assert(rnum == pd_nof_cpu_regs_frame_map, "should be"); |
148 |
126 |
149 _init_done = true; |
127 _init_done = true; |
150 |
128 |
151 R0_opr = as_opr(R0); R0_oop_opr = as_oop_opr(R0); R0_metadata_opr = as_metadata_opr(R0); |
129 R0_opr = as_opr(R0); R0_oop_opr = as_oop_opr(R0); R0_metadata_opr = as_metadata_opr(R0); |
153 R2_opr = as_opr(R2); R2_oop_opr = as_oop_opr(R2); R2_metadata_opr = as_metadata_opr(R2); |
131 R2_opr = as_opr(R2); R2_oop_opr = as_oop_opr(R2); R2_metadata_opr = as_metadata_opr(R2); |
154 R3_opr = as_opr(R3); R3_oop_opr = as_oop_opr(R3); R3_metadata_opr = as_metadata_opr(R3); |
132 R3_opr = as_opr(R3); R3_oop_opr = as_oop_opr(R3); R3_metadata_opr = as_metadata_opr(R3); |
155 R4_opr = as_opr(R4); R4_oop_opr = as_oop_opr(R4); R4_metadata_opr = as_metadata_opr(R4); |
133 R4_opr = as_opr(R4); R4_oop_opr = as_oop_opr(R4); R4_metadata_opr = as_metadata_opr(R4); |
156 R5_opr = as_opr(R5); R5_oop_opr = as_oop_opr(R5); R5_metadata_opr = as_metadata_opr(R5); |
134 R5_opr = as_opr(R5); R5_oop_opr = as_oop_opr(R5); R5_metadata_opr = as_metadata_opr(R5); |
157 |
135 |
158 #ifdef AARCH64 |
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159 ZR_opr = as_opr(ZR); |
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160 #endif // AARCH64 |
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161 |
136 |
162 LR_opr = as_opr(LR); |
137 LR_opr = as_opr(LR); |
163 LR_oop_opr = as_oop_opr(LR); |
138 LR_oop_opr = as_oop_opr(LR); |
164 LR_ptr_opr = as_pointer_opr(LR); |
139 LR_ptr_opr = as_pointer_opr(LR); |
165 FP_opr = as_pointer_opr(FP); |
140 FP_opr = as_pointer_opr(FP); |
167 Rthread_opr = as_pointer_opr(Rthread); |
142 Rthread_opr = as_pointer_opr(Rthread); |
168 |
143 |
169 // LIR operands for result |
144 // LIR operands for result |
170 Int_result_opr = R0_opr; |
145 Int_result_opr = R0_opr; |
171 Object_result_opr = R0_oop_opr; |
146 Object_result_opr = R0_oop_opr; |
172 #ifdef AARCH64 |
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173 Long_result_opr = as_long_opr(R0); |
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174 Float_result_opr = as_float_opr(S0); |
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175 Double_result_opr = as_double_opr(D0); |
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176 #else |
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177 Long_result_opr = as_long_opr(R0, R1); |
147 Long_result_opr = as_long_opr(R0, R1); |
178 #ifdef __ABI_HARD__ |
148 #ifdef __ABI_HARD__ |
179 Float_result_opr = as_float_opr(S0); |
149 Float_result_opr = as_float_opr(S0); |
180 Double_result_opr = as_double_opr(D0); |
150 Double_result_opr = as_double_opr(D0); |
181 #else |
151 #else |
182 Float_result_opr = LIR_OprFact::single_softfp(0); |
152 Float_result_opr = LIR_OprFact::single_softfp(0); |
183 Double_result_opr = LIR_OprFact::double_softfp(0, 1); |
153 Double_result_opr = LIR_OprFact::double_softfp(0, 1); |
184 #endif // __ABI_HARD__ |
154 #endif // __ABI_HARD__ |
185 #endif // AARCH64 |
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186 |
155 |
187 Exception_oop_opr = as_oop_opr(Rexception_obj); |
156 Exception_oop_opr = as_oop_opr(Rexception_obj); |
188 Exception_pc_opr = as_opr(Rexception_pc); |
157 Exception_pc_opr = as_opr(Rexception_pc); |
189 |
158 |
190 for (i = 0; i < nof_caller_save_cpu_regs(); i++) { |
159 for (i = 0; i < nof_caller_save_cpu_regs(); i++) { |
220 max_offset = arg_offset; |
189 max_offset = arg_offset; |
221 } |
190 } |
222 } |
191 } |
223 java_index += type2size[opr->type()]; |
192 java_index += type2size[opr->type()]; |
224 } |
193 } |
225 return max_offset < AARCH64_ONLY(16384) NOT_AARCH64(4096); // TODO-AARCH64 check that LIRAssembler does not generate load/store of byte and half-word with SP as address base |
194 return max_offset < 4096; |
226 } |
195 } |
227 |
196 |
228 VMReg FrameMap::fpu_regname(int n) { |
197 VMReg FrameMap::fpu_regname(int n) { |
229 return as_FloatRegister(n)->as_VMReg(); |
198 return as_FloatRegister(n)->as_VMReg(); |
230 } |
199 } |