1 /*

     2  * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,

    20  * CA 95054 USA or visit www.sun.com if you need additional information or

    21  * have any questions.

    22  *

    23  */

    24 

    25 class VM_Version: public Abstract_VM_Version {

    26 public:

    27   // cpuid result register layouts.  These are all unions of a uint32_t

    28   // (in case anyone wants access to the register as a whole) and a bitfield.

    29 

    30   union StdCpuid1Eax {

    31     uint32_t value;

    32     struct {

    33       uint32_t stepping   : 4,

    34                model      : 4,

    35                family     : 4,

    36                proc_type  : 2,

    37                           : 2,

    38                ext_model  : 4,

    39                ext_family : 8,

    40                           : 4;

    41     } bits;

    42   };

    43 

    44   union StdCpuid1Ebx { // example, unused

    45     uint32_t value;

    46     struct {

    47       uint32_t brand_id         : 8,

    48                clflush_size     : 8,

    49                threads_per_cpu  : 8,

    50                apic_id          : 8;

    51     } bits;

    52   };

    53 

    54   union StdCpuid1Ecx {

    55     uint32_t value;

    56     struct {

    57       uint32_t sse3     : 1,

    58                         : 2,

    59                monitor  : 1,

    60                         : 1,

    61                vmx      : 1,

    62                         : 1,

    63                est      : 1,

    64                         : 1,

    65                ssse3    : 1,

    66                cid      : 1,

    67                         : 2,

    68                cmpxchg16: 1,

    69                         : 4,

    70                dca      : 1,

    71                sse4_1   : 1,

    72                sse4_2   : 1,

    73                         : 11;

    74     } bits;

    75   };

    76 

    77   union StdCpuid1Edx {

    78     uint32_t value;

    79     struct {

    80       uint32_t          : 4,

    81                tsc      : 1,

    82                         : 3,

    83                cmpxchg8 : 1,

    84                         : 6,

    85                cmov     : 1,

    86                         : 7,

    87                mmx      : 1,

    88                fxsr     : 1,

    89                sse      : 1,

    90                sse2     : 1,

    91                         : 1,

    92                ht       : 1,

    93                         : 3;

    94     } bits;

    95   };

    96 

    97   union DcpCpuid4Eax {

    98     uint32_t value;

    99     struct {

   100       uint32_t cache_type    : 5,

   101                              : 21,

   102                cores_per_cpu : 6;

   103     } bits;

   104   };

   105 

   106   union DcpCpuid4Ebx {

   107     uint32_t value;

   108     struct {

   109       uint32_t L1_line_size  : 12,

   110                partitions    : 10,

   111                associativity : 10;

   112     } bits;

   113   };

   114 

   115   union ExtCpuid1Ecx {

   116     uint32_t value;

   117     struct {

   118       uint32_t LahfSahf     : 1,

   119                CmpLegacy    : 1,

   120                             : 4,

   121                abm          : 1,

   122                sse4a        : 1,

   123                misalignsse  : 1,

   124                prefetchw    : 1,

   125                             : 22;

   126     } bits;

   127   };

   128 

   129   union ExtCpuid1Edx {

   130     uint32_t value;

   131     struct {

   132       uint32_t           : 22,

   133                mmx_amd   : 1,

   134                mmx       : 1,

   135                fxsr      : 1,

   136                          : 4,

   137                long_mode : 1,

   138                tdnow2    : 1,

   139                tdnow     : 1;

   140     } bits;

   141   };

   142 

   143   union ExtCpuid5Ex {

   144     uint32_t value;

   145     struct {

   146       uint32_t L1_line_size : 8,

   147                L1_tag_lines : 8,

   148                L1_assoc     : 8,

   149                L1_size      : 8;

   150     } bits;

   151   };

   152 

   153   union ExtCpuid8Ecx {

   154     uint32_t value;

   155     struct {

   156       uint32_t cores_per_cpu : 8,

   157                              : 24;

   158     } bits;

   159   };

   160 

   161 protected:

   162    static int _cpu;

   163    static int _model;

   164    static int _stepping;

   165    static int _cpuFeatures;     // features returned by the "cpuid" instruction

   166                                 // 0 if this instruction is not available

   167    static const char* _features_str;

   168 

   169    enum {

   170      CPU_CX8  = (1 << 0), // next bits are from cpuid 1 (EDX)

   171      CPU_CMOV = (1 << 1),

   172      CPU_FXSR = (1 << 2),

   173      CPU_HT   = (1 << 3),

   174      CPU_MMX  = (1 << 4),

   175      CPU_3DNOW= (1 << 5), // 3DNow comes from cpuid 0x80000001 (EDX)

   176      CPU_SSE  = (1 << 6),

   177      CPU_SSE2 = (1 << 7),

   178      CPU_SSE3 = (1 << 8), // sse3  comes from cpuid 1 (ECX)

   179      CPU_SSSE3= (1 << 9),

   180      CPU_SSE4A= (1 <<10),

   181      CPU_SSE4_1 = (1 << 11),

   182      CPU_SSE4_2 = (1 << 12)

   183    } cpuFeatureFlags;

   184 

   185   // cpuid information block.  All info derived from executing cpuid with

   186   // various function numbers is stored here.  Intel and AMD info is

   187   // merged in this block: accessor methods disentangle it.

   188   //

   189   // The info block is laid out in subblocks of 4 dwords corresponding to

   190   // rax, rbx, rcx and rdx, whether or not they contain anything useful.

   191   struct CpuidInfo {

   192     // cpuid function 0

   193     uint32_t std_max_function;

   194     uint32_t std_vendor_name_0;

   195     uint32_t std_vendor_name_1;

   196     uint32_t std_vendor_name_2;

   197 

   198     // cpuid function 1

   199     StdCpuid1Eax std_cpuid1_rax;

   200     StdCpuid1Ebx std_cpuid1_rbx;

   201     StdCpuid1Ecx std_cpuid1_rcx;

   202     StdCpuid1Edx std_cpuid1_rdx;

   203 

   204     // cpuid function 4 (deterministic cache parameters)

   205     DcpCpuid4Eax dcp_cpuid4_rax;

   206     DcpCpuid4Ebx dcp_cpuid4_rbx;

   207     uint32_t     dcp_cpuid4_rcx; // unused currently

   208     uint32_t     dcp_cpuid4_rdx; // unused currently

   209 

   210     // cpuid function 0x80000000 // example, unused

   211     uint32_t ext_max_function;

   212     uint32_t ext_vendor_name_0;

   213     uint32_t ext_vendor_name_1;

   214     uint32_t ext_vendor_name_2;

   215 

   216     // cpuid function 0x80000001

   217     uint32_t     ext_cpuid1_rax; // reserved

   218     uint32_t     ext_cpuid1_rbx; // reserved

   219     ExtCpuid1Ecx ext_cpuid1_rcx;

   220     ExtCpuid1Edx ext_cpuid1_rdx;

   221 

   222     // cpuid functions 0x80000002 thru 0x80000004: example, unused

   223     uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;

   224     uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;

   225     uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;

   226 

   227     // cpuid function 0x80000005 //AMD L1, Intel reserved

   228     uint32_t     ext_cpuid5_rax; // unused currently

   229     uint32_t     ext_cpuid5_rbx; // reserved

   230     ExtCpuid5Ex  ext_cpuid5_rcx; // L1 data cache info (AMD)

   231     ExtCpuid5Ex  ext_cpuid5_rdx; // L1 instruction cache info (AMD)

   232 

   233     // cpuid function 0x80000008

   234     uint32_t     ext_cpuid8_rax; // unused currently

   235     uint32_t     ext_cpuid8_rbx; // reserved

   236     ExtCpuid8Ecx ext_cpuid8_rcx;

   237     uint32_t     ext_cpuid8_rdx; // reserved

   238   };

   239 

   240   // The actual cpuid info block

   241   static CpuidInfo _cpuid_info;

   242 

   243   // Extractors and predicates

   244   static uint32_t extended_cpu_family() {

   245     uint32_t result = _cpuid_info.std_cpuid1_rax.bits.family;

   246     result += _cpuid_info.std_cpuid1_rax.bits.ext_family;

   247     return result;

   248   }

   249   static uint32_t extended_cpu_model() {

   250     uint32_t result = _cpuid_info.std_cpuid1_rax.bits.model;

   251     result |= _cpuid_info.std_cpuid1_rax.bits.ext_model << 4;

   252     return result;

   253   }

   254   static uint32_t cpu_stepping() {

   255     uint32_t result = _cpuid_info.std_cpuid1_rax.bits.stepping;

   256     return result;

   257   }

   258   static uint logical_processor_count() {

   259     uint result = threads_per_core();

   260     return result;

   261   }

   262   static uint32_t feature_flags() {

   263     uint32_t result = 0;

   264     if (_cpuid_info.std_cpuid1_rdx.bits.cmpxchg8 != 0)

   265       result |= CPU_CX8;

   266     if (_cpuid_info.std_cpuid1_rdx.bits.cmov != 0)

   267       result |= CPU_CMOV;

   268     if (_cpuid_info.std_cpuid1_rdx.bits.fxsr != 0 || is_amd() &&

   269         _cpuid_info.ext_cpuid1_rdx.bits.fxsr != 0)

   270       result |= CPU_FXSR;

   271     // HT flag is set for multi-core processors also.

   272     if (threads_per_core() > 1)

   273       result |= CPU_HT;

   274     if (_cpuid_info.std_cpuid1_rdx.bits.mmx != 0 || is_amd() &&

   275         _cpuid_info.ext_cpuid1_rdx.bits.mmx != 0)

   276       result |= CPU_MMX;

   277     if (is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.tdnow != 0)

   278       result |= CPU_3DNOW;

   279     if (_cpuid_info.std_cpuid1_rdx.bits.sse != 0)

   280       result |= CPU_SSE;

   281     if (_cpuid_info.std_cpuid1_rdx.bits.sse2 != 0)

   282       result |= CPU_SSE2;

   283     if (_cpuid_info.std_cpuid1_rcx.bits.sse3 != 0)

   284       result |= CPU_SSE3;

   285     if (_cpuid_info.std_cpuid1_rcx.bits.ssse3 != 0)

   286       result |= CPU_SSSE3;

   287     if (is_amd() && _cpuid_info.ext_cpuid1_rcx.bits.sse4a != 0)

   288       result |= CPU_SSE4A;

   289     if (_cpuid_info.std_cpuid1_rcx.bits.sse4_1 != 0)

   290       result |= CPU_SSE4_1;

   291     if (_cpuid_info.std_cpuid1_rcx.bits.sse4_2 != 0)

   292       result |= CPU_SSE4_2;

   293     return result;

   294   }

   295 

   296   static void get_processor_features();

   297 

   298 public:

   299   // Offsets for cpuid asm stub

   300   static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }

   301   static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_rax); }

   302   static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_rax); }

   303   static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_rax); }

   304   static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_rax); }

   305   static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_rax); }

   306 

   307   // Initialization

   308   static void initialize();

   309 

   310   // Asserts

   311   static void assert_is_initialized() {

   312     assert(_cpuid_info.std_cpuid1_rax.bits.family != 0, "VM_Version not initialized");

   313   }

   314 

   315   //

   316   // Processor family:

   317   //       3   -  386

   318   //       4   -  486

   319   //       5   -  Pentium

   320   //       6   -  PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,

   321   //              Pentium M, Core Solo, Core Duo, Core2 Duo

   322   //    family 6 model:   9,        13,       14,        15

   323   //    0x0f   -  Pentium 4, Opteron

   324   //

   325   // Note: The cpu family should be used to select between

   326   //       instruction sequences which are valid on all Intel

   327   //       processors.  Use the feature test functions below to

   328   //       determine whether a particular instruction is supported.

   329   //

   330   static int  cpu_family()        { return _cpu;}

   331   static bool is_P6()             { return cpu_family() >= 6; }

   332 

   333   static bool is_amd()            { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'

   334   static bool is_intel()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'

   335 

   336   static uint cores_per_cpu()  {

   337     uint result = 1;

   338     if (is_intel()) {

   339       result = (_cpuid_info.dcp_cpuid4_rax.bits.cores_per_cpu + 1);

   340     } else if (is_amd()) {

   341       result = (_cpuid_info.ext_cpuid8_rcx.bits.cores_per_cpu + 1);

   342     }

   343     return result;

   344   }

   345 

   346   static uint threads_per_core()  {

   347     uint result = 1;

   348     if (_cpuid_info.std_cpuid1_rdx.bits.ht != 0) {

   349       result = _cpuid_info.std_cpuid1_rbx.bits.threads_per_cpu /

   350                cores_per_cpu();

   351     }

   352     return result;

   353   }

   354 

   355   static intx L1_data_cache_line_size()  {

   356     intx result = 0;

   357     if (is_intel()) {

   358       result = (_cpuid_info.dcp_cpuid4_rbx.bits.L1_line_size + 1);

   359     } else if (is_amd()) {

   360       result = _cpuid_info.ext_cpuid5_rcx.bits.L1_line_size;

   361     }

   362     if (result < 32) // not defined ?

   363       result = 32;   // 32 bytes by default on x86

   364     return result;

   365   }

   366 

   367   //

   368   // Feature identification

   369   //

   370   static bool supports_cpuid()    { return _cpuFeatures  != 0; }

   371   static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }

   372   static bool supports_cmov()     { return (_cpuFeatures & CPU_CMOV) != 0; }

   373   static bool supports_fxsr()     { return (_cpuFeatures & CPU_FXSR) != 0; }

   374   static bool supports_ht()       { return (_cpuFeatures & CPU_HT) != 0; }

   375   static bool supports_mmx()      { return (_cpuFeatures & CPU_MMX) != 0; }

   376   static bool supports_sse()      { return (_cpuFeatures & CPU_SSE) != 0; }

   377   static bool supports_sse2()     { return (_cpuFeatures & CPU_SSE2) != 0; }

   378   static bool supports_sse3()     { return (_cpuFeatures & CPU_SSE3) != 0; }

   379   static bool supports_ssse3()    { return (_cpuFeatures & CPU_SSSE3)!= 0; }

   380   static bool supports_sse4_1()   { return (_cpuFeatures & CPU_SSE4_1) != 0; }

   381   static bool supports_sse4_2()   { return (_cpuFeatures & CPU_SSE4_2) != 0; }

   382   //

   383   // AMD features

   384   //

   385   static bool supports_3dnow()    { return (_cpuFeatures & CPU_3DNOW) != 0; }

   386   static bool supports_mmx_ext()  { return is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.mmx_amd != 0; }

   387   static bool supports_3dnow2()   { return is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.tdnow2 != 0; }

   388   static bool supports_sse4a()    { return (_cpuFeatures & CPU_SSE4A) != 0; }

   389 

   390   static bool supports_compare_and_exchange() { return true; }

   391 

   392   static const char* cpu_features()           { return _features_str; }

   393 

   394   static intx allocate_prefetch_distance() {

   395     // This method should be called before allocate_prefetch_style().

   396     //

   397     // Hardware prefetching (distance/size in bytes):

   398     // Pentium 3 -  64 /  32

   399     // Pentium 4 - 256 / 128

   400     // Athlon    -  64 /  32 ????

   401     // Opteron   - 128 /  64 only when 2 sequential cache lines accessed

   402     // Core      - 128 /  64

   403     //

   404     // Software prefetching (distance in bytes / instruction with best score):

   405     // Pentium 3 - 128 / prefetchnta

   406     // Pentium 4 - 512 / prefetchnta

   407     // Athlon    - 128 / prefetchnta

   408     // Opteron   - 256 / prefetchnta

   409     // Core      - 256 / prefetchnta

   410     // It will be used only when AllocatePrefetchStyle > 0

   411 

   412     intx count = AllocatePrefetchDistance;

   413     if (count < 0) {   // default ?

   414       if (is_amd()) {  // AMD

   415         if (supports_sse2())

   416           count = 256; // Opteron

   417         else

   418           count = 128; // Athlon

   419       } else {         // Intel

   420         if (supports_sse2())

   421           if (cpu_family() == 6) {

   422             count = 256; // Pentium M, Core, Core2

   423           } else {

   424             count = 512; // Pentium 4

   425           }

   426         else

   427           count = 128; // Pentium 3 (and all other old CPUs)

   428       }

   429     }

   430     return count;

   431   }

   432   static intx allocate_prefetch_style() {

   433     assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");

   434     // Return 0 if AllocatePrefetchDistance was not defined or

   435     // prefetch instruction is not supported.

   436     return (AllocatePrefetchDistance > 0 &&

   437             (supports_3dnow() || supports_sse())) ? AllocatePrefetchStyle : 0;

   438   }

   439 };