src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.lir.amd64/src/org/graalvm/compiler/lir/amd64/vector/AMD64VectorFloatCompareOp.java
changeset 59095 03fbcd06b4c0
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59094:5d4c3724e4c7 59095:03fbcd06b4c0
       
     1 /*
       
     2  * Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved.
       
     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
       
     4  *
       
     5  * This code is free software; you can redistribute it and/or modify it
       
     6  * under the terms of the GNU General Public License version 2 only, as
       
     7  * published by the Free Software Foundation.
       
     8  *
       
     9  * This code is distributed in the hope that it will be useful, but WITHOUT
       
    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
       
    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
       
    12  * version 2 for more details (a copy is included in the LICENSE file that
       
    13  * accompanied this code).
       
    14  *
       
    15  * You should have received a copy of the GNU General Public License version
       
    16  * 2 along with this work; if not, write to the Free Software Foundation,
       
    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
       
    18  *
       
    19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
       
    20  * or visit www.oracle.com if you need additional information or have any
       
    21  * questions.
       
    22  */
       
    23 
       
    24 
       
    25 package org.graalvm.compiler.lir.amd64.vector;
       
    26 
       
    27 import static jdk.vm.ci.code.ValueUtil.asRegister;
       
    28 import static jdk.vm.ci.code.ValueUtil.isRegister;
       
    29 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
       
    30 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK;
       
    31 
       
    32 import org.graalvm.compiler.asm.amd64.AMD64Address;
       
    33 import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;
       
    34 import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexFloatCompareOp;
       
    35 import org.graalvm.compiler.asm.amd64.AVXKind.AVXSize;
       
    36 import org.graalvm.compiler.lir.LIRInstructionClass;
       
    37 import org.graalvm.compiler.lir.Opcode;
       
    38 import org.graalvm.compiler.lir.amd64.AMD64LIRInstruction;
       
    39 import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
       
    40 
       
    41 import jdk.vm.ci.meta.AllocatableValue;
       
    42 
       
    43 public class AMD64VectorFloatCompareOp extends AMD64LIRInstruction {
       
    44     public static final LIRInstructionClass<AMD64VectorFloatCompareOp> TYPE = LIRInstructionClass.create(AMD64VectorFloatCompareOp.class);
       
    45 
       
    46     @Opcode private final VexFloatCompareOp opcode;
       
    47     private final AVXSize size;
       
    48     @Def({REG}) protected AllocatableValue result;
       
    49     @Use({REG}) protected AllocatableValue x;
       
    50     @Use({REG, STACK}) protected AllocatableValue y;
       
    51     private final VexFloatCompareOp.Predicate predicate;
       
    52 
       
    53     public AMD64VectorFloatCompareOp(VexFloatCompareOp opcode, AVXSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y, VexFloatCompareOp.Predicate predicate) {
       
    54         super(TYPE);
       
    55         this.opcode = opcode;
       
    56         this.size = size;
       
    57         this.result = result;
       
    58         this.x = x;
       
    59         this.y = y;
       
    60         this.predicate = predicate;
       
    61     }
       
    62 
       
    63     @Override
       
    64     public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
       
    65         if (isRegister(y)) {
       
    66             opcode.emit(masm, size, asRegister(result), asRegister(x), asRegister(y), predicate);
       
    67         } else {
       
    68             opcode.emit(masm, size, asRegister(result), asRegister(x), (AMD64Address) crb.asAddress(y), predicate);
       
    69         }
       
    70     }
       
    71 
       
    72 }