2665 /* Simulator extensions to the ISA

  2666 

  2667    haltsim

  2668 

  2669    takes no arguments, causes the sim to enter a debug break and then

  2670    return from the simulator run() call with STATUS_HALT? The linking

  2671    code will call fatal() when it sees STATUS_HALT.

  2672 

  2673    blrt Xn, Wm

  2674    blrt Xn, #gpargs, #fpargs, #type

  2675    Xn holds the 64 bit x86 branch_address

  2676    call format is encoded either as immediate data in the call

  2677    or in register Wm. In the latter case

  2678      Wm[13..6] = #gpargs,

  2679      Wm[5..2] = #fpargs,

  2680      Wm[1,0] = #type

  2681 

  2682    calls the x86 code address 'branch_address' supplied in Xn passing

  2683    arguments taken from the general and floating point registers according

  2684    to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0

  2685    or v0 according to the the return type #type' where

  2686 

  2687    address branch_address;

  2688    uimm4 gpargs;

  2689    uimm4 fpargs;

  2690    enum ReturnType type;

  2691 

  2692    enum ReturnType

  2693      {

  2694        void_ret = 0,

  2695        int_ret = 1,

  2696        long_ret = 1,

  2697        obj_ret = 1, // i.e. same as long

  2698        float_ret = 2,

  2699        double_ret = 3

  2700      }

  2701 

  2702    notify

  2703 

  2704    notifies the simulator of a transfer of control. instr[14:0]

  2705    identifies the type of change of control.

  2706 

  2707    0 ==> initial entry to a method.

  2708 

  2709    1 ==> return into a method from a submethod call.

  2710 

  2711    2 ==> exit out of Java method code.

  2712 

  2713    3 ==> start execution for a new bytecode.

  2714 

  2715    in cases 1 and 2 the simulator is expected to use a JVM callback to

  2716    identify the name of the specific method being executed. in case 4

  2717    the simulator is expected to use a JVM callback to identify the

  2718    bytecode index.

  2719 

  2720    Instruction encodings

  2721    ---------------------

  2722 

  2723    These are encoded in the space with instr[28:25] = 00 which is

  2724    unallocated. Encodings are

  2725 

  2726                      10987654321098765432109876543210

  2727    PSEUDO_HALT   = 0x11100000000000000000000000000000

  2728    PSEUDO_BLRT  = 0x11000000000000000_______________

  2729    PSEUDO_BLRTR = 0x1100000000000000100000__________

  2730    PSEUDO_NOTIFY = 0x10100000000000000_______________

  2731 

  2732    instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY

  2733 

  2734    for BLRT

  2735      instr[14,11] = #gpargs, instr[10,7] = #fpargs

  2736      instr[6,5] = #type, instr[4,0] = Rn

  2737    for BLRTR

  2738      instr[9,5] = Rm, instr[4,0] = Rn

  2739    for NOTIFY

  2740      instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart

  2741 */

  2742 

  2743   enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start };

  2744 

  2745   virtual void notify(int type) {

  2746     if (UseBuiltinSim) {

  2747       starti;

  2748       //  109

  2749       f(0b101, 31, 29);

  2750       //  87654321098765

  2751       f(0b00000000000000, 28, 15);

  2752       f(type, 14, 0);

  2753     }

  2754   }

  2755 

  2756   void blrt(Register Rn, int gpargs, int fpargs, int type) {

  2757     if (UseBuiltinSim) {

  2758       starti;

  2759       f(0b110, 31 ,29);

  2760       f(0b00, 28, 25);

  2761       //  4321098765

  2762       f(0b0000000000, 24, 15);

  2763       f(gpargs, 14, 11);

  2764       f(fpargs, 10, 7);

  2765       f(type, 6, 5);

  2766       rf(Rn, 0);

  2767     } else {

  2768       blr(Rn);

  2769     }

  2770   }

  2771 

  2772   void blrt(Register Rn, Register Rm) {

  2773     if (UseBuiltinSim) {

  2774       starti;

  2775       f(0b110, 31 ,29);

  2776       f(0b00, 28, 25);

  2777       //  4321098765

  2778       f(0b0000000001, 24, 15);

  2779       //  43210

  2780       f(0b00000, 14, 10);

  2781       rf(Rm, 5);

  2782       rf(Rn, 0);

  2783     } else {

  2784       blr(Rn);

  2785     }

  2786   }

  2787 

  2788   void haltsim() {

  2789     starti;

  2790     f(0b111, 31 ,29);

  2791     f(0b00, 28, 27);

  2792     //  654321098765432109876543210

  2793     f(0b000000000000000000000000000, 26, 0);

  2794   }

  2795