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/*
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* Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*/
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package org.graalvm.compiler.lir.amd64.vector;
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import static jdk.vm.ci.code.ValueUtil.asRegister;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMOp.VPXOR;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMOp.VXORPD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMOp.VXORPS;
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import static org.graalvm.compiler.asm.amd64.AVXKind.AVXSize.XMM;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
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import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;
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import org.graalvm.compiler.asm.amd64.AVXKind;
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import org.graalvm.compiler.lir.LIRInstruction;
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import org.graalvm.compiler.lir.LIRInstructionClass;
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import org.graalvm.compiler.lir.amd64.AMD64LIRInstruction;
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import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
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import jdk.vm.ci.amd64.AMD64Kind;
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import jdk.vm.ci.code.Register;
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import jdk.vm.ci.meta.AllocatableValue;
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public class AMD64VectorClearOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<AMD64VectorClearOp> TYPE = LIRInstructionClass.create(AMD64VectorClearOp.class);
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protected @LIRInstruction.Def({REG}) AllocatableValue result;
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public AMD64VectorClearOp(AllocatableValue result) {
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this(TYPE, result);
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}
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protected AMD64VectorClearOp(LIRInstructionClass<? extends AMD64VectorClearOp> c, AllocatableValue result) {
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super(c);
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this.result = result;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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AMD64Kind kind = (AMD64Kind) result.getPlatformKind();
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Register register = asRegister(result);
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switch (kind.getScalar()) {
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case SINGLE:
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VXORPS.emit(masm, AVXKind.getRegisterSize(kind), register, register, register);
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break;
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case DOUBLE:
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VXORPD.emit(masm, AVXKind.getRegisterSize(kind), register, register, register);
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break;
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default:
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// on AVX1, YMM VPXOR is not supported - still it is possible to clear the whole YMM
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// register as the upper 128-bit are implicitly cleared by the AVX1 instruction.
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VPXOR.emit(masm, XMM, register, register, register);
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}
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}
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}
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