author | trims |
Thu, 27 May 2010 19:08:38 -0700 | |
changeset 5547 | f4b087cbb361 |
parent 1217 | 5eb97f366a6a |
child 7397 | 5b173b4ca846 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 2005, 2008, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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inline bool LinearScan::is_processed_reg_num(int reg_num) { |
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#ifndef _LP64 |
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// rsp and rbp (numbers 6 ancd 7) are ignored |
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assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below"); |
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assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below"); |
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assert(reg_num >= 0, "invalid reg_num"); |
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return reg_num < 6 || reg_num > 7; |
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#else |
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// rsp and rbp, r10, r15 (numbers 6 ancd 7) are ignored |
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assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below"); |
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assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below"); |
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assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below"); |
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assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below"); |
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assert(reg_num >= 0, "invalid reg_num"); |
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return reg_num < 12 || reg_num > 15; |
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#endif // _LP64 |
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} |
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inline int LinearScan::num_physical_regs(BasicType type) { |
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// Intel requires two cpu registers for long, |
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// but requires only one fpu register for double |
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if (LP64_ONLY(false &&) type == T_LONG) { |
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return 2; |
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} |
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return 1; |
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} |
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inline bool LinearScan::requires_adjacent_regs(BasicType type) { |
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return false; |
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} |
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inline bool LinearScan::is_caller_save(int assigned_reg) { |
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assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers"); |
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return true; // no callee-saved registers on Intel |
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} |
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inline void LinearScan::pd_add_temps(LIR_Op* op) { |
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switch (op->code()) { |
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case lir_tan: |
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case lir_sin: |
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case lir_cos: { |
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// The slow path for these functions may need to save and |
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// restore all live registers but we don't want to save and |
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// restore everything all the time, so mark the xmms as being |
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// killed. If the slow path were explicit or we could propagate |
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// live register masks down to the assembly we could do better |
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// but we don't have any easy way to do that right now. We |
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// could also consider not killing all xmm registers if we |
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// assume that slow paths are uncommon but it's not clear that |
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// would be a good idea. |
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if (UseSSE > 0) { |
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#ifndef PRODUCT |
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if (TraceLinearScanLevel >= 2) { |
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tty->print_cr("killing XMMs for trig"); |
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} |
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#endif |
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int op_id = op->id(); |
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for (int xmm = 0; xmm < FrameMap::nof_caller_save_xmm_regs; xmm++) { |
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LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(xmm); |
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add_temp(reg_num(opr), op_id, noUse, T_ILLEGAL); |
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} |
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} |
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break; |
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} |
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} |
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} |
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// Implementation of LinearScanWalker |
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inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) { |
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if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) { |
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assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only"); |
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_first_reg = pd_first_byte_reg; |
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_last_reg = pd_last_byte_reg; |
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return true; |
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} else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) { |
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_first_reg = pd_first_xmm_reg; |
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_last_reg = pd_last_xmm_reg; |
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return true; |
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} |
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return false; |
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} |
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class FpuStackAllocator VALUE_OBJ_CLASS_SPEC { |
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private: |
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Compilation* _compilation; |
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LinearScan* _allocator; |
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LIR_OpVisitState visitor; |
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LIR_List* _lir; |
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int _pos; |
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FpuStackSim _sim; |
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FpuStackSim _temp_sim; |
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bool _debug_information_computed; |
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LinearScan* allocator() { return _allocator; } |
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Compilation* compilation() const { return _compilation; } |
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// unified bailout support |
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void bailout(const char* msg) const { compilation()->bailout(msg); } |
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bool bailed_out() const { return compilation()->bailed_out(); } |
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int pos() { return _pos; } |
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void set_pos(int pos) { _pos = pos; } |
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LIR_Op* cur_op() { return lir()->instructions_list()->at(pos()); } |
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LIR_List* lir() { return _lir; } |
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void set_lir(LIR_List* lir) { _lir = lir; } |
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FpuStackSim* sim() { return &_sim; } |
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FpuStackSim* temp_sim() { return &_temp_sim; } |
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int fpu_num(LIR_Opr opr); |
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int tos_offset(LIR_Opr opr); |
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LIR_Opr to_fpu_stack_top(LIR_Opr opr, bool dont_check_offset = false); |
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// Helper functions for handling operations |
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void insert_op(LIR_Op* op); |
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void insert_exchange(int offset); |
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void insert_exchange(LIR_Opr opr); |
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void insert_free(int offset); |
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void insert_free_if_dead(LIR_Opr opr); |
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void insert_free_if_dead(LIR_Opr opr, LIR_Opr ignore); |
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void insert_copy(LIR_Opr from, LIR_Opr to); |
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void do_rename(LIR_Opr from, LIR_Opr to); |
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void do_push(LIR_Opr opr); |
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void pop_if_last_use(LIR_Op* op, LIR_Opr opr); |
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void pop_always(LIR_Op* op, LIR_Opr opr); |
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void clear_fpu_stack(LIR_Opr preserve); |
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void handle_op1(LIR_Op1* op1); |
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void handle_op2(LIR_Op2* op2); |
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void handle_opCall(LIR_OpCall* opCall); |
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void compute_debug_information(LIR_Op* op); |
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void allocate_exception_handler(XHandler* xhandler); |
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void allocate_block(BlockBegin* block); |
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#ifndef PRODUCT |
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void check_invalid_lir_op(LIR_Op* op); |
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#endif |
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// Helper functions for merging of fpu stacks |
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void merge_insert_add(LIR_List* instrs, FpuStackSim* cur_sim, int reg); |
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void merge_insert_xchg(LIR_List* instrs, FpuStackSim* cur_sim, int slot); |
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void merge_insert_pop(LIR_List* instrs, FpuStackSim* cur_sim); |
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bool merge_rename(FpuStackSim* cur_sim, FpuStackSim* sux_sim, int start_slot, int change_slot); |
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void merge_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, FpuStackSim* sux_sim); |
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void merge_cleanup_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, BitMap& live_fpu_regs); |
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bool merge_fpu_stack_with_successors(BlockBegin* block); |
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public: |
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LIR_Opr to_fpu_stack(LIR_Opr opr); // used by LinearScan for creation of debug information |
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FpuStackAllocator(Compilation* compilation, LinearScan* allocator); |
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void allocate(); |
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}; |