/*

 * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "asm/macroAssembler.hpp"

#include "interpreter/interp_masm.hpp"

#include "interpreter/interpreter.hpp"

#include "interpreter/interpreterRuntime.hpp"

#include "interpreter/templateTable.hpp"

#include "memory/universe.hpp"

#include "oops/cpCache.hpp"

#include "oops/methodData.hpp"

#include "oops/objArrayKlass.hpp"

#include "oops/oop.inline.hpp"

#include "prims/methodHandles.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/stubRoutines.hpp"

#include "runtime/synchronizer.hpp"

#define __ _masm->

//----------------------------------------------------------------------------------------------------

// Platform-dependent initialization

void TemplateTable::pd_initialize() {

  // No arm specific initialization

}

//----------------------------------------------------------------------------------------------------

// Address computation

// local variables

static inline Address iaddress(int n)            {

  return Address(Rlocals, Interpreter::local_offset_in_bytes(n));

}

static inline Address laddress(int n)            { return iaddress(n + 1); }

#ifndef AARCH64

static inline Address haddress(int n)            { return iaddress(n + 0); }

#endif // !AARCH64

static inline Address faddress(int n)            { return iaddress(n); }

static inline Address daddress(int n)            { return laddress(n); }

static inline Address aaddress(int n)            { return iaddress(n); }

void TemplateTable::get_local_base_addr(Register r, Register index) {

  __ sub(r, Rlocals, AsmOperand(index, lsl, Interpreter::logStackElementSize));

}

Address TemplateTable::load_iaddress(Register index, Register scratch) {

#ifdef AARCH64

  get_local_base_addr(scratch, index);

  return Address(scratch);

#else

  return Address(Rlocals, index, lsl, Interpreter::logStackElementSize, basic_offset, sub_offset);

#endif // AARCH64

}

Address TemplateTable::load_aaddress(Register index, Register scratch) {

  return load_iaddress(index, scratch);

}

Address TemplateTable::load_faddress(Register index, Register scratch) {

#ifdef __SOFTFP__

  return load_iaddress(index, scratch);

#else

  get_local_base_addr(scratch, index);

  return Address(scratch);

#endif // __SOFTFP__

}

Address TemplateTable::load_daddress(Register index, Register scratch) {

  get_local_base_addr(scratch, index);

  return Address(scratch, Interpreter::local_offset_in_bytes(1));

}

// At top of Java expression stack which may be different than SP.

// It isn't for category 1 objects.

static inline Address at_tos() {

  return Address(Rstack_top, Interpreter::expr_offset_in_bytes(0));

}

static inline Address at_tos_p1() {

  return Address(Rstack_top, Interpreter::expr_offset_in_bytes(1));

}

static inline Address at_tos_p2() {

  return Address(Rstack_top, Interpreter::expr_offset_in_bytes(2));

}

// 32-bit ARM:

// Loads double/long local into R0_tos_lo/R1_tos_hi with two

// separate ldr instructions (supports nonadjacent values).

// Used for longs in all modes, and for doubles in SOFTFP mode.

//

// AArch64: loads long local into R0_tos.

//

void TemplateTable::load_category2_local(Register Rlocal_index, Register tmp) {

  const Register Rlocal_base = tmp;

  assert_different_registers(Rlocal_index, tmp);

  get_local_base_addr(Rlocal_base, Rlocal_index);

#ifdef AARCH64

  __ ldr(R0_tos, Address(Rlocal_base, Interpreter::local_offset_in_bytes(1)));

#else

  __ ldr(R0_tos_lo, Address(Rlocal_base, Interpreter::local_offset_in_bytes(1)));

  __ ldr(R1_tos_hi, Address(Rlocal_base, Interpreter::local_offset_in_bytes(0)));

#endif // AARCH64

}

// 32-bit ARM:

// Stores R0_tos_lo/R1_tos_hi to double/long local with two

// separate str instructions (supports nonadjacent values).

// Used for longs in all modes, and for doubles in SOFTFP mode

//

// AArch64: stores R0_tos to long local.

//

void TemplateTable::store_category2_local(Register Rlocal_index, Register tmp) {

  const Register Rlocal_base = tmp;

  assert_different_registers(Rlocal_index, tmp);

  get_local_base_addr(Rlocal_base, Rlocal_index);

#ifdef AARCH64

  __ str(R0_tos, Address(Rlocal_base, Interpreter::local_offset_in_bytes(1)));

#else

  __ str(R0_tos_lo, Address(Rlocal_base, Interpreter::local_offset_in_bytes(1)));

  __ str(R1_tos_hi, Address(Rlocal_base, Interpreter::local_offset_in_bytes(0)));

#endif // AARCH64

}

// Returns address of Java array element using temp register as address base.

Address TemplateTable::get_array_elem_addr(BasicType elemType, Register array, Register index, Register temp) {

  int logElemSize = exact_log2(type2aelembytes(elemType));

  __ add_ptr_scaled_int32(temp, array, index, logElemSize);

  return Address(temp, arrayOopDesc::base_offset_in_bytes(elemType));

}

//----------------------------------------------------------------------------------------------------

// Condition conversion

AsmCondition convNegCond(TemplateTable::Condition cc) {

  switch (cc) {

    case TemplateTable::equal        : return ne;

    case TemplateTable::not_equal    : return eq;

    case TemplateTable::less         : return ge;

    case TemplateTable::less_equal   : return gt;

    case TemplateTable::greater      : return le;

    case TemplateTable::greater_equal: return lt;

  }

  ShouldNotReachHere();

  return nv;

}

//----------------------------------------------------------------------------------------------------

// Miscelaneous helper routines

// Store an oop (or NULL) at the address described by obj.

// Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).

// Also destroys new_val and obj.base().

static void do_oop_store(InterpreterMacroAssembler* _masm,

                         Address obj,

                         Register new_val,

                         Register tmp1,

                         Register tmp2,

                         Register tmp3,

                         BarrierSet::Name barrier,

                         bool precise,

                         bool is_null) {

  assert_different_registers(obj.base(), new_val, tmp1, tmp2, tmp3, noreg);

  switch (barrier) {

#if INCLUDE_ALL_GCS

    case BarrierSet::G1BarrierSet:

      {

        // flatten object address if needed

        assert (obj.mode() == basic_offset, "pre- or post-indexing is not supported here");

        const Register store_addr = obj.base();

        if (obj.index() != noreg) {

          assert (obj.disp() == 0, "index or displacement, not both");

#ifdef AARCH64

          __ add(store_addr, obj.base(), obj.index(), obj.extend(), obj.shift_imm());

#else

          assert(obj.offset_op() == add_offset, "addition is expected");

          __ add(store_addr, obj.base(), AsmOperand(obj.index(), obj.shift(), obj.shift_imm()));

#endif // AARCH64

        } else if (obj.disp() != 0) {

          __ add(store_addr, obj.base(), obj.disp());

        }

        __ g1_write_barrier_pre(store_addr, new_val, tmp1, tmp2, tmp3);

        if (is_null) {

          __ store_heap_oop_null(new_val, Address(store_addr));

        } else {

          // G1 barrier needs uncompressed oop for region cross check.

          Register val_to_store = new_val;

          if (UseCompressedOops) {

            val_to_store = tmp1;

            __ mov(val_to_store, new_val);

          }

          __ store_heap_oop(val_to_store, Address(store_addr)); // blows val_to_store:

          val_to_store = noreg;

          __ g1_write_barrier_post(store_addr, new_val, tmp1, tmp2, tmp3);

        }

      }

      break;

    case BarrierSet::Epsilon:

      {

        if (is_null) {

          __ store_heap_oop_null(new_val, obj);

        } else {

          __ store_heap_oop(new_val, obj); // blows new_val:

          new_val = noreg;

        }

      }

      break;

#endif // INCLUDE_ALL_GCS

    case BarrierSet::CardTableModRef:

      {

        if (is_null) {

          __ store_heap_oop_null(new_val, obj);

        } else {

          assert (!precise || (obj.index() == noreg && obj.disp() == 0),

                  "store check address should be calculated beforehand");

          __ store_check_part1(tmp1);

          __ store_heap_oop(new_val, obj); // blows new_val:

          new_val = noreg;

          __ store_check_part2(obj.base(), tmp1, tmp2);

        }

      }

      break;

    case BarrierSet::ModRef:

      ShouldNotReachHere();

      break;

    default:

      ShouldNotReachHere();

      break;

  }

}

Address TemplateTable::at_bcp(int offset) {

  assert(_desc->uses_bcp(), "inconsistent uses_bcp information");

  return Address(Rbcp, offset);

}

// Blows volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64), Rtemp, LR.

void TemplateTable::patch_bytecode(Bytecodes::Code bc, Register bc_reg,

                                   Register temp_reg, bool load_bc_into_bc_reg/*=true*/,

                                   int byte_no) {

  assert_different_registers(bc_reg, temp_reg);

  if (!RewriteBytecodes)  return;

  Label L_patch_done;

  switch (bc) {

  case Bytecodes::_fast_aputfield:

  case Bytecodes::_fast_bputfield:

  case Bytecodes::_fast_zputfield:

  case Bytecodes::_fast_cputfield:

  case Bytecodes::_fast_dputfield:

  case Bytecodes::_fast_fputfield:

  case Bytecodes::_fast_iputfield:

  case Bytecodes::_fast_lputfield:

  case Bytecodes::_fast_sputfield:

    {

      // We skip bytecode quickening for putfield instructions when

      // the put_code written to the constant pool cache is zero.

      // This is required so that every execution of this instruction

      // calls out to InterpreterRuntime::resolve_get_put to do

      // additional, required work.

      assert(byte_no == f1_byte || byte_no == f2_byte, "byte_no out of range");

      assert(load_bc_into_bc_reg, "we use bc_reg as temp");

      __ get_cache_and_index_and_bytecode_at_bcp(bc_reg, temp_reg, temp_reg, byte_no, 1, sizeof(u2));

      __ mov(bc_reg, bc);

      __ cbz(temp_reg, L_patch_done);  // test if bytecode is zero

    }

    break;

  default:

    assert(byte_no == -1, "sanity");

    // the pair bytecodes have already done the load.

    if (load_bc_into_bc_reg) {

      __ mov(bc_reg, bc);

    }

  }

  if (__ can_post_breakpoint()) {

    Label L_fast_patch;

    // if a breakpoint is present we can't rewrite the stream directly

    __ ldrb(temp_reg, at_bcp(0));

    __ cmp(temp_reg, Bytecodes::_breakpoint);

    __ b(L_fast_patch, ne);

    if (bc_reg != R3) {

      __ mov(R3, bc_reg);

    }

    __ mov(R1, Rmethod);

    __ mov(R2, Rbcp);

    // Let breakpoint table handling rewrite to quicker bytecode

    __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::set_original_bytecode_at), R1, R2, R3);

    __ b(L_patch_done);

    __ bind(L_fast_patch);

  }

#ifdef ASSERT

  Label L_okay;

  __ ldrb(temp_reg, at_bcp(0));

  __ cmp(temp_reg, (int)Bytecodes::java_code(bc));

  __ b(L_okay, eq);

  __ cmp(temp_reg, bc_reg);

  __ b(L_okay, eq);

  __ stop("patching the wrong bytecode");

  __ bind(L_okay);

#endif

  // patch bytecode

  __ strb(bc_reg, at_bcp(0));

  __ bind(L_patch_done);

}

//----------------------------------------------------------------------------------------------------

// Individual instructions

void TemplateTable::nop() {

  transition(vtos, vtos);

  // nothing to do

}

void TemplateTable::shouldnotreachhere() {

  transition(vtos, vtos);

  __ stop("shouldnotreachhere bytecode");

}

void TemplateTable::aconst_null() {

  transition(vtos, atos);

  __ mov(R0_tos, 0);

}

void TemplateTable::iconst(int value) {

  transition(vtos, itos);

  __ mov_slow(R0_tos, value);

}

void TemplateTable::lconst(int value) {

  transition(vtos, ltos);

  assert((value == 0) || (value == 1), "unexpected long constant");

  __ mov(R0_tos, value);

#ifndef AARCH64

  __ mov(R1_tos_hi, 0);

#endif // !AARCH64

}

void TemplateTable::fconst(int value) {

  transition(vtos, ftos);

#ifdef AARCH64

  switch(value) {

  case 0:   __ fmov_sw(S0_tos, ZR);    break;

  case 1:   __ fmov_s (S0_tos, 0x70);  break;

  case 2:   __ fmov_s (S0_tos, 0x00);  break;

  default:  ShouldNotReachHere();      break;

  }

#else

  const int zero = 0;         // 0.0f

  const int one = 0x3f800000; // 1.0f

  const int two = 0x40000000; // 2.0f

  switch(value) {

  case 0:   __ mov(R0_tos, zero);   break;

  case 1:   __ mov(R0_tos, one);    break;

  case 2:   __ mov(R0_tos, two);    break;

  default:  ShouldNotReachHere();   break;

  }

#ifndef __SOFTFP__

  __ fmsr(S0_tos, R0_tos);

#endif // !__SOFTFP__

#endif // AARCH64

}

void TemplateTable::dconst(int value) {

  transition(vtos, dtos);

#ifdef AARCH64

  switch(value) {

  case 0:   __ fmov_dx(D0_tos, ZR);    break;

  case 1:   __ fmov_d (D0_tos, 0x70);  break;

  default:  ShouldNotReachHere();      break;

  }

#else

  const int one_lo = 0;            // low part of 1.0

  const int one_hi = 0x3ff00000;   // high part of 1.0

  if (value == 0) {

#ifdef __SOFTFP__

    __ mov(R0_tos_lo, 0);

    __ mov(R1_tos_hi, 0);

#else

    __ mov(R0_tmp, 0);

    __ fmdrr(D0_tos, R0_tmp, R0_tmp);

#endif // __SOFTFP__

  } else if (value == 1) {

    __ mov(R0_tos_lo, one_lo);

    __ mov_slow(R1_tos_hi, one_hi);

#ifndef __SOFTFP__

    __ fmdrr(D0_tos, R0_tos_lo, R1_tos_hi);

#endif // !__SOFTFP__

  } else {

    ShouldNotReachHere();

  }

#endif // AARCH64

}

void TemplateTable::bipush() {

  transition(vtos, itos);

  __ ldrsb(R0_tos, at_bcp(1));

}

void TemplateTable::sipush() {

  transition(vtos, itos);

  __ ldrsb(R0_tmp, at_bcp(1));

  __ ldrb(R1_tmp, at_bcp(2));

  __ orr(R0_tos, R1_tmp, AsmOperand(R0_tmp, lsl, BitsPerByte));

}

void TemplateTable::ldc(bool wide) {

  transition(vtos, vtos);

  Label fastCase, Done;

  const Register Rindex = R1_tmp;

  const Register Rcpool = R2_tmp;

  const Register Rtags  = R3_tmp;

  const Register RtagType = R3_tmp;

  if (wide) {

    __ get_unsigned_2_byte_index_at_bcp(Rindex, 1);

  } else {

    __ ldrb(Rindex, at_bcp(1));

  }

  __ get_cpool_and_tags(Rcpool, Rtags);

  const int base_offset = ConstantPool::header_size() * wordSize;

  const int tags_offset = Array<u1>::base_offset_in_bytes();

  // get const type

  __ add(Rtemp, Rtags, tags_offset);

#ifdef AARCH64

  __ add(Rtemp, Rtemp, Rindex);

  __ ldarb(RtagType, Rtemp);  // TODO-AARCH64 figure out if barrier is needed here, or control dependency is enough

#else

  __ ldrb(RtagType, Address(Rtemp, Rindex));

  volatile_barrier(MacroAssembler::LoadLoad, Rtemp);

#endif // AARCH64

  // unresolved class - get the resolved class

  __ cmp(RtagType, JVM_CONSTANT_UnresolvedClass);

  // unresolved class in error (resolution failed) - call into runtime

  // so that the same error from first resolution attempt is thrown.

#ifdef AARCH64

  __ mov(Rtemp, JVM_CONSTANT_UnresolvedClassInError); // this constant does not fit into 5-bit immediate constraint

  __ cond_cmp(RtagType, Rtemp, ne);

#else

  __ cond_cmp(RtagType, JVM_CONSTANT_UnresolvedClassInError, ne);

#endif // AARCH64

  // resolved class - need to call vm to get java mirror of the class

  __ cond_cmp(RtagType, JVM_CONSTANT_Class, ne);

  __ b(fastCase, ne);

  // slow case - call runtime

  __ mov(R1, wide);

  call_VM(R0_tos, CAST_FROM_FN_PTR(address, InterpreterRuntime::ldc), R1);

  __ push(atos);

  __ b(Done);

  // int, float, String

  __ bind(fastCase);

#ifdef ASSERT

  { Label L;

    __ cmp(RtagType, JVM_CONSTANT_Integer);

    __ cond_cmp(RtagType, JVM_CONSTANT_Float, ne);

    __ b(L, eq);

    __ stop("unexpected tag type in ldc");

    __ bind(L);

  }

#endif // ASSERT

  // itos, ftos

  __ add(Rtemp, Rcpool, AsmOperand(Rindex, lsl, LogBytesPerWord));

  __ ldr_u32(R0_tos, Address(Rtemp, base_offset));

  // floats and ints are placed on stack in the same way, so

  // we can use push(itos) to transfer float value without VFP

  __ push(itos);

  __ bind(Done);

}