/*

 * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#ifndef CPU_ARM_VM_MACROASSEMBLER_ARM_HPP

#define CPU_ARM_VM_MACROASSEMBLER_ARM_HPP

#include "code/relocInfo.hpp"

#include "code/relocInfo_ext.hpp"

class BiasedLockingCounters;

// Introduced AddressLiteral and its subclasses to ease portability from

// x86 and avoid relocation issues

class AddressLiteral {

  RelocationHolder _rspec;

  // Typically we use AddressLiterals we want to use their rval

  // However in some situations we want the lval (effect address) of the item.

  // We provide a special factory for making those lvals.

  bool _is_lval;

  address          _target;

 private:

  static relocInfo::relocType reloc_for_target(address target) {

    // Used for ExternalAddress or when the type is not specified

    // Sometimes ExternalAddress is used for values which aren't

    // exactly addresses, like the card table base.

    // external_word_type can't be used for values in the first page

    // so just skip the reloc in that case.

    return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;

  }

  void set_rspec(relocInfo::relocType rtype);

 protected:

  // creation

  AddressLiteral()

    : _is_lval(false),

      _target(NULL)

  {}

  public:

  AddressLiteral(address target, relocInfo::relocType rtype) {

    _is_lval = false;

    _target = target;

    set_rspec(rtype);

  }

  AddressLiteral(address target, RelocationHolder const& rspec)

    : _rspec(rspec),

      _is_lval(false),

      _target(target)

  {}

  AddressLiteral(address target) {

    _is_lval = false;

    _target = target;

    set_rspec(reloc_for_target(target));

  }

  AddressLiteral addr() {

    AddressLiteral ret = *this;

    ret._is_lval = true;

    return ret;

  }

 private:

  address target() { return _target; }

  bool is_lval() { return _is_lval; }

  relocInfo::relocType reloc() const { return _rspec.type(); }

  const RelocationHolder& rspec() const { return _rspec; }

  friend class Assembler;

  friend class MacroAssembler;

  friend class Address;

  friend class LIR_Assembler;

  friend class InlinedAddress;

};

class ExternalAddress: public AddressLiteral {

  public:

  ExternalAddress(address target) : AddressLiteral(target) {}

};

class InternalAddress: public AddressLiteral {

  public:

  InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}

};

// Inlined constants, for use with ldr_literal / bind_literal

// Note: InlinedInteger not supported (use move_slow(Register,int[,cond]))

class InlinedLiteral: StackObj {

 public:

  Label label; // need to be public for direct access with &

  InlinedLiteral() {

  }

};

class InlinedMetadata: public InlinedLiteral {

 private:

  Metadata *_data;

 public:

  InlinedMetadata(Metadata *data): InlinedLiteral() {

    _data = data;

  }

  Metadata *data() { return _data; }

};

// Currently unused

// class InlinedOop: public InlinedLiteral {

//  private:

//   jobject _jobject;

//

//  public:

//   InlinedOop(jobject target): InlinedLiteral() {

//     _jobject = target;

//   }

//   jobject jobject() { return _jobject; }

// };

class InlinedAddress: public InlinedLiteral {

 private:

  AddressLiteral _literal;

 public:

  InlinedAddress(jobject object): InlinedLiteral(), _literal((address)object, relocInfo::oop_type) {

    ShouldNotReachHere(); // use mov_oop (or implement InlinedOop)

  }

  InlinedAddress(Metadata *data): InlinedLiteral(), _literal((address)data, relocInfo::metadata_type) {

    ShouldNotReachHere(); // use InlinedMetadata or mov_metadata

  }

  InlinedAddress(address target, const RelocationHolder &rspec): InlinedLiteral(), _literal(target, rspec) {

    assert(rspec.type() != relocInfo::oop_type, "Do not use InlinedAddress for oops");

    assert(rspec.type() != relocInfo::metadata_type, "Do not use InlinedAddress for metadatas");

  }

  InlinedAddress(address target, relocInfo::relocType rtype): InlinedLiteral(), _literal(target, rtype) {

    assert(rtype != relocInfo::oop_type, "Do not use InlinedAddress for oops");

    assert(rtype != relocInfo::metadata_type, "Do not use InlinedAddress for metadatas");

  }

  // Note: default is relocInfo::none for InlinedAddress

  InlinedAddress(address target): InlinedLiteral(), _literal(target, relocInfo::none) {

  }

  address target() { return _literal.target(); }

  const RelocationHolder& rspec() const { return _literal.rspec(); }

};

class InlinedString: public InlinedLiteral {

 private:

  const char* _msg;

 public:

  InlinedString(const char* msg): InlinedLiteral() {

    _msg = msg;

  }

  const char* msg() { return _msg; }

};

class MacroAssembler: public Assembler {

protected:

  // Support for VM calls

  //

  // This is the base routine called by the different versions of call_VM_leaf.

  void call_VM_leaf_helper(address entry_point, int number_of_arguments);

  // This is the base routine called by the different versions of call_VM. The interpreter

  // may customize this version by overriding it for its purposes (e.g., to save/restore

  // additional registers when doing a VM call).

  virtual void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions);

public:

  MacroAssembler(CodeBuffer* code) : Assembler(code) {}

  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.

  // The implementation is only non-empty for the InterpreterMacroAssembler,

  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.

  virtual void check_and_handle_popframe() {}

  virtual void check_and_handle_earlyret() {}

  // By default, we do not need relocation information for non

  // patchable absolute addresses. However, when needed by some

  // extensions, ignore_non_patchable_relocations can be modified,

  // returning false to preserve all relocation information.

  inline bool ignore_non_patchable_relocations() { return true; }

  // Initially added to the Assembler interface as a pure virtual:

  //   RegisterConstant delayed_value(..)

  // for:

  //   6812678 macro assembler needs delayed binding of a few constants (for 6655638)

  // this was subsequently modified to its present name and return type

  virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);

#ifdef AARCH64

# define NOT_IMPLEMENTED() unimplemented("NYI at " __FILE__ ":" XSTR(__LINE__))

# define NOT_TESTED()      warn("Not tested at " __FILE__ ":" XSTR(__LINE__))

#endif

  void align(int modulus);

  // Support for VM calls

  //

  // It is imperative that all calls into the VM are handled via the call_VM methods.

  // They make sure that the stack linkage is setup correctly. call_VM's correspond

  // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.

  void call_VM(Register oop_result, address entry_point, bool check_exceptions = true);

  void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);

  void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);

  void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);

  // The following methods are required by templateTable.cpp,

  // but not used on ARM.

  void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);

  void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);

  void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);

  void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);

  // Note: The super_call_VM calls are not used on ARM

  // Raw call, without saving/restoring registers, exception handling, etc.

  // Mainly used from various stubs.

  // Note: if 'save_R9_if_scratched' is true, call_VM may on some

  // platforms save values on the stack. Set it to false (and handle

  // R9 in the callers) if the top of the stack must not be modified

  // by call_VM.

  void call_VM(address entry_point, bool save_R9_if_scratched);

  void call_VM_leaf(address entry_point);

  void call_VM_leaf(address entry_point, Register arg_1);

  void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);

  void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);

  void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);

  void get_vm_result(Register oop_result, Register tmp);

  void get_vm_result_2(Register metadata_result, Register tmp);

  // Always sets/resets sp, which default to SP if (last_sp == noreg)

  // Optionally sets/resets fp (use noreg to avoid setting it)

  // Always sets/resets pc on AArch64; optionally sets/resets pc on 32-bit ARM depending on save_last_java_pc flag

  // Note: when saving PC, set_last_Java_frame returns PC's offset in the code section

  //       (for oop_maps offset computation)

  int set_last_Java_frame(Register last_sp, Register last_fp, bool save_last_java_pc, Register tmp);

  void reset_last_Java_frame(Register tmp);

  // status set in set_last_Java_frame for reset_last_Java_frame

  bool _fp_saved;

  bool _pc_saved;

#ifdef PRODUCT

#define BLOCK_COMMENT(str) /* nothing */

#define STOP(error) __ stop(error)

#else

#define BLOCK_COMMENT(str) __ block_comment(str)

#define STOP(error) __ block_comment(error); __ stop(error)

#endif

  void lookup_virtual_method(Register recv_klass,

                             Register vtable_index,

                             Register method_result);

  // Test sub_klass against super_klass, with fast and slow paths.

  // The fast path produces a tri-state answer: yes / no / maybe-slow.

  // One of the three labels can be NULL, meaning take the fall-through.

  // No registers are killed, except temp_regs.

  void check_klass_subtype_fast_path(Register sub_klass,

                                     Register super_klass,

                                     Register temp_reg,

                                     Register temp_reg2,

                                     Label* L_success,

                                     Label* L_failure,

                                     Label* L_slow_path);

  // The rest of the type check; must be wired to a corresponding fast path.

  // It does not repeat the fast path logic, so don't use it standalone.

  // temp_reg3 can be noreg, if no temps are available.

  // Updates the sub's secondary super cache as necessary.

  // If set_cond_codes:

  // - condition codes will be Z on success, NZ on failure.

  // - temp_reg will be 0 on success, non-0 on failure

  void check_klass_subtype_slow_path(Register sub_klass,

                                     Register super_klass,

                                     Register temp_reg,

                                     Register temp_reg2,

                                     Register temp_reg3, // auto assigned if noreg

                                     Label* L_success,

                                     Label* L_failure,

                                     bool set_cond_codes = false);

  // Simplified, combined version, good for typical uses.

  // temp_reg3 can be noreg, if no temps are available. It is used only on slow path.

  // Falls through on failure.

  void check_klass_subtype(Register sub_klass,

                           Register super_klass,

                           Register temp_reg,

                           Register temp_reg2,

                           Register temp_reg3, // auto assigned on slow path if noreg

                           Label& L_success);

  // Returns address of receiver parameter, using tmp as base register. tmp and params_count can be the same.

  Address receiver_argument_address(Register params_base, Register params_count, Register tmp);

  void _verify_oop(Register reg, const char* s, const char* file, int line);

  void _verify_oop_addr(Address addr, const char * s, const char* file, int line);

  // TODO: verify method and klass metadata (compare against vptr?)

  void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}

  void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}

#define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)

#define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop ", __FILE__, __LINE__)

#define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)

#define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)

  void null_check(Register reg, Register tmp, int offset = -1);

  inline void null_check(Register reg) { null_check(reg, noreg, -1); } // for C1 lir_null_check

  // Puts address of allocated object into register `obj` and end of allocated object into register `obj_end`.

  void eden_allocate(Register obj, Register obj_end, Register tmp1, Register tmp2,

                     RegisterOrConstant size_expression, Label& slow_case);

  void tlab_allocate(Register obj, Register obj_end, Register tmp1,

                     RegisterOrConstant size_expression, Label& slow_case);

  void zero_memory(Register start, Register end, Register tmp);

  void incr_allocated_bytes(RegisterOrConstant size_in_bytes, Register tmp);

  static bool needs_explicit_null_check(intptr_t offset);

  void arm_stack_overflow_check(int frame_size_in_bytes, Register tmp);

  void arm_stack_overflow_check(Register Rsize, Register tmp);

  void bang_stack_with_offset(int offset) {

    ShouldNotReachHere();

  }

  // Biased locking support

  // lock_reg and obj_reg must be loaded up with the appropriate values.

  // swap_reg must be supplied.

  // tmp_reg must be supplied.

  // Optional slow case is for implementations (interpreter and C1) which branch to

  // slow case directly. If slow_case is NULL, then leaves condition

  // codes set (for C2's Fast_Lock node) and jumps to done label.

  // Falls through for the fast locking attempt.

  // Returns offset of first potentially-faulting instruction for null

  // check info (currently consumed only by C1). If

  // swap_reg_contains_mark is true then returns -1 as it is assumed

  // the calling code has already passed any potential faults.

  // Notes:

  // - swap_reg and tmp_reg are scratched

  // - Rtemp was (implicitly) scratched and can now be specified as the tmp2

  int biased_locking_enter(Register obj_reg, Register swap_reg, Register tmp_reg,

                           bool swap_reg_contains_mark,

                           Register tmp2,

                           Label& done, Label& slow_case,

                           BiasedLockingCounters* counters = NULL);

  void biased_locking_exit(Register obj_reg, Register temp_reg, Label& done);

  // Building block for CAS cases of biased locking: makes CAS and records statistics.

  // Optional slow_case label is used to transfer control if CAS fails. Otherwise leaves condition codes set.

  void biased_locking_enter_with_cas(Register obj_reg, Register old_mark_reg, Register new_mark_reg,

                                     Register tmp, Label& slow_case, int* counter_addr);

  void resolve_jobject(Register value, Register tmp1, Register tmp2);

#if INCLUDE_ALL_GCS

  // G1 pre-barrier.

  // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).

  // If store_addr != noreg, then previous value is loaded from [store_addr];

  // in such case store_addr and new_val registers are preserved;

  // otherwise pre_val register is preserved.

  void g1_write_barrier_pre(Register store_addr,

                            Register new_val,

                            Register pre_val,

                            Register tmp1,

                            Register tmp2);

  // G1 post-barrier.

  // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).

  void g1_write_barrier_post(Register store_addr,

                             Register new_val,

                             Register tmp1,

                             Register tmp2,

                             Register tmp3);

#endif // INCLUDE_ALL_GCS

#ifndef AARCH64

  void nop() {

    mov(R0, R0);

  }

  void push(Register rd, AsmCondition cond = al) {

    assert(rd != SP, "unpredictable instruction");

    str(rd, Address(SP, -wordSize, pre_indexed), cond);

  }

  void push(RegisterSet reg_set, AsmCondition cond = al) {

    assert(!reg_set.contains(SP), "unpredictable instruction");

    stmdb(SP, reg_set, writeback, cond);

  }

  void pop(Register rd, AsmCondition cond = al) {

    assert(rd != SP, "unpredictable instruction");

    ldr(rd, Address(SP, wordSize, post_indexed), cond);

  }

  void pop(RegisterSet reg_set, AsmCondition cond = al) {

    assert(!reg_set.contains(SP), "unpredictable instruction");

    ldmia(SP, reg_set, writeback, cond);

  }

  void fpushd(FloatRegister fd, AsmCondition cond = al) {

    fstmdbd(SP, FloatRegisterSet(fd), writeback, cond);

  }

  void fpushs(FloatRegister fd, AsmCondition cond = al) {

    fstmdbs(SP, FloatRegisterSet(fd), writeback, cond);

  }

  void fpopd(FloatRegister fd, AsmCondition cond = al) {

    fldmiad(SP, FloatRegisterSet(fd), writeback, cond);

  }

  void fpops(FloatRegister fd, AsmCondition cond = al) {

    fldmias(SP, FloatRegisterSet(fd), writeback, cond);

  }

#endif // !AARCH64

  // Order access primitives

  enum Membar_mask_bits {

    StoreStore = 1 << 3,

    LoadStore  = 1 << 2,

    StoreLoad  = 1 << 1,

    LoadLoad   = 1 << 0

  };

#ifdef AARCH64

  // tmp register is not used on AArch64, this parameter is provided solely for better compatibility with 32-bit ARM

  void membar(Membar_mask_bits order_constraint, Register tmp = noreg);

#else

  void membar(Membar_mask_bits mask,

              Register tmp,

              bool preserve_flags = true,

              Register load_tgt = noreg);

#endif

  void breakpoint(AsmCondition cond = al);

  void stop(const char* msg);

  // prints msg and continues

  void warn(const char* msg);

  void unimplemented(const char* what = "");

  void should_not_reach_here()                   { stop("should not reach here"); }

  static void debug(const char* msg, const intx* registers);

  // Create a walkable frame to help tracking down who called this code.

  // Returns the frame size in words.

  int should_not_call_this() {

    raw_push(FP, LR);

    should_not_reach_here();

    flush();

    return 2; // frame_size_in_words (FP+LR)

  }

  int save_all_registers();

  void restore_all_registers();

  int save_caller_save_registers();

  void restore_caller_save_registers();

  void add_rc(Register dst, Register arg1, RegisterOrConstant arg2);

  // add_slow and mov_slow are used to manipulate offsets larger than 1024,

  // these functions are not expected to handle all possible constants,

  // only those that can really occur during compilation

  void add_slow(Register rd, Register rn, int c);

  void sub_slow(Register rd, Register rn, int c);

#ifdef AARCH64

  static int mov_slow_helper(Register rd, intptr_t c, MacroAssembler* masm /* optional */);

#endif

  void mov_slow(Register rd, intptr_t c NOT_AARCH64_ARG(AsmCondition cond = al));

  void mov_slow(Register rd, const char *string);

  void mov_slow(Register rd, address addr);

  void patchable_mov_oop(Register rd, jobject o, int oop_index) {

    mov_oop(rd, o, oop_index AARCH64_ONLY_ARG(true));

  }

  void mov_oop(Register rd, jobject o, int index = 0