author | eosterlund |
Wed, 21 Mar 2018 14:38:32 +0100 | |
changeset 49484 | ee8fa73b90f9 |
parent 49455 | 848864ed9b17 |
child 49734 | f946776e9354 |
permissions | -rw-r--r-- |
42664 | 1 |
/* |
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* Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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#include "precompiled.hpp" |
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#include "asm/assembler.hpp" |
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#include "asm/assembler.inline.hpp" |
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#include "ci/ciEnv.hpp" |
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#include "gc/shared/cardTableBarrierSet.hpp" |
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#include "gc/shared/collectedHeap.inline.hpp" |
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#include "interpreter/interpreter.hpp" |
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#include "interpreter/interpreterRuntime.hpp" |
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#include "interpreter/templateInterpreterGenerator.hpp" |
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#include "memory/resourceArea.hpp" |
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#include "prims/jvm_misc.hpp" |
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#include "prims/methodHandles.hpp" |
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#include "runtime/biasedLocking.hpp" |
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#include "runtime/interfaceSupport.inline.hpp" |
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#include "runtime/objectMonitor.hpp" |
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#include "runtime/os.hpp" |
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#include "runtime/sharedRuntime.hpp" |
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#include "runtime/stubRoutines.hpp" |
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#include "utilities/hashtable.hpp" |
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#include "utilities/macros.hpp" |
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#if INCLUDE_ALL_GCS |
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8195148: Collapse G1SATBCardTableModRefBS and G1SATBCardTableLoggingModRefBS into a single G1BarrierSet
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parents:
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#include "gc/g1/g1BarrierSet.hpp" |
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#include "gc/g1/g1CollectedHeap.inline.hpp" |
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#include "gc/g1/heapRegion.hpp" |
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#endif // INCLUDE_ALL_GCS |
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// Returns whether given imm has equal bit fields <0:size-1> and <size:2*size-1>. |
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inline bool Assembler::LogicalImmediate::has_equal_subpatterns(uintx imm, int size) { |
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uintx mask = right_n_bits(size); |
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uintx subpattern1 = mask_bits(imm, mask); |
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uintx subpattern2 = mask_bits(imm >> size, mask); |
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return subpattern1 == subpattern2; |
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} |
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// Returns least size that is a power of two from 2 to 64 with the proviso that given |
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// imm is composed of repeating patterns of this size. |
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inline int Assembler::LogicalImmediate::least_pattern_size(uintx imm) { |
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int size = BitsPerWord; |
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while (size > 2 && has_equal_subpatterns(imm, size >> 1)) { |
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size >>= 1; |
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} |
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return size; |
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} |
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// Returns count of set bits in given imm. Based on variable-precision SWAR algorithm. |
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inline int Assembler::LogicalImmediate::population_count(uintx x) { |
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x -= ((x >> 1) & 0x5555555555555555L); |
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x = (((x >> 2) & 0x3333333333333333L) + (x & 0x3333333333333333L)); |
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x = (((x >> 4) + x) & 0x0f0f0f0f0f0f0f0fL); |
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x += (x >> 8); |
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x += (x >> 16); |
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x += (x >> 32); |
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return(x & 0x7f); |
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} |
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// Let given x be <A:B> where B = 0 and least bit of A = 1. Returns <A:C>, where C is B-size set bits. |
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inline uintx Assembler::LogicalImmediate::set_least_zeroes(uintx x) { |
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return x | (x - 1); |
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} |
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#ifdef ASSERT |
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// Restores immediate by encoded bit masks. |
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uintx Assembler::LogicalImmediate::decode() { |
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assert (_encoded, "should be"); |
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int len_code = (_immN << 6) | ((~_imms) & 0x3f); |
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assert (len_code != 0, "should be"); |
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int len = 6; |
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while (!is_set_nth_bit(len_code, len)) len--; |
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int esize = 1 << len; |
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assert (len > 0, "should be"); |
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assert ((_is32bit ? 32 : 64) >= esize, "should be"); |
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int levels = right_n_bits(len); |
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int S = _imms & levels; |
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int R = _immr & levels; |
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assert (S != levels, "should be"); |
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uintx welem = right_n_bits(S + 1); |
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uintx wmask = (R == 0) ? welem : ((welem >> R) | (welem << (esize - R))); |
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for (int size = esize; size < 64; size <<= 1) { |
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wmask |= (wmask << size); |
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} |
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return wmask; |
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} |
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#endif |
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// Constructs LogicalImmediate by given imm. Figures out if given imm can be used in AArch64 logical |
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// instructions (AND, ANDS, EOR, ORR) and saves its encoding. |
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void Assembler::LogicalImmediate::construct(uintx imm, bool is32) { |
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_is32bit = is32; |
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if (is32) { |
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assert(((imm >> 32) == 0) || (((intx)imm >> 31) == -1), "32-bit immediate is out of range"); |
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// Replicate low 32 bits. |
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imm &= 0xffffffff; |
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imm |= imm << 32; |
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} |
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// All-zeroes and all-ones can not be encoded. |
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if (imm != 0 && (~imm != 0)) { |
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// Let LPS (least pattern size) be the least size (power of two from 2 to 64) of repeating |
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// patterns in the immediate. If immediate value can be encoded, it is encoded by pattern |
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// of exactly LPS size (due to structure of valid patterns). In order to verify |
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// that immediate value can be encoded, LPS is calculated and <LPS-1:0> bits of immediate |
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// are verified to be valid pattern. |
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int lps = least_pattern_size(imm); |
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uintx lps_mask = right_n_bits(lps); |
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// A valid pattern has one of the following forms: |
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// | 0 x A | 1 x B | 0 x C |, where B > 0 and C > 0, or |
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// | 1 x A | 0 x B | 1 x C |, where B > 0 and C > 0. |
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// For simplicity, the second form of the pattern is inverted into the first form. |
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bool inverted = imm & 0x1; |
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uintx pattern = (inverted ? ~imm : imm) & lps_mask; |
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// | 0 x A | 1 x (B + C) | |
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uintx without_least_zeroes = set_least_zeroes(pattern); |
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// Pattern is valid iff without least zeroes it is a power of two - 1. |
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if ((without_least_zeroes & (without_least_zeroes + 1)) == 0) { |
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// Count B as population count of pattern. |
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int bits_count = population_count(pattern); |
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// Count B+C as population count of pattern without least zeroes |
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int left_range = population_count(without_least_zeroes); |
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// S-prefix is a part of imms field which encodes LPS. |
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// LPS | S prefix |
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// 64 | not defined |
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// 32 | 0b0 |
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// 16 | 0b10 |
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// 8 | 0b110 |
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// 4 | 0b1110 |
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// 2 | 0b11110 |
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int s_prefix = (lps == 64) ? 0 : ~set_least_zeroes(lps) & 0x3f; |
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// immN bit is set iff LPS == 64. |
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_immN = (lps == 64) ? 1 : 0; |
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assert (!is32 || (_immN == 0), "32-bit immediate should be encoded with zero N-bit"); |
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// immr is the rotation size. |
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_immr = lps + (inverted ? 0 : bits_count) - left_range; |
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// imms is the field that encodes bits count and S-prefix. |
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_imms = ((inverted ? (lps - bits_count) : bits_count) - 1) | s_prefix; |
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_encoded = true; |
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assert (decode() == imm, "illegal encoding"); |
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return; |
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} |
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} |
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_encoded = false; |
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} |