/*

 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "compiler/compileLog.hpp"

#include "compiler/oopMap.hpp"

#include "memory/allocation.inline.hpp"

#include "opto/addnode.hpp"

#include "opto/block.hpp"

#include "opto/callnode.hpp"

#include "opto/cfgnode.hpp"

#include "opto/chaitin.hpp"

#include "opto/coalesce.hpp"

#include "opto/connode.hpp"

#include "opto/idealGraphPrinter.hpp"

#include "opto/indexSet.hpp"

#include "opto/machnode.hpp"

#include "opto/memnode.hpp"

#include "opto/opcodes.hpp"

#include "opto/rootnode.hpp"

//=============================================================================

#ifndef PRODUCT

void LRG::dump( ) const {

  ttyLocker ttyl;

  tty->print("%d ",num_regs());

  _mask.dump();

  if( _msize_valid ) {

    if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size);

    else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size());

  } else {

    tty->print(", #?(%d) ",_mask.Size());

  }

  tty->print("EffDeg: ");

  if( _degree_valid ) tty->print( "%d ", _eff_degree );

  else tty->print("? ");

  if( is_multidef() ) {

    tty->print("MultiDef ");

    if (_defs != NULL) {

      tty->print("(");

      for (int i = 0; i < _defs->length(); i++) {

        tty->print("N%d ", _defs->at(i)->_idx);

      }

      tty->print(") ");

    }

  }

  else if( _def == 0 ) tty->print("Dead ");

  else tty->print("Def: N%d ",_def->_idx);

  tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());

  // Flags

  if( _is_oop ) tty->print("Oop ");

  if( _is_float ) tty->print("Float ");

  if( _was_spilled1 ) tty->print("Spilled ");

  if( _was_spilled2 ) tty->print("Spilled2 ");

  if( _direct_conflict ) tty->print("Direct_conflict ");

  if( _fat_proj ) tty->print("Fat ");

  if( _was_lo ) tty->print("Lo ");

  if( _has_copy ) tty->print("Copy ");

  if( _at_risk ) tty->print("Risk ");

  if( _must_spill ) tty->print("Must_spill ");

  if( _is_bound ) tty->print("Bound ");

  if( _msize_valid ) {

    if( _degree_valid && lo_degree() ) tty->print("Trivial ");

  }

  tty->cr();

}

#endif

//------------------------------score------------------------------------------

// Compute score from cost and area.  Low score is best to spill.

static double raw_score( double cost, double area ) {

  return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;

}

double LRG::score() const {

  // Scale _area by RegisterCostAreaRatio/64K then subtract from cost.

  // Bigger area lowers score, encourages spilling this live range.

  // Bigger cost raise score, prevents spilling this live range.

  // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer

  // to turn a divide by a constant into a multiply by the reciprical).

  double score = raw_score( _cost, _area);

  // Account for area.  Basically, LRGs covering large areas are better

  // to spill because more other LRGs get freed up.

  if( _area == 0.0 )            // No area?  Then no progress to spill

    return 1e35;

  if( _was_spilled2 )           // If spilled once before, we are unlikely

    return score + 1e30;        // to make progress again.

  if( _cost >= _area*3.0 )      // Tiny area relative to cost

    return score + 1e17;        // Probably no progress to spill

  if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost

    return score + 1e10;        // Likely no progress to spill

  return score;

}

//------------------------------LRG_List---------------------------------------

LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) {

  memset( _lidxs, 0, sizeof(uint)*max );

}

void LRG_List::extend( uint nidx, uint lidx ) {

  _nesting.check();

  if( nidx >= _max ) {

    uint size = 16;

    while( size <= nidx ) size <<=1;

    _lidxs = REALLOC_RESOURCE_ARRAY( uint, _lidxs, _max, size );

    _max = size;

  }

  while( _cnt <= nidx )

    _lidxs[_cnt++] = 0;

  _lidxs[nidx] = lidx;

}

#define NUMBUCKS 3

//------------------------------Chaitin----------------------------------------

PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher)

  : PhaseRegAlloc(unique, cfg, matcher,

#ifndef PRODUCT

       print_chaitin_statistics

#else

       NULL

#endif

       ),

    _names(unique), _uf_map(unique),

    _maxlrg(0), _live(0),

    _spilled_once(Thread::current()->resource_area()),

    _spilled_twice(Thread::current()->resource_area()),

    _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0),

    _oldphi(unique)

#ifndef PRODUCT

  , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling"))

#endif

{

  NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); )

  _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg._outer_loop_freq);

  uint i,j;

  // Build a list of basic blocks, sorted by frequency

  _blks = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks );

  // Experiment with sorting strategies to speed compilation

  double  cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket

  Block **buckets[NUMBUCKS];             // Array of buckets

  uint    buckcnt[NUMBUCKS];             // Array of bucket counters

  double  buckval[NUMBUCKS];             // Array of bucket value cutoffs

  for( i = 0; i < NUMBUCKS; i++ ) {

    buckets[i] = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks );

    buckcnt[i] = 0;

    // Bump by three orders of magnitude each time

    cutoff *= 0.001;

    buckval[i] = cutoff;

    for( j = 0; j < _cfg._num_blocks; j++ ) {

      buckets[i][j] = NULL;

    }

  }

  // Sort blocks into buckets

  for( i = 0; i < _cfg._num_blocks; i++ ) {

    for( j = 0; j < NUMBUCKS; j++ ) {

      if( (j == NUMBUCKS-1) || (_cfg._blocks[i]->_freq > buckval[j]) ) {

        // Assign block to end of list for appropriate bucket

        buckets[j][buckcnt[j]++] = _cfg._blocks[i];

        break;                      // kick out of inner loop

      }

    }

  }

  // Dump buckets into final block array

  uint blkcnt = 0;

  for( i = 0; i < NUMBUCKS; i++ ) {

    for( j = 0; j < buckcnt[i]; j++ ) {

      _blks[blkcnt++] = buckets[i][j];

    }

  }

  assert(blkcnt == _cfg._num_blocks, "Block array not totally filled");

}

void PhaseChaitin::Register_Allocate() {

  // Above the OLD FP (and in registers) are the incoming arguments.  Stack

  // slots in this area are called "arg_slots".  Above the NEW FP (and in

  // registers) is the outgoing argument area; above that is the spill/temp

  // area.  These are all "frame_slots".  Arg_slots start at the zero

  // stack_slots and count up to the known arg_size.  Frame_slots start at

  // the stack_slot #arg_size and go up.  After allocation I map stack

  // slots to actual offsets.  Stack-slots in the arg_slot area are biased

  // by the frame_size; stack-slots in the frame_slot area are biased by 0.

  _trip_cnt = 0;

  _alternate = 0;

  _matcher._allocation_started = true;

  ResourceArea live_arena;      // Arena for liveness & IFG info

  ResourceMark rm(&live_arena);

  // Need live-ness for the IFG; need the IFG for coalescing.  If the

  // liveness is JUST for coalescing, then I can get some mileage by renaming

  // all copy-related live ranges low and then using the max copy-related

  // live range as a cut-off for LIVE and the IFG.  In other words, I can

  // build a subset of LIVE and IFG just for copies.

  PhaseLive live(_cfg,_names,&live_arena);

  // Need IFG for coalescing and coloring

  PhaseIFG ifg( &live_arena );

  _ifg = &ifg;

  if (C->unique() > _names.Size())  _names.extend(C->unique()-1, 0);

  // Come out of SSA world to the Named world.  Assign (virtual) registers to

  // Nodes.  Use the same register for all inputs and the output of PhiNodes

  // - effectively ending SSA form.  This requires either coalescing live

  // ranges or inserting copies.  For the moment, we insert "virtual copies"

  // - we pretend there is a copy prior to each Phi in predecessor blocks.

  // We will attempt to coalesce such "virtual copies" before we manifest

  // them for real.

  de_ssa();

#ifdef ASSERT

  // Veify the graph before RA.

  verify(&live_arena);

#endif

  {

    NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )

    _live = NULL;                 // Mark live as being not available

    rm.reset_to_mark();           // Reclaim working storage

    IndexSet::reset_memory(C, &live_arena);

    ifg.init(_maxlrg);            // Empty IFG

    gather_lrg_masks( false );    // Collect LRG masks

    live.compute( _maxlrg );      // Compute liveness

    _live = &live;                // Mark LIVE as being available

  }

  // Base pointers are currently "used" by instructions which define new

  // derived pointers.  This makes base pointers live up to the where the

  // derived pointer is made, but not beyond.  Really, they need to be live

  // across any GC point where the derived value is live.  So this code looks

  // at all the GC points, and "stretches" the live range of any base pointer

  // to the GC point.

  if( stretch_base_pointer_live_ranges(&live_arena) ) {

    NOT_PRODUCT( Compile::TracePhase t3("computeLive (sbplr)", &_t_computeLive, TimeCompiler); )

    // Since some live range stretched, I need to recompute live

    _live = NULL;

    rm.reset_to_mark();         // Reclaim working storage

    IndexSet::reset_memory(C, &live_arena);

    ifg.init(_maxlrg);

    gather_lrg_masks( false );

    live.compute( _maxlrg );

    _live = &live;

  }

  // Create the interference graph using virtual copies

  build_ifg_virtual( );  // Include stack slots this time

  // Aggressive (but pessimistic) copy coalescing.

  // This pass works on virtual copies.  Any virtual copies which are not

  // coalesced get manifested as actual copies

  {

    // The IFG is/was triangular.  I am 'squaring it up' so Union can run

    // faster.  Union requires a 'for all' operation which is slow on the

    // triangular adjacency matrix (quick reminder: the IFG is 'sparse' -

    // meaning I can visit all the Nodes neighbors less than a Node in time

    // O(# of neighbors), but I have to visit all the Nodes greater than a

    // given Node and search them for an instance, i.e., time O(#MaxLRG)).

    _ifg->SquareUp();

    PhaseAggressiveCoalesce coalesce( *this );

    coalesce.coalesce_driver( );

    // Insert un-coalesced copies.  Visit all Phis.  Where inputs to a Phi do

    // not match the Phi itself, insert a copy.

    coalesce.insert_copies(_matcher);

  }

  // After aggressive coalesce, attempt a first cut at coloring.

  // To color, we need the IFG and for that we need LIVE.

  {

    NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )

    _live = NULL;

    rm.reset_to_mark();           // Reclaim working storage

    IndexSet::reset_memory(C, &live_arena);

    ifg.init(_maxlrg);

    gather_lrg_masks( true );

    live.compute( _maxlrg );

    _live = &live;

  }

  // Build physical interference graph

  uint must_spill = 0;

  must_spill = build_ifg_physical( &live_arena );

  // If we have a guaranteed spill, might as well spill now

  if( must_spill ) {

    if( !_maxlrg ) return;

    // Bail out if unique gets too large (ie - unique > MaxNodeLimit)

    C->check_node_count(10*must_spill, "out of nodes before split");

    if (C->failing())  return;

    _maxlrg = Split( _maxlrg );        // Split spilling LRG everywhere

    // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)

    // or we failed to split

    C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split");

    if (C->failing())  return;

    NOT_PRODUCT( C->verify_graph_edges(); )

    compact();                  // Compact LRGs; return new lower max lrg

    {

      NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )

      _live = NULL;

      rm.reset_to_mark();         // Reclaim working storage

      IndexSet::reset_memory(C, &live_arena);

      ifg.init(_maxlrg);          // Build a new interference graph

      gather_lrg_masks( true );   // Collect intersect mask

      live.compute( _maxlrg );    // Compute LIVE

      _live = &live;

    }

    build_ifg_physical( &live_arena );

    _ifg->SquareUp();

    _ifg->Compute_Effective_Degree();

    // Only do conservative coalescing if requested

    if( OptoCoalesce ) {

      // Conservative (and pessimistic) copy coalescing of those spills

      PhaseConservativeCoalesce coalesce( *this );

      // If max live ranges greater than cutoff, don't color the stack.

      // This cutoff can be larger than below since it is only done once.

      coalesce.coalesce_driver( );

    }

    compress_uf_map_for_nodes();

#ifdef ASSERT

    verify(&live_arena, true);

#endif

  } else {

    ifg.SquareUp();

    ifg.Compute_Effective_Degree();

#ifdef ASSERT

    set_was_low();

#endif

  }

  // Prepare for Simplify & Select

  cache_lrg_info();           // Count degree of LRGs

  // Simplify the InterFerence Graph by removing LRGs of low degree.

  // LRGs of low degree are trivially colorable.

  Simplify();

  // Select colors by re-inserting LRGs back into the IFG in reverse order.

  // Return whether or not something spills.

  uint spills = Select( );

  // If we spill, split and recycle the entire thing

  while( spills ) {

    if( _trip_cnt++ > 24 ) {

      DEBUG_ONLY( dump_for_spill_split_recycle(); )

      if( _trip_cnt > 27 ) {

        C->record_method_not_compilable("failed spill-split-recycle sanity check");

        return;

      }

    }

    if( !_maxlrg ) return;

    _maxlrg = Split( _maxlrg );        // Split spilling LRG everywhere

    // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)

    C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after split");

    if (C->failing())  return;

    compact();                  // Compact LRGs; return new lower max lrg

    // Nuke the live-ness and interference graph and LiveRanGe info

    {

      NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )

      _live = NULL;

      rm.reset_to_mark();         // Reclaim working storage

      IndexSet::reset_memory(C, &live_arena);

      ifg.init(_maxlrg);

      // Create LiveRanGe array.

      // Intersect register masks for all USEs and DEFs

      gather_lrg_masks( true );

      live.compute( _maxlrg );

      _live = &live;

    }

    must_spill = build_ifg_physical( &live_arena );

    _ifg->SquareUp();

    _ifg->Compute_Effective_Degree();

    // Only do conservative coalescing if requested

    if( OptoCoalesce ) {

      // Conservative (and pessimistic) copy coalescing

      PhaseConservativeCoalesce coalesce( *this );

      // Check for few live ranges determines how aggressive coalesce is.

      coalesce.coalesce_driver( );

    }

    compress_uf_map_for_nodes();

#ifdef ASSERT

    verify(&live_arena, true);

#endif

    cache_lrg_info();           // Count degree of LRGs

    // Simplify the InterFerence Graph by removing LRGs of low degree.

    // LRGs of low degree are trivially colorable.

    Simplify();

    // Select colors by re-inserting LRGs back into the IFG in reverse order.

    // Return whether or not something spills.

    spills = Select( );

  }

  // Count number of Simplify-Select trips per coloring success.

  _allocator_attempts += _trip_cnt + 1;

  _allocator_successes += 1;

  // Peephole remove copies

  post_allocate_copy_removal();

#ifdef ASSERT

  // Veify the graph after RA.

  verify(&live_arena);

#endif

  // max_reg is past the largest *register* used.

  // Convert that to a frame_slot number.

  if( _max_reg <= _matcher._new_SP )

    _framesize = C->out_preserve_stack_slots();

  else _framesize = _max_reg -_matcher._new_SP;

  assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");

  // This frame must preserve the required fp alignment

  _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots());

  assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" );

#ifndef PRODUCT

  _total_framesize += _framesize;

  if( (int)_framesize > _max_framesize )

    _max_framesize = _framesize;

#endif

  // Convert CISC spills

  fixup_spills();

  // Log regalloc results

  CompileLog* log = Compile::current()->log();

  if (log != NULL) {

    log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());

  }

  if (C->failing())  return;

  NOT_PRODUCT( C->verify_graph_edges(); )

  // Move important info out of the live_arena to longer lasting storage.

  alloc_node_regs(_names.Size());

  for( uint i=0; i < _names.Size(); i++ ) {

    if( _names[i] ) {           // Live range associated with Node?

      LRG &lrg = lrgs( _names[i] );

      if( lrg.num_regs() == 1 ) {

        _node_regs[i].set1( lrg.reg() );

      } else {                  // Must be a register-pair

        if( !lrg._fat_proj ) {  // Must be aligned adjacent register pair

          // Live ranges record the highest register in their mask.

          // We want the low register for the AD file writer's convenience.

          _node_regs[i].set2( OptoReg::add(lrg.reg(),-1) );

        } else {                // Misaligned; extract 2 bits

          OptoReg::Name hi = lrg.reg(); // Get hi register

          lrg.Remove(hi);       // Yank from mask

          int lo = lrg.mask().find_first_elem(); // Find lo

          _node_regs[i].set_pair( hi, lo );

        }

      }

      if( lrg._is_oop ) _node_oops.set(i);

    } else {

      _node_regs[i].set_bad();

    }

  }

  // Done!

  _live = NULL;

  _ifg = NULL;

  C->set_indexSet_arena(NULL);  // ResourceArea is at end of scope

}

//------------------------------de_ssa-----------------------------------------

void PhaseChaitin::de_ssa() {

  // Set initial Names for all Nodes.  Most Nodes get the virtual register

  // number.  A few get the ZERO live range number.  These do not

  // get allocated, but instead rely on correct scheduling to ensure that

  // only one instance is simultaneously live at a time.

  uint lr_counter = 1;

  for( uint i = 0; i < _cfg._num_blocks; i++ ) {

    Block *b = _cfg._blocks[i];

    uint cnt = b->_nodes.size();

    // Handle all the normal Nodes in the block

    for( uint j = 0; j < cnt; j++ ) {

      Node *n = b->_nodes[j];

      // Pre-color to the zero live range, or pick virtual register