//

// Copyright (c) 2011, Oracle and/or its affiliates. All rights reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

//

// This code is free software; you can redistribute it and/or modify it

// under the terms of the GNU General Public License version 2 only, as

// published by the Free Software Foundation.

//

// This code is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// version 2 for more details (a copy is included in the LICENSE file that

// accompanied this code).

//

// You should have received a copy of the GNU General Public License version

// 2 along with this work; if not, write to the Free Software Foundation,

// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

//

// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

// or visit www.oracle.com if you need additional information or have any

// questions.

//

//

// X86 Common Architecture Description File

source %{

  // Float masks come from different places depending on platform.

#ifdef _LP64

  static address float_signmask()  { return StubRoutines::x86::float_sign_mask(); }

  static address float_signflip()  { return StubRoutines::x86::float_sign_flip(); }

  static address double_signmask() { return StubRoutines::x86::double_sign_mask(); }

  static address double_signflip() { return StubRoutines::x86::double_sign_flip(); }

#else

  static address float_signmask()  { return (address)float_signmask_pool; }

  static address float_signflip()  { return (address)float_signflip_pool; }

  static address double_signmask() { return (address)double_signmask_pool; }

  static address double_signflip() { return (address)double_signflip_pool; }

#endif

%}

// INSTRUCTIONS -- Platform independent definitions (same for 32- and 64-bit)

instruct addF_reg(regF dst, regF src) %{

  predicate((UseSSE>=1) && (UseAVX == 0));

  match(Set dst (AddF dst src));

  format %{ "addss   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ addss($dst$$XMMRegister, $src$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct addF_mem(regF dst, memory src) %{

  predicate((UseSSE>=1) && (UseAVX == 0));

  match(Set dst (AddF dst (LoadF src)));

  format %{ "addss   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ addss($dst$$XMMRegister, $src$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct addF_imm(regF dst, immF con) %{

  predicate((UseSSE>=1) && (UseAVX == 0));

  match(Set dst (AddF dst con));

  format %{ "addss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}

  ins_cost(150);

  ins_encode %{

    __ addss($dst$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct vaddF_reg(regF dst, regF src1, regF src2) %{

  predicate(UseAVX > 0);

  match(Set dst (AddF src1 src2));

  format %{ "vaddss  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct vaddF_mem(regF dst, regF src1, memory src2) %{

  predicate(UseAVX > 0);

  match(Set dst (AddF src1 (LoadF src2)));

  format %{ "vaddss  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct vaddF_imm(regF dst, regF src, immF con) %{

  predicate(UseAVX > 0);

  match(Set dst (AddF src con));

  format %{ "vaddss  $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}

  ins_cost(150);

  ins_encode %{

    __ vaddss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct addD_reg(regD dst, regD src) %{

  predicate((UseSSE>=2) && (UseAVX == 0));

  match(Set dst (AddD dst src));

  format %{ "addsd   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ addsd($dst$$XMMRegister, $src$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct addD_mem(regD dst, memory src) %{

  predicate((UseSSE>=2) && (UseAVX == 0));

  match(Set dst (AddD dst (LoadD src)));

  format %{ "addsd   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ addsd($dst$$XMMRegister, $src$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct addD_imm(regD dst, immD con) %{

  predicate((UseSSE>=2) && (UseAVX == 0));

  match(Set dst (AddD dst con));

  format %{ "addsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}

  ins_cost(150);

  ins_encode %{

    __ addsd($dst$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct vaddD_reg(regD dst, regD src1, regD src2) %{

  predicate(UseAVX > 0);

  match(Set dst (AddD src1 src2));

  format %{ "vaddsd  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct vaddD_mem(regD dst, regD src1, memory src2) %{

  predicate(UseAVX > 0);

  match(Set dst (AddD src1 (LoadD src2)));

  format %{ "vaddsd  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct vaddD_imm(regD dst, regD src, immD con) %{

  predicate(UseAVX > 0);

  match(Set dst (AddD src con));

  format %{ "vaddsd  $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}

  ins_cost(150);

  ins_encode %{

    __ vaddsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct subF_reg(regF dst, regF src) %{

  predicate((UseSSE>=1) && (UseAVX == 0));

  match(Set dst (SubF dst src));

  format %{ "subss   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ subss($dst$$XMMRegister, $src$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct subF_mem(regF dst, memory src) %{

  predicate((UseSSE>=1) && (UseAVX == 0));

  match(Set dst (SubF dst (LoadF src)));

  format %{ "subss   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ subss($dst$$XMMRegister, $src$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct subF_imm(regF dst, immF con) %{

  predicate((UseSSE>=1) && (UseAVX == 0));

  match(Set dst (SubF dst con));

  format %{ "subss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}

  ins_cost(150);

  ins_encode %{

    __ subss($dst$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct vsubF_reg(regF dst, regF src1, regF src2) %{

  predicate(UseAVX > 0);

  match(Set dst (SubF src1 src2));

  format %{ "vsubss  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct vsubF_mem(regF dst, regF src1, memory src2) %{

  predicate(UseAVX > 0);

  match(Set dst (SubF src1 (LoadF src2)));

  format %{ "vsubss  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct vsubF_imm(regF dst, regF src, immF con) %{

  predicate(UseAVX > 0);

  match(Set dst (SubF src con));

  format %{ "vsubss  $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}

  ins_cost(150);

  ins_encode %{

    __ vsubss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct subD_reg(regD dst, regD src) %{

  predicate((UseSSE>=2) && (UseAVX == 0));

  match(Set dst (SubD dst src));

  format %{ "subsd   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ subsd($dst$$XMMRegister, $src$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct subD_mem(regD dst, memory src) %{

  predicate((UseSSE>=2) && (UseAVX == 0));

  match(Set dst (SubD dst (LoadD src)));

  format %{ "subsd   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ subsd($dst$$XMMRegister, $src$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct subD_imm(regD dst, immD con) %{

  predicate((UseSSE>=2) && (UseAVX == 0));

  match(Set dst (SubD dst con));

  format %{ "subsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}

  ins_cost(150);

  ins_encode %{

    __ subsd($dst$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct vsubD_reg(regD dst, regD src1, regD src2) %{

  predicate(UseAVX > 0);

  match(Set dst (SubD src1 src2));

  format %{ "vsubsd  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct vsubD_mem(regD dst, regD src1, memory src2) %{

  predicate(UseAVX > 0);

  match(Set dst (SubD src1 (LoadD src2)));

  format %{ "vsubsd  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct vsubD_imm(regD dst, regD src, immD con) %{

  predicate(UseAVX > 0);

  match(Set dst (SubD src con));

  format %{ "vsubsd  $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}

  ins_cost(150);

  ins_encode %{

    __ vsubsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct mulF_reg(regF dst, regF src) %{

  predicate((UseSSE>=1) && (UseAVX == 0));

  match(Set dst (MulF dst src));

  format %{ "mulss   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ mulss($dst$$XMMRegister, $src$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct mulF_mem(regF dst, memory src) %{

  predicate((UseSSE>=1) && (UseAVX == 0));

  match(Set dst (MulF dst (LoadF src)));

  format %{ "mulss   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ mulss($dst$$XMMRegister, $src$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct mulF_imm(regF dst, immF con) %{

  predicate((UseSSE>=1) && (UseAVX == 0));

  match(Set dst (MulF dst con));

  format %{ "mulss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}

  ins_cost(150);

  ins_encode %{

    __ mulss($dst$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct vmulF_reg(regF dst, regF src1, regF src2) %{

  predicate(UseAVX > 0);

  match(Set dst (MulF src1 src2));

  format %{ "vmulss  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct vmulF_mem(regF dst, regF src1, memory src2) %{

  predicate(UseAVX > 0);

  match(Set dst (MulF src1 (LoadF src2)));

  format %{ "vmulss  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct vmulF_imm(regF dst, regF src, immF con) %{

  predicate(UseAVX > 0);

  match(Set dst (MulF src con));

  format %{ "vmulss  $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}

  ins_cost(150);

  ins_encode %{

    __ vmulss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct mulD_reg(regD dst, regD src) %{

  predicate((UseSSE>=2) && (UseAVX == 0));

  match(Set dst (MulD dst src));

  format %{ "mulsd   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ mulsd($dst$$XMMRegister, $src$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct mulD_mem(regD dst, memory src) %{

  predicate((UseSSE>=2) && (UseAVX == 0));

  match(Set dst (MulD dst (LoadD src)));

  format %{ "mulsd   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ mulsd($dst$$XMMRegister, $src$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct mulD_imm(regD dst, immD con) %{

  predicate((UseSSE>=2) && (UseAVX == 0));

  match(Set dst (MulD dst con));

  format %{ "mulsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}

  ins_cost(150);

  ins_encode %{

    __ mulsd($dst$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct vmulD_reg(regD dst, regD src1, regD src2) %{

  predicate(UseAVX > 0);

  match(Set dst (MulD src1 src2));

  format %{ "vmulsd  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct vmulD_mem(regD dst, regD src1, memory src2) %{

  predicate(UseAVX > 0);

  match(Set dst (MulD src1 (LoadD src2)));

  format %{ "vmulsd  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct vmulD_imm(regD dst, regD src, immD con) %{

  predicate(UseAVX > 0);

  match(Set dst (MulD src con));

  format %{ "vmulsd  $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}

  ins_cost(150);

  ins_encode %{

    __ vmulsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct divF_reg(regF dst, regF src) %{

  predicate((UseSSE>=1) && (UseAVX == 0));

  match(Set dst (DivF dst src));

  format %{ "divss   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ divss($dst$$XMMRegister, $src$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct divF_mem(regF dst, memory src) %{

  predicate((UseSSE>=1) && (UseAVX == 0));

  match(Set dst (DivF dst (LoadF src)));

  format %{ "divss   $dst, $src" %}

  ins_cost(150);

  ins_encode %{

    __ divss($dst$$XMMRegister, $src$$Address);

  %}

  ins_pipe(pipe_slow);

%}

instruct divF_imm(regF dst, immF con) %{

  predicate((UseSSE>=1) && (UseAVX == 0));

  match(Set dst (DivF dst con));

  format %{ "divss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}

  ins_cost(150);

  ins_encode %{

    __ divss($dst$$XMMRegister, $constantaddress($con));

  %}

  ins_pipe(pipe_slow);

%}

instruct vdivF_reg(regF dst, regF src1, regF src2) %{

  predicate(UseAVX > 0);

  match(Set dst (DivF src1 src2));

  format %{ "vdivss  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);

  %}

  ins_pipe(pipe_slow);

%}

instruct vdivF_mem(regF dst, regF src1, memory src2) %{

  predicate(UseAVX > 0);

  match(Set dst (DivF src1 (LoadF src2)));

  format %{ "vdivss  $dst, $src1, $src2" %}

  ins_cost(150);

  ins_encode %{

    __ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);

  %}

  ins_pipe(pipe_slow);

%}