hotspot/src/cpu/x86/vm/assembler_x86.inline.hpp
author kvn
Fri, 07 Nov 2008 09:29:38 -0800
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permissions -rw-r--r--
6462850: generate biased locking code in C2 ideal graph Summary: Inline biased locking code in C2 ideal graph during macro nodes expansion Reviewed-by: never
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/*
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 * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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 * CA 95054 USA or visit www.sun.com if you need additional information or
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 * have any questions.
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 *
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 */
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inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
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  unsigned char op = branch[0];
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  assert(op == 0xE8 /* call */ ||
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         op == 0xE9 /* jmp */ ||
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         op == 0xEB /* short jmp */ ||
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         (op & 0xF0) == 0x70 /* short jcc */ ||
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         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */,
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         "Invalid opcode at patch point");
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  if (op == 0xEB || (op & 0xF0) == 0x70) {
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    // short offset operators (jmp and jcc)
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    char* disp = (char*) &branch[1];
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    int imm8 = target - (address) &disp[1];
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    guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
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    *disp = imm8;
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  } else {
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    int* disp = (int*) &branch[(op == 0x0F)? 2: 1];
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    int imm32 = target - (address) &disp[1];
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    *disp = imm32;
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  }
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}
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#ifndef PRODUCT
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inline void MacroAssembler::pd_print_patched_instruction(address branch) {
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  const char* s;
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  unsigned char op = branch[0];
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  if (op == 0xE8) {
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    s = "call";
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  } else if (op == 0xE9 || op == 0xEB) {
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    s = "jmp";
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  } else if ((op & 0xF0) == 0x70) {
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    s = "jcc";
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  } else if (op == 0x0F) {
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    s = "jcc";
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  } else {
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    s = "????";
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  }
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  tty->print("%s (unresolved)", s);
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}
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#endif // ndef PRODUCT
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#ifndef _LP64
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inline int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { return reg_enc; }
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inline int Assembler::prefixq_and_encode(int reg_enc) { return reg_enc; }
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inline int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { return dst_enc << 3 | src_enc; }
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inline int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { return dst_enc << 3 | src_enc; }
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inline void Assembler::prefix(Register reg) {}
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inline void Assembler::prefix(Address adr) {}
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inline void Assembler::prefixq(Address adr) {}
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inline void Assembler::prefix(Address adr, Register reg,  bool byteinst) {}
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inline void Assembler::prefixq(Address adr, Register reg) {}
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inline void Assembler::prefix(Address adr, XMMRegister reg) {}
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#else
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inline void Assembler::emit_long64(jlong x) {
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  *(jlong*) _code_pos = x;
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  _code_pos += sizeof(jlong);
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  code_section()->set_end(_code_pos);
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}
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#endif // _LP64