hotspot/src/cpu/aarch64/vm/c1_FpuStackSim_aarch64.hpp
author kvn
Mon, 28 Dec 2015 23:11:01 -0800
changeset 35154 a9b3c1984a01
parent 29184 e234025cafb6
permissions -rw-r--r--
8143925: Enhancing CounterMode.crypt() for AES Summary: Add intrinsic for CounterMode.crypt() to leverage the parallel nature of AES in Counter(CTR) Mode. Reviewed-by: kvn, ascarpino Contributed-by: kishor.kharbas@intel.com
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/*
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 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
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 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#ifndef CPU_AARCH64_VM_C1_FPUSTACKSIM_HPP
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#define CPU_AARCH64_VM_C1_FPUSTACKSIM_HPP
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// No FPU stack on AARCH64
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class FpuStackSim;
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#endif // CPU_AARCH64_VM_C1_FPUSTACKSIM_HPP