hotspot/src/cpu/ppc/vm/c1_LIRAssembler_ppc.hpp
author mdoerr
Fri, 18 Mar 2016 12:50:17 +0100
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child 42650 1f304d0c888b
permissions -rw-r--r--
8152172: PPC64: Support AES intrinsics Reviewed-by: kvn, mdoerr, simonis Contributed-by: horii@jp.ibm.com
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/*
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 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
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 * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#ifndef CPU_PPC_VM_C1_LIRASSEMBLER_PPC_HPP
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#define CPU_PPC_VM_C1_LIRASSEMBLER_PPC_HPP
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 private:
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  //////////////////////////////////////////////////////////////////////////////
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  // PPC64 load/store emission
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  //
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  // The PPC ld/st instructions cannot accomodate displacements > 16 bits long.
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  // The following "pseudo" instructions (load/store) make it easier to
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  // use the indexed addressing mode by allowing 32 bit displacements:
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  //
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  void explicit_null_check(Register addr, CodeEmitInfo* info);
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  int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned);
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  int store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide);
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  int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned);
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  int load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide);
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  int shift_amount(BasicType t);
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  // Record the type of the receiver in ReceiverTypeData.
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  void type_profile_helper(Register mdo, int mdo_offset_bias,
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                           ciMethodData *md, ciProfileData *data,
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                           Register recv, Register tmp1, Label* update_done);
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  // Setup pointers to MDO, MDO slot, also compute offset bias to access the slot.
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  void setup_md_access(ciMethod* method, int bci,
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                       ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias);
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 public:
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  static const ConditionRegister BOOL_RESULT;
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  // Emit trampoline stub for call. Call bailout() if failed. Return true on success.
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  bool emit_trampoline_stub_for_call(address target, Register Rtoc = noreg);
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enum {
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  max_static_call_stub_size = 4 * BytesPerInstWord + MacroAssembler::b64_patchable_size,
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  call_stub_size = max_static_call_stub_size + MacroAssembler::trampoline_stub_size, // or smaller
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  exception_handler_size = MacroAssembler::b64_patchable_size, // or smaller
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  deopt_handler_size = MacroAssembler::bl64_patchable_size
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};
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#endif // CPU_PPC_VM_C1_LIRASSEMBLER_PPC_HPP