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/*
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* Copyright 2000-2005 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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* CA 95054 USA or visit www.sun.com if you need additional information or
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* have any questions.
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*
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*/
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class Arena;
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class Bundle;
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class Block;
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class Block_Array;
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class Node;
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class Node_Array;
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class Node_List;
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class PhaseCFG;
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class PhaseChaitin;
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class Pipeline_Use_Element;
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class Pipeline_Use;
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#ifndef PRODUCT
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#define DEBUG_ARG(x) , x
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#else
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#define DEBUG_ARG(x)
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#endif
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// Define the initial sizes for allocation of the resizable code buffer
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enum {
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initial_code_capacity = 16 * 1024,
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initial_stub_capacity = 4 * 1024,
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initial_const_capacity = 4 * 1024,
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initial_locs_capacity = 3 * 1024
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};
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//------------------------------Scheduling----------------------------------
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// This class contains all the information necessary to implement instruction
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// scheduling and bundling.
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class Scheduling {
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private:
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// Arena to use
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Arena *_arena;
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// Control-Flow Graph info
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PhaseCFG *_cfg;
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// Register Allocation info
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PhaseRegAlloc *_regalloc;
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// Number of nodes in the method
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uint _node_bundling_limit;
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// List of scheduled nodes. Generated in reverse order
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Node_List _scheduled;
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// List of nodes currently available for choosing for scheduling
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Node_List _available;
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// Mapping from node (index) to basic block
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Block_Array& _bbs;
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// For each instruction beginning a bundle, the number of following
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// nodes to be bundled with it.
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Bundle *_node_bundling_base;
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// Mapping from register to Node
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Node_List _reg_node;
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// Free list for pinch nodes.
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Node_List _pinch_free_list;
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// Latency from the beginning of the containing basic block (base 1)
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// for each node.
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unsigned short *_node_latency;
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// Number of uses of this node within the containing basic block.
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short *_uses;
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// Schedulable portion of current block. Skips Region/Phi/CreateEx up
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// front, branch+proj at end. Also skips Catch/CProj (same as
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// branch-at-end), plus just-prior exception-throwing call.
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uint _bb_start, _bb_end;
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// Latency from the end of the basic block as scheduled
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unsigned short *_current_latency;
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// Remember the next node
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Node *_next_node;
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// Use this for an unconditional branch delay slot
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Node *_unconditional_delay_slot;
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// Pointer to a Nop
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MachNopNode *_nop;
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// Length of the current bundle, in instructions
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uint _bundle_instr_count;
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// Current Cycle number, for computing latencies and bundling
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uint _bundle_cycle_number;
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// Bundle information
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Pipeline_Use_Element _bundle_use_elements[resource_count];
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Pipeline_Use _bundle_use;
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// Dump the available list
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void dump_available() const;
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public:
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Scheduling(Arena *arena, Compile &compile);
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// Destructor
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NOT_PRODUCT( ~Scheduling(); )
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// Step ahead "i" cycles
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void step(uint i);
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// Step ahead 1 cycle, and clear the bundle state (for example,
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// at a branch target)
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void step_and_clear();
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Bundle* node_bundling(const Node *n) {
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assert(valid_bundle_info(n), "oob");
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return (&_node_bundling_base[n->_idx]);
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}
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bool valid_bundle_info(const Node *n) const {
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return (_node_bundling_limit > n->_idx);
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}
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bool starts_bundle(const Node *n) const {
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return (_node_bundling_limit > n->_idx && _node_bundling_base[n->_idx].starts_bundle());
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}
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// Do the scheduling
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void DoScheduling();
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// Compute the local latencies walking forward over the list of
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// nodes for a basic block
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void ComputeLocalLatenciesForward(const Block *bb);
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// Compute the register antidependencies within a basic block
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void ComputeRegisterAntidependencies(Block *bb);
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void verify_do_def( Node *n, OptoReg::Name def, const char *msg );
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void verify_good_schedule( Block *b, const char *msg );
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void anti_do_def( Block *b, Node *def, OptoReg::Name def_reg, int is_def );
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void anti_do_use( Block *b, Node *use, OptoReg::Name use_reg );
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// Add a node to the current bundle
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void AddNodeToBundle(Node *n, const Block *bb);
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// Add a node to the list of available nodes
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void AddNodeToAvailableList(Node *n);
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// Compute the local use count for the nodes in a block, and compute
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// the list of instructions with no uses in the block as available
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void ComputeUseCount(const Block *bb);
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// Choose an instruction from the available list to add to the bundle
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Node * ChooseNodeToBundle();
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// See if this Node fits into the currently accumulating bundle
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bool NodeFitsInBundle(Node *n);
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// Decrement the use count for a node
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void DecrementUseCounts(Node *n, const Block *bb);
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// Garbage collect pinch nodes for reuse by other blocks.
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void garbage_collect_pinch_nodes();
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// Clean up a pinch node for reuse (helper for above).
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void cleanup_pinch( Node *pinch );
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// Information for statistics gathering
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#ifndef PRODUCT
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private:
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// Gather information on size of nops relative to total
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uint _branches, _unconditional_delays;
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static uint _total_nop_size, _total_method_size;
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static uint _total_branches, _total_unconditional_delays;
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static uint _total_instructions_per_bundle[Pipeline::_max_instrs_per_cycle+1];
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public:
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static void print_statistics();
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static void increment_instructions_per_bundle(uint i) {
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_total_instructions_per_bundle[i]++;
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}
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static void increment_nop_size(uint s) {
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_total_nop_size += s;
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}
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static void increment_method_size(uint s) {
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_total_method_size += s;
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}
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#endif
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};
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