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/*
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* Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*/
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package org.graalvm.compiler.lir.amd64;
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import static java.lang.Double.doubleToRawLongBits;
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import static java.lang.Float.floatToRawIntBits;
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import static jdk.vm.ci.code.ValueUtil.asRegister;
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import static jdk.vm.ci.code.ValueUtil.isRegister;
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import static jdk.vm.ci.code.ValueUtil.isStackSlot;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.ConditionFlag.Equal;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.ConditionFlag.NotEqual;
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import static org.graalvm.compiler.core.common.GraalOptions.GeneratePIC;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.COMPOSITE;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.CONST;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.HINT;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.ILLEGAL;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.UNINITIALIZED;
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import static org.graalvm.compiler.lir.LIRValueUtil.asJavaConstant;
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import static org.graalvm.compiler.lir.LIRValueUtil.isJavaConstant;
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import org.graalvm.compiler.asm.Label;
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import org.graalvm.compiler.asm.amd64.AMD64Address;
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import org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MIOp;
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import org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp;
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import org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize;
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import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;
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import org.graalvm.compiler.core.common.CompressEncoding;
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import org.graalvm.compiler.core.common.LIRKind;
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import org.graalvm.compiler.core.common.NumUtil;
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import org.graalvm.compiler.core.common.spi.LIRKindTool;
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import org.graalvm.compiler.core.common.type.DataPointerConstant;
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import org.graalvm.compiler.debug.GraalError;
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import org.graalvm.compiler.lir.LIRFrameState;
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import org.graalvm.compiler.lir.LIRInstructionClass;
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import org.graalvm.compiler.lir.Opcode;
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import org.graalvm.compiler.lir.StandardOp.LoadConstantOp;
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import org.graalvm.compiler.lir.StandardOp.NullCheck;
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import org.graalvm.compiler.lir.StandardOp.ValueMoveOp;
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import org.graalvm.compiler.lir.VirtualStackSlot;
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import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
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import org.graalvm.compiler.options.OptionValues;
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import jdk.vm.ci.amd64.AMD64;
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import jdk.vm.ci.amd64.AMD64Kind;
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import jdk.vm.ci.code.Register;
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import jdk.vm.ci.code.RegisterValue;
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import jdk.vm.ci.code.StackSlot;
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import jdk.vm.ci.meta.AllocatableValue;
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import jdk.vm.ci.meta.Constant;
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import jdk.vm.ci.meta.JavaConstant;
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import jdk.vm.ci.meta.Value;
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public class AMD64Move {
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private abstract static class AbstractMoveOp extends AMD64LIRInstruction implements ValueMoveOp {
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public static final LIRInstructionClass<AbstractMoveOp> TYPE = LIRInstructionClass.create(AbstractMoveOp.class);
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private AMD64Kind moveKind;
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protected AbstractMoveOp(LIRInstructionClass<? extends AbstractMoveOp> c, AMD64Kind moveKind) {
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super(c);
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this.moveKind = moveKind;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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move(moveKind, crb, masm, getResult(), getInput());
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}
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}
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@Opcode("MOVE")
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public static final class MoveToRegOp extends AbstractMoveOp {
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public static final LIRInstructionClass<MoveToRegOp> TYPE = LIRInstructionClass.create(MoveToRegOp.class);
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@Def({REG, HINT}) protected AllocatableValue result;
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@Use({REG, STACK}) protected AllocatableValue input;
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public MoveToRegOp(AMD64Kind moveKind, AllocatableValue result, AllocatableValue input) {
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super(TYPE, moveKind);
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this.result = result;
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this.input = input;
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}
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@Override
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public AllocatableValue getInput() {
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return input;
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}
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@Override
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public AllocatableValue getResult() {
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return result;
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}
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}
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@Opcode("MOVE")
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public static final class MoveFromRegOp extends AbstractMoveOp {
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public static final LIRInstructionClass<MoveFromRegOp> TYPE = LIRInstructionClass.create(MoveFromRegOp.class);
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@Def({REG, STACK}) protected AllocatableValue result;
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@Use({REG, HINT}) protected AllocatableValue input;
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public MoveFromRegOp(AMD64Kind moveKind, AllocatableValue result, AllocatableValue input) {
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super(TYPE, moveKind);
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this.result = result;
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this.input = input;
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}
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@Override
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public AllocatableValue getInput() {
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return input;
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}
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@Override
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public AllocatableValue getResult() {
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return result;
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}
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}
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@Opcode("MOVE")
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public static class MoveFromConstOp extends AMD64LIRInstruction implements LoadConstantOp {
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public static final LIRInstructionClass<MoveFromConstOp> TYPE = LIRInstructionClass.create(MoveFromConstOp.class);
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@Def({REG, STACK}) protected AllocatableValue result;
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private final JavaConstant input;
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public MoveFromConstOp(AllocatableValue result, JavaConstant input) {
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super(TYPE);
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this.result = result;
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this.input = input;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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if (isRegister(result)) {
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const2reg(crb, masm, asRegister(result), input, (AMD64Kind) result.getPlatformKind());
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} else {
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assert isStackSlot(result);
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const2stack(crb, masm, result, input);
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}
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}
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@Override
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public Constant getConstant() {
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return input;
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}
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@Override
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public AllocatableValue getResult() {
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return result;
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}
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}
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@Opcode("STACKMOVE")
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public static final class AMD64StackMove extends AMD64LIRInstruction implements ValueMoveOp {
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public static final LIRInstructionClass<AMD64StackMove> TYPE = LIRInstructionClass.create(AMD64StackMove.class);
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@Def({STACK}) protected AllocatableValue result;
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@Use({STACK, HINT}) protected AllocatableValue input;
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@Alive({OperandFlag.STACK, OperandFlag.UNINITIALIZED}) private AllocatableValue backupSlot;
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private Register scratch;
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public AMD64StackMove(AllocatableValue result, AllocatableValue input, Register scratch, AllocatableValue backupSlot) {
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super(TYPE);
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this.result = result;
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this.input = input;
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this.backupSlot = backupSlot;
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this.scratch = scratch;
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}
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@Override
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public AllocatableValue getInput() {
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return input;
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}
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@Override
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public AllocatableValue getResult() {
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return result;
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}
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public Register getScratchRegister() {
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return scratch;
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}
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public AllocatableValue getBackupSlot() {
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return backupSlot;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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AMD64Kind backupKind = (AMD64Kind) backupSlot.getPlatformKind();
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if (backupKind.isXMM()) {
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// graal doesn't use vector values, so it's safe to backup using DOUBLE
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backupKind = AMD64Kind.DOUBLE;
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}
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// backup scratch register
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reg2stack(backupKind, crb, masm, backupSlot, scratch);
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// move stack slot
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stack2reg((AMD64Kind) getInput().getPlatformKind(), crb, masm, scratch, getInput());
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reg2stack((AMD64Kind) getResult().getPlatformKind(), crb, masm, getResult(), scratch);
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// restore scratch register
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stack2reg(backupKind, crb, masm, scratch, backupSlot);
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}
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}
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@Opcode("MULTISTACKMOVE")
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public static final class AMD64MultiStackMove extends AMD64LIRInstruction {
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public static final LIRInstructionClass<AMD64MultiStackMove> TYPE = LIRInstructionClass.create(AMD64MultiStackMove.class);
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@Def({STACK}) protected AllocatableValue[] results;
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@Use({STACK}) protected Value[] inputs;
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@Alive({OperandFlag.STACK, OperandFlag.UNINITIALIZED}) private AllocatableValue backupSlot;
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private Register scratch;
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public AMD64MultiStackMove(AllocatableValue[] results, Value[] inputs, Register scratch, AllocatableValue backupSlot) {
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super(TYPE);
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this.results = results;
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this.inputs = inputs;
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this.backupSlot = backupSlot;
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this.scratch = scratch;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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AMD64Kind backupKind = (AMD64Kind) backupSlot.getPlatformKind();
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if (backupKind.isXMM()) {
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// graal doesn't use vector values, so it's safe to backup using DOUBLE
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backupKind = AMD64Kind.DOUBLE;
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}
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// backup scratch register
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move(backupKind, crb, masm, backupSlot, scratch.asValue(backupSlot.getValueKind()));
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for (int i = 0; i < results.length; i++) {
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Value input = inputs[i];
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AllocatableValue result = results[i];
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// move stack slot
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move((AMD64Kind) input.getPlatformKind(), crb, masm, scratch.asValue(input.getValueKind()), input);
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move((AMD64Kind) result.getPlatformKind(), crb, masm, result, scratch.asValue(result.getValueKind()));
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}
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// restore scratch register
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move(backupKind, crb, masm, scratch.asValue(backupSlot.getValueKind()), backupSlot);
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}
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}
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@Opcode("STACKMOVE")
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public static final class AMD64PushPopStackMove extends AMD64LIRInstruction implements ValueMoveOp {
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public static final LIRInstructionClass<AMD64PushPopStackMove> TYPE = LIRInstructionClass.create(AMD64PushPopStackMove.class);
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@Def({STACK}) protected AllocatableValue result;
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@Use({STACK, HINT}) protected AllocatableValue input;
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private final OperandSize size;
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public AMD64PushPopStackMove(OperandSize size, AllocatableValue result, AllocatableValue input) {
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super(TYPE);
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this.result = result;
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this.input = input;
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this.size = size;
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}
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@Override
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public AllocatableValue getInput() {
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return input;
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}
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@Override
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public AllocatableValue getResult() {
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return result;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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AMD64MOp.PUSH.emit(masm, size, (AMD64Address) crb.asAddress(input));
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AMD64MOp.POP.emit(masm, size, (AMD64Address) crb.asAddress(result));
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}
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}
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public static final class LeaOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<LeaOp> TYPE = LIRInstructionClass.create(LeaOp.class);
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@Def({REG}) protected AllocatableValue result;
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@Use({COMPOSITE, UNINITIALIZED}) protected AMD64AddressValue address;
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private final OperandSize size;
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public LeaOp(AllocatableValue result, AMD64AddressValue address, OperandSize size) {
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super(TYPE);
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this.result = result;
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this.address = address;
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this.size = size;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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if (size == OperandSize.QWORD) {
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masm.leaq(asRegister(result, AMD64Kind.QWORD), address.toAddress());
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} else {
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assert size == OperandSize.DWORD;
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masm.lead(asRegister(result, AMD64Kind.DWORD), address.toAddress());
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}
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}
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}
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public static final class LeaDataOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<LeaDataOp> TYPE = LIRInstructionClass.create(LeaDataOp.class);
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@Def({REG}) protected AllocatableValue result;
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private final DataPointerConstant data;
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public LeaDataOp(AllocatableValue result, DataPointerConstant data) {
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super(TYPE);
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this.result = result;
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this.data = data;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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masm.leaq(asRegister(result), (AMD64Address) crb.recordDataReferenceInCode(data));
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}
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}
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public static final class StackLeaOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<StackLeaOp> TYPE = LIRInstructionClass.create(StackLeaOp.class);
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@Def({REG}) protected AllocatableValue result;
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@Use({STACK, UNINITIALIZED}) protected AllocatableValue slot;
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public StackLeaOp(AllocatableValue result, AllocatableValue slot) {
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super(TYPE);
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this.result = result;
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this.slot = slot;
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assert slot instanceof VirtualStackSlot || slot instanceof StackSlot;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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masm.leaq(asRegister(result, AMD64Kind.QWORD), (AMD64Address) crb.asAddress(slot));
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}
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}
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public static final class MembarOp extends AMD64LIRInstruction {
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public static final LIRInstructionClass<MembarOp> TYPE = LIRInstructionClass.create(MembarOp.class);
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private final int barriers;
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public MembarOp(final int barriers) {
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super(TYPE);
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this.barriers = barriers;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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masm.membar(barriers);
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}
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}
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public static final class NullCheckOp extends AMD64LIRInstruction implements NullCheck {
|
|
382 |
public static final LIRInstructionClass<NullCheckOp> TYPE = LIRInstructionClass.create(NullCheckOp.class);
|
|
383 |
|
|
384 |
@Use({COMPOSITE}) protected AMD64AddressValue address;
|
|
385 |
@State protected LIRFrameState state;
|
|
386 |
|
|
387 |
public NullCheckOp(AMD64AddressValue address, LIRFrameState state) {
|
|
388 |
super(TYPE);
|
|
389 |
this.address = address;
|
|
390 |
this.state = state;
|
|
391 |
}
|
|
392 |
|
|
393 |
@Override
|
|
394 |
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
|
|
395 |
crb.recordImplicitException(masm.position(), state);
|
|
396 |
masm.nullCheck(address.toAddress());
|
|
397 |
}
|
|
398 |
|
|
399 |
@Override
|
|
400 |
public Value getCheckedValue() {
|
|
401 |
return address.base;
|
|
402 |
}
|
|
403 |
|
|
404 |
@Override
|
|
405 |
public LIRFrameState getState() {
|
|
406 |
return state;
|
|
407 |
}
|
|
408 |
}
|
|
409 |
|
|
410 |
@Opcode("CAS")
|
|
411 |
public static final class CompareAndSwapOp extends AMD64LIRInstruction {
|
|
412 |
public static final LIRInstructionClass<CompareAndSwapOp> TYPE = LIRInstructionClass.create(CompareAndSwapOp.class);
|
|
413 |
|
|
414 |
private final AMD64Kind accessKind;
|
|
415 |
|
|
416 |
@Def protected AllocatableValue result;
|
|
417 |
@Use({COMPOSITE}) protected AMD64AddressValue address;
|
|
418 |
@Use protected AllocatableValue cmpValue;
|
|
419 |
@Use protected AllocatableValue newValue;
|
|
420 |
|
|
421 |
public CompareAndSwapOp(AMD64Kind accessKind, AllocatableValue result, AMD64AddressValue address, AllocatableValue cmpValue, AllocatableValue newValue) {
|
|
422 |
super(TYPE);
|
|
423 |
this.accessKind = accessKind;
|
|
424 |
this.result = result;
|
|
425 |
this.address = address;
|
|
426 |
this.cmpValue = cmpValue;
|
|
427 |
this.newValue = newValue;
|
|
428 |
}
|
|
429 |
|
|
430 |
@Override
|
|
431 |
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
|
|
432 |
assert asRegister(cmpValue).equals(AMD64.rax) && asRegister(result).equals(AMD64.rax);
|
|
433 |
|
|
434 |
if (crb.target.isMP) {
|
|
435 |
masm.lock();
|
|
436 |
}
|
|
437 |
switch (accessKind) {
|
50330
|
438 |
case BYTE:
|
|
439 |
masm.cmpxchgb(asRegister(newValue), address.toAddress());
|
|
440 |
break;
|
|
441 |
case WORD:
|
|
442 |
masm.cmpxchgw(asRegister(newValue), address.toAddress());
|
|
443 |
break;
|
43972
|
444 |
case DWORD:
|
|
445 |
masm.cmpxchgl(asRegister(newValue), address.toAddress());
|
|
446 |
break;
|
|
447 |
case QWORD:
|
|
448 |
masm.cmpxchgq(asRegister(newValue), address.toAddress());
|
|
449 |
break;
|
|
450 |
default:
|
|
451 |
throw GraalError.shouldNotReachHere();
|
|
452 |
}
|
|
453 |
}
|
|
454 |
}
|
|
455 |
|
|
456 |
@Opcode("ATOMIC_READ_AND_ADD")
|
|
457 |
public static final class AtomicReadAndAddOp extends AMD64LIRInstruction {
|
|
458 |
public static final LIRInstructionClass<AtomicReadAndAddOp> TYPE = LIRInstructionClass.create(AtomicReadAndAddOp.class);
|
|
459 |
|
|
460 |
private final AMD64Kind accessKind;
|
|
461 |
|
|
462 |
@Def protected AllocatableValue result;
|
|
463 |
@Alive({COMPOSITE}) protected AMD64AddressValue address;
|
|
464 |
@Use protected AllocatableValue delta;
|
|
465 |
|
|
466 |
public AtomicReadAndAddOp(AMD64Kind accessKind, AllocatableValue result, AMD64AddressValue address, AllocatableValue delta) {
|
|
467 |
super(TYPE);
|
|
468 |
this.accessKind = accessKind;
|
|
469 |
this.result = result;
|
|
470 |
this.address = address;
|
|
471 |
this.delta = delta;
|
|
472 |
}
|
|
473 |
|
|
474 |
@Override
|
|
475 |
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
|
|
476 |
move(accessKind, crb, masm, result, delta);
|
|
477 |
if (crb.target.isMP) {
|
|
478 |
masm.lock();
|
|
479 |
}
|
|
480 |
switch (accessKind) {
|
50330
|
481 |
case BYTE:
|
|
482 |
masm.xaddb(address.toAddress(), asRegister(result));
|
|
483 |
break;
|
|
484 |
case WORD:
|
|
485 |
masm.xaddw(address.toAddress(), asRegister(result));
|
|
486 |
break;
|
43972
|
487 |
case DWORD:
|
|
488 |
masm.xaddl(address.toAddress(), asRegister(result));
|
|
489 |
break;
|
|
490 |
case QWORD:
|
|
491 |
masm.xaddq(address.toAddress(), asRegister(result));
|
|
492 |
break;
|
|
493 |
default:
|
|
494 |
throw GraalError.shouldNotReachHere();
|
|
495 |
}
|
|
496 |
}
|
|
497 |
}
|
|
498 |
|
|
499 |
@Opcode("ATOMIC_READ_AND_WRITE")
|
|
500 |
public static final class AtomicReadAndWriteOp extends AMD64LIRInstruction {
|
|
501 |
public static final LIRInstructionClass<AtomicReadAndWriteOp> TYPE = LIRInstructionClass.create(AtomicReadAndWriteOp.class);
|
|
502 |
|
|
503 |
private final AMD64Kind accessKind;
|
|
504 |
|
|
505 |
@Def protected AllocatableValue result;
|
|
506 |
@Alive({COMPOSITE}) protected AMD64AddressValue address;
|
|
507 |
@Use protected AllocatableValue newValue;
|
|
508 |
|
|
509 |
public AtomicReadAndWriteOp(AMD64Kind accessKind, AllocatableValue result, AMD64AddressValue address, AllocatableValue newValue) {
|
|
510 |
super(TYPE);
|
|
511 |
this.accessKind = accessKind;
|
|
512 |
this.result = result;
|
|
513 |
this.address = address;
|
|
514 |
this.newValue = newValue;
|
|
515 |
}
|
|
516 |
|
|
517 |
@Override
|
|
518 |
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
|
|
519 |
move(accessKind, crb, masm, result, newValue);
|
|
520 |
switch (accessKind) {
|
50330
|
521 |
case BYTE:
|
|
522 |
masm.xchgb(asRegister(result), address.toAddress());
|
|
523 |
break;
|
|
524 |
case WORD:
|
|
525 |
masm.xchgw(asRegister(result), address.toAddress());
|
|
526 |
break;
|
43972
|
527 |
case DWORD:
|
|
528 |
masm.xchgl(asRegister(result), address.toAddress());
|
|
529 |
break;
|
|
530 |
case QWORD:
|
|
531 |
masm.xchgq(asRegister(result), address.toAddress());
|
|
532 |
break;
|
|
533 |
default:
|
|
534 |
throw GraalError.shouldNotReachHere();
|
|
535 |
}
|
|
536 |
}
|
|
537 |
}
|
|
538 |
|
|
539 |
public static void move(CompilationResultBuilder crb, AMD64MacroAssembler masm, Value result, Value input) {
|
|
540 |
move((AMD64Kind) result.getPlatformKind(), crb, masm, result, input);
|
|
541 |
}
|
|
542 |
|
|
543 |
public static void move(AMD64Kind moveKind, CompilationResultBuilder crb, AMD64MacroAssembler masm, Value result, Value input) {
|
|
544 |
if (isRegister(input)) {
|
|
545 |
if (isRegister(result)) {
|
|
546 |
reg2reg(moveKind, masm, result, input);
|
|
547 |
} else if (isStackSlot(result)) {
|
|
548 |
reg2stack(moveKind, crb, masm, result, asRegister(input));
|
|
549 |
} else {
|
|
550 |
throw GraalError.shouldNotReachHere();
|
|
551 |
}
|
|
552 |
} else if (isStackSlot(input)) {
|
|
553 |
if (isRegister(result)) {
|
|
554 |
stack2reg(moveKind, crb, masm, asRegister(result), input);
|
|
555 |
} else {
|
|
556 |
throw GraalError.shouldNotReachHere();
|
|
557 |
}
|
|
558 |
} else if (isJavaConstant(input)) {
|
|
559 |
if (isRegister(result)) {
|
57537
|
560 |
const2reg(crb, masm, asRegister(result), asJavaConstant(input), moveKind);
|
43972
|
561 |
} else if (isStackSlot(result)) {
|
|
562 |
const2stack(crb, masm, result, asJavaConstant(input));
|
|
563 |
} else {
|
|
564 |
throw GraalError.shouldNotReachHere();
|
|
565 |
}
|
|
566 |
} else {
|
|
567 |
throw GraalError.shouldNotReachHere();
|
|
568 |
}
|
|
569 |
}
|
|
570 |
|
|
571 |
private static void reg2reg(AMD64Kind kind, AMD64MacroAssembler masm, Value result, Value input) {
|
|
572 |
if (asRegister(input).equals(asRegister(result))) {
|
|
573 |
return;
|
|
574 |
}
|
51436
|
575 |
assert asRegister(result).getRegisterCategory().equals(asRegister(input).getRegisterCategory());
|
43972
|
576 |
switch (kind) {
|
|
577 |
case BYTE:
|
|
578 |
case WORD:
|
|
579 |
case DWORD:
|
|
580 |
masm.movl(asRegister(result), asRegister(input));
|
|
581 |
break;
|
|
582 |
case QWORD:
|
|
583 |
masm.movq(asRegister(result), asRegister(input));
|
|
584 |
break;
|
|
585 |
case SINGLE:
|
|
586 |
masm.movflt(asRegister(result, AMD64Kind.SINGLE), asRegister(input, AMD64Kind.SINGLE));
|
|
587 |
break;
|
|
588 |
case DOUBLE:
|
|
589 |
masm.movdbl(asRegister(result, AMD64Kind.DOUBLE), asRegister(input, AMD64Kind.DOUBLE));
|
|
590 |
break;
|
|
591 |
default:
|
|
592 |
throw GraalError.shouldNotReachHere("kind=" + kind);
|
|
593 |
}
|
|
594 |
}
|
|
595 |
|
|
596 |
public static void reg2stack(AMD64Kind kind, CompilationResultBuilder crb, AMD64MacroAssembler masm, Value result, Register input) {
|
|
597 |
AMD64Address dest = (AMD64Address) crb.asAddress(result);
|
|
598 |
switch (kind) {
|
|
599 |
case BYTE:
|
|
600 |
masm.movb(dest, input);
|
|
601 |
break;
|
|
602 |
case WORD:
|
|
603 |
masm.movw(dest, input);
|
|
604 |
break;
|
|
605 |
case DWORD:
|
|
606 |
masm.movl(dest, input);
|
|
607 |
break;
|
|
608 |
case QWORD:
|
|
609 |
masm.movq(dest, input);
|
|
610 |
break;
|
|
611 |
case SINGLE:
|
|
612 |
masm.movflt(dest, input);
|
|
613 |
break;
|
|
614 |
case DOUBLE:
|
|
615 |
masm.movsd(dest, input);
|
|
616 |
break;
|
|
617 |
default:
|
|
618 |
throw GraalError.shouldNotReachHere();
|
|
619 |
}
|
|
620 |
}
|
|
621 |
|
|
622 |
public static void stack2reg(AMD64Kind kind, CompilationResultBuilder crb, AMD64MacroAssembler masm, Register result, Value input) {
|
|
623 |
AMD64Address src = (AMD64Address) crb.asAddress(input);
|
|
624 |
switch (kind) {
|
|
625 |
case BYTE:
|
|
626 |
masm.movsbl(result, src);
|
|
627 |
break;
|
|
628 |
case WORD:
|
|
629 |
masm.movswl(result, src);
|
|
630 |
break;
|
|
631 |
case DWORD:
|
|
632 |
masm.movl(result, src);
|
|
633 |
break;
|
|
634 |
case QWORD:
|
|
635 |
masm.movq(result, src);
|
|
636 |
break;
|
|
637 |
case SINGLE:
|
|
638 |
masm.movflt(result, src);
|
|
639 |
break;
|
|
640 |
case DOUBLE:
|
|
641 |
masm.movdbl(result, src);
|
|
642 |
break;
|
|
643 |
default:
|
|
644 |
throw GraalError.shouldNotReachHere();
|
|
645 |
}
|
|
646 |
}
|
|
647 |
|
57537
|
648 |
public static void const2reg(CompilationResultBuilder crb, AMD64MacroAssembler masm, Register result, JavaConstant input, AMD64Kind moveKind) {
|
43972
|
649 |
/*
|
|
650 |
* Note: we use the kind of the input operand (and not the kind of the result operand)
|
|
651 |
* because they don't match in all cases. For example, an object constant can be loaded to a
|
|
652 |
* long register when unsafe casts occurred (e.g., for a write barrier where arithmetic
|
|
653 |
* operations are then performed on the pointer).
|
|
654 |
*/
|
|
655 |
switch (input.getJavaKind().getStackKind()) {
|
|
656 |
case Int:
|
|
657 |
// Do not optimize with an XOR as this instruction may be between
|
|
658 |
// a CMP and a Jcc in which case the XOR will modify the condition
|
|
659 |
// flags and interfere with the Jcc.
|
|
660 |
masm.movl(result, input.asInt());
|
|
661 |
|
|
662 |
break;
|
|
663 |
case Long:
|
|
664 |
// Do not optimize with an XOR as this instruction may be between
|
|
665 |
// a CMP and a Jcc in which case the XOR will modify the condition
|
|
666 |
// flags and interfere with the Jcc.
|
|
667 |
if (input.asLong() == (int) input.asLong()) {
|
|
668 |
// Sign extended to long
|
|
669 |
masm.movslq(result, (int) input.asLong());
|
|
670 |
} else if ((input.asLong() & 0xFFFFFFFFL) == input.asLong()) {
|
|
671 |
// Zero extended to long
|
|
672 |
masm.movl(result, (int) input.asLong());
|
|
673 |
} else {
|
|
674 |
masm.movq(result, input.asLong());
|
|
675 |
}
|
|
676 |
break;
|
|
677 |
case Float:
|
|
678 |
// This is *not* the same as 'constant == 0.0f' in the case where constant is -0.0f
|
|
679 |
if (Float.floatToRawIntBits(input.asFloat()) == Float.floatToRawIntBits(0.0f)) {
|
|
680 |
masm.xorps(result, result);
|
|
681 |
} else {
|
|
682 |
masm.movflt(result, (AMD64Address) crb.asFloatConstRef(input));
|
|
683 |
}
|
|
684 |
break;
|
|
685 |
case Double:
|
|
686 |
// This is *not* the same as 'constant == 0.0d' in the case where constant is -0.0d
|
|
687 |
if (Double.doubleToRawLongBits(input.asDouble()) == Double.doubleToRawLongBits(0.0d)) {
|
|
688 |
masm.xorpd(result, result);
|
|
689 |
} else {
|
|
690 |
masm.movdbl(result, (AMD64Address) crb.asDoubleConstRef(input));
|
|
691 |
}
|
|
692 |
break;
|
|
693 |
case Object:
|
57537
|
694 |
assert moveKind != null : "a nun-null moveKind is required for loading an object constant";
|
43972
|
695 |
// Do not optimize with an XOR as this instruction may be between
|
|
696 |
// a CMP and a Jcc in which case the XOR will modify the condition
|
|
697 |
// flags and interfere with the Jcc.
|
|
698 |
if (input.isNull()) {
|
57537
|
699 |
if (moveKind == AMD64Kind.QWORD && crb.mustReplaceWithUncompressedNullRegister(input)) {
|
|
700 |
masm.movq(result, crb.uncompressedNullRegister);
|
50858
|
701 |
} else {
|
57537
|
702 |
// Upper bits will be zeroed so this also works for narrow oops
|
54084
|
703 |
masm.movslq(result, 0);
|
50858
|
704 |
}
|
43972
|
705 |
} else {
|
57537
|
706 |
if (crb.target.inlineObjects) {
|
|
707 |
crb.recordInlineDataInCode(input);
|
|
708 |
if (moveKind == AMD64Kind.DWORD) {
|
|
709 |
// Support for narrow oops
|
|
710 |
masm.movl(result, 0xDEADDEAD, true);
|
|
711 |
} else {
|
|
712 |
masm.movq(result, 0xDEADDEADDEADDEADL, true);
|
|
713 |
}
|
|
714 |
} else {
|
|
715 |
if (moveKind == AMD64Kind.DWORD) {
|
|
716 |
// Support for narrow oops
|
|
717 |
masm.movl(result, (AMD64Address) crb.recordDataReferenceInCode(input, 0));
|
|
718 |
} else {
|
|
719 |
masm.movq(result, (AMD64Address) crb.recordDataReferenceInCode(input, 0));
|
|
720 |
}
|
|
721 |
}
|
43972
|
722 |
}
|
|
723 |
break;
|
|
724 |
default:
|
|
725 |
throw GraalError.shouldNotReachHere();
|
|
726 |
}
|
|
727 |
}
|
|
728 |
|
46680
|
729 |
public static boolean canMoveConst2Stack(JavaConstant input) {
|
|
730 |
switch (input.getJavaKind().getStackKind()) {
|
|
731 |
case Int:
|
|
732 |
break;
|
|
733 |
case Long:
|
|
734 |
break;
|
|
735 |
case Float:
|
|
736 |
break;
|
|
737 |
case Double:
|
|
738 |
break;
|
|
739 |
case Object:
|
|
740 |
if (input.isNull()) {
|
|
741 |
return true;
|
|
742 |
} else {
|
|
743 |
return false;
|
|
744 |
}
|
|
745 |
default:
|
|
746 |
return false;
|
|
747 |
}
|
|
748 |
return true;
|
|
749 |
}
|
|
750 |
|
43972
|
751 |
public static void const2stack(CompilationResultBuilder crb, AMD64MacroAssembler masm, Value result, JavaConstant input) {
|
|
752 |
AMD64Address dest = (AMD64Address) crb.asAddress(result);
|
|
753 |
final long imm;
|
|
754 |
switch (input.getJavaKind().getStackKind()) {
|
|
755 |
case Int:
|
|
756 |
imm = input.asInt();
|
|
757 |
break;
|
|
758 |
case Long:
|
|
759 |
imm = input.asLong();
|
|
760 |
break;
|
|
761 |
case Float:
|
|
762 |
imm = floatToRawIntBits(input.asFloat());
|
|
763 |
break;
|
|
764 |
case Double:
|
|
765 |
imm = doubleToRawLongBits(input.asDouble());
|
|
766 |
break;
|
|
767 |
case Object:
|
|
768 |
if (input.isNull()) {
|
57537
|
769 |
if (crb.mustReplaceWithUncompressedNullRegister(input)) {
|
|
770 |
masm.movq(dest, crb.uncompressedNullRegister);
|
50858
|
771 |
return;
|
|
772 |
}
|
43972
|
773 |
imm = 0;
|
|
774 |
} else {
|
57537
|
775 |
throw GraalError.shouldNotReachHere("Non-null object constants must be in a register");
|
43972
|
776 |
}
|
|
777 |
break;
|
|
778 |
default:
|
|
779 |
throw GraalError.shouldNotReachHere();
|
|
780 |
}
|
|
781 |
|
|
782 |
switch ((AMD64Kind) result.getPlatformKind()) {
|
|
783 |
case BYTE:
|
|
784 |
assert NumUtil.isByte(imm) : "Is not in byte range: " + imm;
|
|
785 |
AMD64MIOp.MOVB.emit(masm, OperandSize.BYTE, dest, (int) imm);
|
|
786 |
break;
|
|
787 |
case WORD:
|
|
788 |
assert NumUtil.isShort(imm) : "Is not in short range: " + imm;
|
|
789 |
AMD64MIOp.MOV.emit(masm, OperandSize.WORD, dest, (int) imm);
|
|
790 |
break;
|
|
791 |
case DWORD:
|
|
792 |
case SINGLE:
|
|
793 |
assert NumUtil.isInt(imm) : "Is not in int range: " + imm;
|
|
794 |
masm.movl(dest, (int) imm);
|
|
795 |
break;
|
|
796 |
case QWORD:
|
|
797 |
case DOUBLE:
|
|
798 |
masm.movlong(dest, imm);
|
|
799 |
break;
|
|
800 |
default:
|
|
801 |
throw GraalError.shouldNotReachHere("Unknown result Kind: " + result.getPlatformKind());
|
|
802 |
}
|
|
803 |
}
|
47798
|
804 |
|
48861
|
805 |
public abstract static class PointerCompressionOp extends AMD64LIRInstruction {
|
47798
|
806 |
protected final LIRKindTool lirKindTool;
|
|
807 |
protected final CompressEncoding encoding;
|
|
808 |
protected final boolean nonNull;
|
|
809 |
|
|
810 |
@Def({REG, HINT}) private AllocatableValue result;
|
48861
|
811 |
@Use({REG, CONST}) private Value input;
|
49451
|
812 |
@Alive({REG, ILLEGAL, UNINITIALIZED}) private AllocatableValue baseRegister;
|
47798
|
813 |
|
48861
|
814 |
protected PointerCompressionOp(LIRInstructionClass<? extends PointerCompressionOp> type, AllocatableValue result, Value input,
|
|
815 |
AllocatableValue baseRegister, CompressEncoding encoding, boolean nonNull, LIRKindTool lirKindTool) {
|
|
816 |
|
47798
|
817 |
super(type);
|
|
818 |
this.result = result;
|
|
819 |
this.input = input;
|
|
820 |
this.baseRegister = baseRegister;
|
|
821 |
this.encoding = encoding;
|
|
822 |
this.nonNull = nonNull;
|
|
823 |
this.lirKindTool = lirKindTool;
|
|
824 |
}
|
|
825 |
|
49451
|
826 |
public static boolean hasBase(OptionValues options, CompressEncoding encoding) {
|
|
827 |
return GeneratePIC.getValue(options) || encoding.hasBase();
|
47798
|
828 |
}
|
|
829 |
|
48861
|
830 |
public final Value getInput() {
|
|
831 |
return input;
|
|
832 |
}
|
|
833 |
|
|
834 |
public final AllocatableValue getResult() {
|
|
835 |
return result;
|
47798
|
836 |
}
|
|
837 |
|
50858
|
838 |
protected final Register getResultRegister() {
|
|
839 |
return asRegister(result);
|
|
840 |
}
|
|
841 |
|
|
842 |
protected final Register getBaseRegister(CompilationResultBuilder crb) {
|
|
843 |
return hasBase(crb.getOptions(), encoding) ? asRegister(baseRegister) : Register.None;
|
47798
|
844 |
}
|
|
845 |
|
|
846 |
protected final int getShift() {
|
|
847 |
return encoding.getShift();
|
|
848 |
}
|
|
849 |
|
|
850 |
protected final void move(LIRKind kind, CompilationResultBuilder crb, AMD64MacroAssembler masm) {
|
|
851 |
AMD64Move.move((AMD64Kind) kind.getPlatformKind(), crb, masm, result, input);
|
|
852 |
}
|
|
853 |
}
|
|
854 |
|
48861
|
855 |
public static class CompressPointerOp extends PointerCompressionOp {
|
|
856 |
public static final LIRInstructionClass<CompressPointerOp> TYPE = LIRInstructionClass.create(CompressPointerOp.class);
|
47798
|
857 |
|
48861
|
858 |
public CompressPointerOp(AllocatableValue result, Value input, AllocatableValue baseRegister, CompressEncoding encoding, boolean nonNull, LIRKindTool lirKindTool) {
|
|
859 |
this(TYPE, result, input, baseRegister, encoding, nonNull, lirKindTool);
|
|
860 |
}
|
|
861 |
|
50858
|
862 |
private CompressPointerOp(LIRInstructionClass<? extends PointerCompressionOp> type, AllocatableValue result, Value input,
|
48861
|
863 |
AllocatableValue baseRegister, CompressEncoding encoding, boolean nonNull, LIRKindTool lirKindTool) {
|
|
864 |
|
|
865 |
super(type, result, input, baseRegister, encoding, nonNull, lirKindTool);
|
47798
|
866 |
}
|
|
867 |
|
|
868 |
@Override
|
|
869 |
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
|
|
870 |
move(lirKindTool.getObjectKind(), crb, masm);
|
|
871 |
|
50858
|
872 |
final Register resReg = getResultRegister();
|
|
873 |
final Register baseReg = getBaseRegister(crb);
|
|
874 |
if (!baseReg.equals(Register.None)) {
|
47798
|
875 |
if (!nonNull) {
|
|
876 |
masm.testq(resReg, resReg);
|
|
877 |
masm.cmovq(Equal, resReg, baseReg);
|
|
878 |
}
|
|
879 |
masm.subq(resReg, baseReg);
|
|
880 |
}
|
|
881 |
|
|
882 |
int shift = getShift();
|
|
883 |
if (shift != 0) {
|
|
884 |
masm.shrq(resReg, shift);
|
|
885 |
}
|
|
886 |
}
|
|
887 |
}
|
|
888 |
|
48861
|
889 |
public static class UncompressPointerOp extends PointerCompressionOp {
|
|
890 |
public static final LIRInstructionClass<UncompressPointerOp> TYPE = LIRInstructionClass.create(UncompressPointerOp.class);
|
47798
|
891 |
|
48861
|
892 |
public UncompressPointerOp(AllocatableValue result, Value input, AllocatableValue baseRegister, CompressEncoding encoding, boolean nonNull, LIRKindTool lirKindTool) {
|
|
893 |
this(TYPE, result, input, baseRegister, encoding, nonNull, lirKindTool);
|
|
894 |
}
|
|
895 |
|
50858
|
896 |
private UncompressPointerOp(LIRInstructionClass<? extends PointerCompressionOp> type, AllocatableValue result, Value input,
|
48861
|
897 |
AllocatableValue baseRegister, CompressEncoding encoding, boolean nonNull, LIRKindTool lirKindTool) {
|
|
898 |
super(type, result, input, baseRegister, encoding, nonNull, lirKindTool);
|
47798
|
899 |
}
|
|
900 |
|
|
901 |
@Override
|
|
902 |
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
|
50858
|
903 |
Register baseReg = getBaseRegister(crb);
|
|
904 |
if (nonNull && !baseReg.equals(Register.None) && getInput() instanceof RegisterValue) {
|
|
905 |
Register inputReg = ((RegisterValue) getInput()).getRegister();
|
|
906 |
if (!inputReg.equals(getResultRegister())) {
|
|
907 |
masm.leaq(getResultRegister(), new AMD64Address(baseReg, inputReg, AMD64Address.Scale.fromShift(getShift())));
|
|
908 |
return;
|
|
909 |
}
|
|
910 |
}
|
47798
|
911 |
move(lirKindTool.getNarrowOopKind(), crb, masm);
|
50858
|
912 |
emitUncompressCode(masm, getResultRegister(), getShift(), baseReg, nonNull);
|
49451
|
913 |
}
|
47798
|
914 |
|
49451
|
915 |
public static void emitUncompressCode(AMD64MacroAssembler masm, Register resReg, int shift, Register baseReg, boolean nonNull) {
|
50858
|
916 |
if (nonNull) {
|
|
917 |
if (!baseReg.equals(Register.None)) {
|
|
918 |
if (shift != 0) {
|
|
919 |
masm.leaq(resReg, new AMD64Address(baseReg, resReg, AMD64Address.Scale.fromShift(shift)));
|
|
920 |
} else {
|
|
921 |
masm.addq(resReg, baseReg);
|
|
922 |
}
|
|
923 |
} else if (shift != 0) {
|
|
924 |
masm.shlq(resReg, shift);
|
|
925 |
}
|
|
926 |
} else {
|
|
927 |
if (shift != 0) {
|
|
928 |
masm.shlq(resReg, shift);
|
47798
|
929 |
}
|
|
930 |
|
50858
|
931 |
if (!baseReg.equals(Register.None)) {
|
|
932 |
if (shift == 0) {
|
|
933 |
// if encoding.shift != 0, the flags are already set by the shlq
|
|
934 |
masm.testq(resReg, resReg);
|
|
935 |
}
|
47798
|
936 |
|
50858
|
937 |
Label done = new Label();
|
|
938 |
masm.jccb(Equal, done);
|
|
939 |
masm.addq(resReg, baseReg);
|
|
940 |
masm.bind(done);
|
|
941 |
}
|
47798
|
942 |
}
|
|
943 |
}
|
|
944 |
}
|
50858
|
945 |
|
|
946 |
private abstract static class ZeroNullConversionOp extends AMD64LIRInstruction {
|
|
947 |
@Def({REG, HINT}) protected AllocatableValue result;
|
|
948 |
@Use({REG}) protected AllocatableValue input;
|
|
949 |
|
|
950 |
protected ZeroNullConversionOp(LIRInstructionClass<? extends ZeroNullConversionOp> type, AllocatableValue result, AllocatableValue input) {
|
|
951 |
super(type);
|
|
952 |
this.result = result;
|
|
953 |
this.input = input;
|
|
954 |
}
|
|
955 |
|
|
956 |
@Override
|
|
957 |
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
|
57537
|
958 |
Register nullRegister = crb.uncompressedNullRegister;
|
50858
|
959 |
if (!nullRegister.equals(Register.None)) {
|
|
960 |
emitConversion(asRegister(result), asRegister(input), nullRegister, masm);
|
|
961 |
}
|
|
962 |
}
|
|
963 |
|
|
964 |
protected abstract void emitConversion(Register resultRegister, Register inputRegister, Register nullRegister, AMD64MacroAssembler masm);
|
|
965 |
}
|
|
966 |
|
|
967 |
public static class ConvertNullToZeroOp extends ZeroNullConversionOp {
|
|
968 |
public static final LIRInstructionClass<ConvertNullToZeroOp> TYPE = LIRInstructionClass.create(ConvertNullToZeroOp.class);
|
|
969 |
|
|
970 |
public ConvertNullToZeroOp(AllocatableValue result, AllocatableValue input) {
|
|
971 |
super(TYPE, result, input);
|
|
972 |
}
|
|
973 |
|
|
974 |
@Override
|
|
975 |
protected final void emitConversion(Register resultRegister, Register inputRegister, Register nullRegister, AMD64MacroAssembler masm) {
|
|
976 |
if (inputRegister.equals(resultRegister)) {
|
|
977 |
masm.subq(inputRegister, nullRegister);
|
|
978 |
Label done = new Label();
|
|
979 |
masm.jccb(Equal, done);
|
|
980 |
masm.addq(inputRegister, nullRegister);
|
|
981 |
masm.bind(done);
|
|
982 |
} else {
|
|
983 |
masm.subq(resultRegister, resultRegister);
|
|
984 |
masm.cmpq(inputRegister, nullRegister);
|
|
985 |
masm.cmovq(NotEqual, resultRegister, inputRegister);
|
|
986 |
}
|
|
987 |
}
|
|
988 |
}
|
|
989 |
|
|
990 |
public static class ConvertZeroToNullOp extends ZeroNullConversionOp {
|
|
991 |
public static final LIRInstructionClass<ConvertZeroToNullOp> TYPE = LIRInstructionClass.create(ConvertZeroToNullOp.class);
|
|
992 |
|
|
993 |
public ConvertZeroToNullOp(AllocatableValue result, AllocatableValue input) {
|
|
994 |
super(TYPE, result, input);
|
|
995 |
}
|
|
996 |
|
|
997 |
@Override
|
|
998 |
protected final void emitConversion(Register resultRegister, Register inputRegister, Register nullRegister, AMD64MacroAssembler masm) {
|
|
999 |
if (!inputRegister.equals(resultRegister)) {
|
|
1000 |
masm.movq(resultRegister, inputRegister);
|
|
1001 |
}
|
|
1002 |
masm.testq(inputRegister, inputRegister);
|
|
1003 |
masm.cmovq(Equal, resultRegister, nullRegister);
|
|
1004 |
}
|
|
1005 |
}
|
43972
|
1006 |
}
|