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/*
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* Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2019, Arm Limited and affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*/
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package org.graalvm.compiler.lir.aarch64;
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import static jdk.vm.ci.aarch64.AArch64.zr;
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import static jdk.vm.ci.code.ValueUtil.asRegister;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
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import org.graalvm.compiler.asm.Label;
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import org.graalvm.compiler.asm.aarch64.AArch64Address;
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import org.graalvm.compiler.asm.aarch64.AArch64Assembler;
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import org.graalvm.compiler.asm.aarch64.AArch64Assembler.ConditionFlag;
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import org.graalvm.compiler.asm.aarch64.AArch64MacroAssembler;
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import org.graalvm.compiler.lir.LIRInstructionClass;
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import org.graalvm.compiler.lir.Opcode;
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import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
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import jdk.vm.ci.code.CodeUtil;
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import jdk.vm.ci.code.Register;
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import jdk.vm.ci.meta.Value;
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/**
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* Zero a chunk of memory on AArch64.
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*/
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@Opcode("ZERO_MEMORY")
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public final class AArch64ZeroMemoryOp extends AArch64LIRInstruction {
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public static final LIRInstructionClass<AArch64ZeroMemoryOp> TYPE = LIRInstructionClass.create(AArch64ZeroMemoryOp.class);
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@Use({REG}) protected Value addressValue;
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@Use({REG}) protected Value lengthValue;
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@Temp({REG}) protected Value addressValueTemp;
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@Temp({REG}) protected Value lengthValueTemp;
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private final boolean isAligned;
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private final boolean useDcZva;
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private final int zvaLength;
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/**
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* Constructor of AArch64ZeroMemoryOp.
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*
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* @param address starting address of the memory chunk to be zeroed.
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* @param length size of the memory chunk to be zeroed, in bytes.
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* @param isAligned whether both address and size are aligned to 8 bytes.
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* @param useDcZva is DC ZVA instruction is able to use.
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* @param zvaLength the ZVA length info of current AArch64 CPU, negative value indicates length
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* is unknown at compile time.
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*/
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public AArch64ZeroMemoryOp(Value address, Value length, boolean isAligned, boolean useDcZva, int zvaLength) {
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super(TYPE);
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this.addressValue = address;
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this.lengthValue = length;
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this.addressValueTemp = address;
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this.lengthValueTemp = length;
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this.useDcZva = useDcZva;
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this.zvaLength = zvaLength;
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this.isAligned = isAligned;
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}
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@Override
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protected void emitCode(CompilationResultBuilder crb, AArch64MacroAssembler masm) {
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Register base = asRegister(addressValue);
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Register size = asRegister(lengthValue);
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try (AArch64MacroAssembler.ScratchRegister scratchRegister = masm.getScratchRegister()) {
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Register alignmentBits = scratchRegister.getRegister();
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Label tail = new Label();
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Label done = new Label();
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// Jump to DONE if size is zero.
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masm.cbz(64, size, done);
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if (!isAligned) {
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Label baseAlignedTo2Bytes = new Label();
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Label baseAlignedTo4Bytes = new Label();
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Label baseAlignedTo8Bytes = new Label();
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// Jump to per-byte zeroing loop if the zeroing size is less than 8
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masm.cmp(64, size, 8);
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masm.branchConditionally(ConditionFlag.LT, tail);
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// Make base 8-byte aligned
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masm.neg(64, alignmentBits, base);
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masm.and(64, alignmentBits, alignmentBits, 7);
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masm.tbz(alignmentBits, 0, baseAlignedTo2Bytes);
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masm.sub(64, size, size, 1);
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masm.str(8, zr, AArch64Address.createPostIndexedImmediateAddress(base, 1));
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masm.bind(baseAlignedTo2Bytes);
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masm.tbz(alignmentBits, 1, baseAlignedTo4Bytes);
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masm.sub(64, size, size, 2);
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masm.str(16, zr, AArch64Address.createPostIndexedImmediateAddress(base, 2));
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masm.bind(baseAlignedTo4Bytes);
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masm.tbz(alignmentBits, 2, baseAlignedTo8Bytes);
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masm.sub(64, size, size, 4);
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masm.str(32, zr, AArch64Address.createPostIndexedImmediateAddress(base, 4));
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masm.bind(baseAlignedTo8Bytes);
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// At this point base is 8-byte aligned.
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}
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if (useDcZva && zvaLength > 0) {
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// From ARMv8-A architecture reference manual D12.2.35 Data Cache Zero ID register:
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// A valid ZVA length should be a power-of-2 value in [4, 2048]
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assert (CodeUtil.isPowerOf2(zvaLength) && 4 <= zvaLength && zvaLength <= 2048);
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Label preCheck = new Label();
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Label preLoop = new Label();
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Label mainCheck = new Label();
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Label mainLoop = new Label();
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Label postCheck = new Label();
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Label postLoop = new Label();
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masm.neg(64, alignmentBits, base);
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masm.and(64, alignmentBits, alignmentBits, zvaLength - 1);
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// Is size less than number of bytes to be pre-zeroed? Jump to post check if so.
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masm.cmp(64, size, alignmentBits);
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masm.branchConditionally(AArch64Assembler.ConditionFlag.LE, postCheck);
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masm.sub(64, size, size, alignmentBits);
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// Pre loop: align base according to the supported bulk zeroing stride.
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masm.jmp(preCheck);
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masm.align(crb.target.wordSize * 2);
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masm.bind(preLoop);
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masm.str(64, zr, AArch64Address.createPostIndexedImmediateAddress(base, 8));
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masm.bind(preCheck);
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masm.subs(64, alignmentBits, alignmentBits, 8);
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masm.branchConditionally(AArch64Assembler.ConditionFlag.GE, preLoop);
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// Main loop: bulk zeroing
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masm.jmp(mainCheck);
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masm.align(crb.target.wordSize * 2);
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masm.bind(mainLoop);
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masm.dc(AArch64Assembler.DataCacheOperationType.ZVA, base);
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masm.add(64, base, base, zvaLength);
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masm.bind(mainCheck);
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masm.subs(64, size, size, zvaLength);
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masm.branchConditionally(AArch64Assembler.ConditionFlag.GE, mainLoop);
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masm.add(64, size, size, zvaLength);
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// Post loop: handle bytes after the main loop
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masm.jmp(postCheck);
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masm.align(crb.target.wordSize * 2);
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masm.bind(postLoop);
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masm.str(64, zr, AArch64Address.createPostIndexedImmediateAddress(base, 8));
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masm.bind(postCheck);
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masm.subs(64, size, size, 8);
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masm.branchConditionally(AArch64Assembler.ConditionFlag.GE, postLoop);
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if (!isAligned) {
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// Restore size for tail zeroing
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masm.add(64, size, size, 8);
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}
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} else {
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Label mainCheck = new Label();
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Label mainLoop = new Label();
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if (!isAligned) {
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// After aligning base, we may have size less than 8. Need to check again.
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masm.cmp(64, size, 8);
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masm.branchConditionally(ConditionFlag.LT, tail);
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}
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masm.tbz(base, 3, mainCheck);
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masm.sub(64, size, size, 8);
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masm.str(64, zr, AArch64Address.createPostIndexedImmediateAddress(base, 8));
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masm.jmp(mainCheck);
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// The STP loop that zeros 16 bytes in each iteration.
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masm.align(crb.target.wordSize * 2);
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masm.bind(mainLoop);
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masm.stp(64, zr, zr, AArch64Address.createPostIndexedImmediateAddress(base, 2));
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masm.bind(mainCheck);
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masm.subs(64, size, size, 16);
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masm.branchConditionally(AArch64Assembler.ConditionFlag.GE, mainLoop);
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// We may need to zero the tail 8 bytes of the memory chunk.
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masm.add(64, size, size, 16);
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masm.tbz(size, 3, tail);
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masm.str(64, zr, AArch64Address.createPostIndexedImmediateAddress(base, 8));
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if (!isAligned) {
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// Adjust size for tail zeroing
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masm.sub(64, size, size, 8);
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}
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}
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masm.bind(tail);
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if (!isAligned) {
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Label perByteZeroingLoop = new Label();
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masm.cbz(64, size, done);
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// We have to ensure size > 0 when entering the following loop
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masm.align(crb.target.wordSize * 2);
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masm.bind(perByteZeroingLoop);
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masm.str(8, zr, AArch64Address.createPostIndexedImmediateAddress(base, 1));
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masm.subs(64, size, size, 1);
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masm.branchConditionally(AArch64Assembler.ConditionFlag.NE, perByteZeroingLoop);
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}
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masm.bind(done);
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}
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}
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}
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