/*

 * Copyright (c) 2013, 2019, Oracle and/or its affiliates. All rights reserved.

 * Copyright (c) 2018, Red Hat Inc. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 */

package org.graalvm.compiler.asm.aarch64;

import static jdk.vm.ci.aarch64.AArch64.CPU;

import static jdk.vm.ci.aarch64.AArch64.SIMD;

import static jdk.vm.ci.aarch64.AArch64.cpuRegisters;

import static jdk.vm.ci.aarch64.AArch64.r0;

import static jdk.vm.ci.aarch64.AArch64.sp;

import static jdk.vm.ci.aarch64.AArch64.zr;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADD;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADDS;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADDV;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADRP;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.AND;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ANDS;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ASRV;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BFM;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BIC;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BICS;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BLR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.BRK;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CAS;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CCMP;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CLREX;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CLS;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CLZ;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CNT;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CSEL;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CSINC;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.CSNEG;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.DC;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.DMB;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.EON;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.EOR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.EXTR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FABS;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FADD;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCCMP;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCMP;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCMPZERO;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCSEL;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTDS;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTSD;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTZS;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FDIV;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FMADD;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FMOV;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FMSUB;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FMUL;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FNEG;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FRINTM;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FRINTN;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FRINTP;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FRINTZ;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FSQRT;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.FSUB;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.HINT;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.HLT;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.LDADD;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.LDAR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.LDAXR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.LDP;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.LDR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.LDRS;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.LDXR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.LSLV;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.LSRV;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.MADD;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.MOVK;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.MOVN;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.MOVZ;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.MRS;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.MSUB;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ORN;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ORR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.RBIT;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.RET;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.REVW;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.REVX;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.RORV;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.SBFM;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.SCVTF;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.SDIV;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.STLR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.STLXR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.STP;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.STR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.STXR;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.SUB;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.SUBS;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.SWP;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.TBNZ;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.TBZ;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.UBFM;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.UDIV;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.UMOV;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.InstructionType.FP32;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.InstructionType.FP64;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.InstructionType.General32;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.InstructionType.General64;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.InstructionType.floatFromSize;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.InstructionType.generalFromSize;

import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.InstructionType.simdFromSize;

import java.util.Arrays;

import org.graalvm.compiler.asm.Assembler;

import org.graalvm.compiler.asm.aarch64.AArch64Address.AddressingMode;

import org.graalvm.compiler.core.common.NumUtil;

import org.graalvm.compiler.debug.GraalError;

import jdk.vm.ci.aarch64.AArch64;

import jdk.vm.ci.aarch64.AArch64.CPUFeature;

import jdk.vm.ci.aarch64.AArch64.Flag;

import jdk.vm.ci.code.Register;

import jdk.vm.ci.code.TargetDescription;

public abstract class AArch64Assembler extends Assembler {

    public static class LogicalImmediateTable {

        private static final Immediate[] IMMEDIATE_TABLE = buildImmediateTable();

        private static final int ImmediateOffset = 10;

        private static final int ImmediateRotateOffset = 16;

        private static final int ImmediateSizeOffset = 22;

        /**

         * Specifies whether immediate can be represented in all cases (YES), as a 64bit instruction

         * (SIXTY_FOUR_BIT_ONLY) or not at all (NO).

         */

        enum Representable {

            YES,

            SIXTY_FOUR_BIT_ONLY,

            NO

        }

        /**

         * Tests whether an immediate can be encoded for logical instructions.

         *

         * @param is64bit if true immediate is considered a 64-bit pattern. If false we may use a

         *            64-bit instruction to load the 32-bit pattern into a register.

         * @return enum specifying whether immediate can be used for 32- and 64-bit logical

         *         instructions ({@code #Representable.YES}), for 64-bit instructions only (

         *         {@link Representable#SIXTY_FOUR_BIT_ONLY}) or not at all (

         *         {@link Representable#NO}).

         */

        public static Representable isRepresentable(boolean is64bit, long immediate) {

            int pos = getLogicalImmTablePos(is64bit, immediate);

            if (pos < 0) {

                // if 32bit instruction we can try again as 64bit immediate which may succeed.

                // i.e. 0xffffffff fails as a 32bit immediate but works as 64bit one.

                if (!is64bit) {

                    assert NumUtil.isUnsignedNbit(32, immediate);

                    pos = getLogicalImmTablePos(true, immediate);

                    return pos >= 0 ? Representable.SIXTY_FOUR_BIT_ONLY : Representable.NO;

                }

                return Representable.NO;

            }

            Immediate imm = IMMEDIATE_TABLE[pos];

            return imm.only64bit() ? Representable.SIXTY_FOUR_BIT_ONLY : Representable.YES;

        }

        public static Representable isRepresentable(int immediate) {

            return isRepresentable(false, immediate & 0xFFFF_FFFFL);

        }

        public static int getLogicalImmEncoding(boolean is64bit, long value) {

            int pos = getLogicalImmTablePos(is64bit, value);

            assert pos >= 0 : "Value cannot be represented as logical immediate: " + value + ", is64bit=" + is64bit;

            Immediate imm = IMMEDIATE_TABLE[pos];

            assert is64bit || !imm.only64bit() : "Immediate can only be represented for 64bit, but 32bit instruction specified";

            return IMMEDIATE_TABLE[pos].encoding;

        }

        /**

         * @param is64bit if true also allow 64-bit only encodings to be returned.

         * @return If positive the return value is the position into the IMMEDIATE_TABLE for the

         *         given immediate, if negative the immediate cannot be encoded.

         */

        private static int getLogicalImmTablePos(boolean is64bit, long value) {

            Immediate imm;

            if (!is64bit) {

                // 32bit instructions can only have 32bit immediates.

                if (!NumUtil.isUnsignedNbit(32, value)) {

                    return -1;

                }

                // If we have a 32bit instruction (and therefore immediate) we have to duplicate it

                // across 64bit to find it in the table.

                imm = new Immediate(value << 32 | value);

            } else {

                imm = new Immediate(value);

            }

            int pos = Arrays.binarySearch(IMMEDIATE_TABLE, imm);

            if (pos < 0) {

                return -1;

            }

            if (!is64bit && IMMEDIATE_TABLE[pos].only64bit()) {

                return -1;

            }

            return pos;

        }

        /**

         * To quote 5.4.2: [..] an immediate is a 32 or 64 bit pattern viewed as a vector of

         * identical elements of size e = 2, 4, 8, 16, 32 or (in the case of bimm64) 64 bits. Each

         * element contains the same sub-pattern: a single run of 1 to e-1 non-zero bits, rotated by

         * 0 to e-1 bits. It is encoded in the following: 10-16: rotation amount (6bit) starting

         * from 1s in the LSB (i.e. 0111->1011->1101->1110) 16-22: This stores a combination of the

         * number of set bits and the pattern size. The pattern size is encoded as follows (x is

         * used to store the number of 1 bits - 1) e pattern 2 1111xx 4 1110xx 8 110xxx 16 10xxxx 32

         * 0xxxxx 64 xxxxxx 22: if set we have an instruction with 64bit pattern?

         */

        private static final class Immediate implements Comparable<Immediate> {

            public final long imm;

            public final int encoding;

            Immediate(long imm, boolean is64, int s, int r) {

                this.imm = imm;

                this.encoding = computeEncoding(is64, s, r);

            }

            // Used to be able to binary search for an immediate in the table.

            Immediate(long imm) {

                this(imm, false, 0, 0);

            }

            /**

             * Returns true if this pattern is only representable as 64bit.

             */

            public boolean only64bit() {

                return (encoding & (1 << ImmediateSizeOffset)) != 0;

            }

            private static int computeEncoding(boolean is64, int s, int r) {

                int sf = is64 ? 1 : 0;

                return sf << ImmediateSizeOffset | r << ImmediateRotateOffset | s << ImmediateOffset;

            }

            @Override

            public int compareTo(Immediate o) {

                return Long.compare(imm, o.imm);

            }

        }

        private static Immediate[] buildImmediateTable() {

            final int nrImmediates = 5334;

            final Immediate[] table = new Immediate[nrImmediates];

            int nrImms = 0;

            for (int logE = 1; logE <= 6; logE++) {

                int e = 1 << logE;

                long mask = NumUtil.getNbitNumberLong(e);

                for (int nrOnes = 1; nrOnes < e; nrOnes++) {

                    long val = (1L << nrOnes) - 1;

                    // r specifies how much we rotate the value

                    for (int r = 0; r < e; r++) {

                        long immediate = (val >>> r | val << (e - r)) & mask;

                        // Duplicate pattern to fill whole 64bit range.

                        switch (logE) {

                            case 1:

                                immediate |= immediate << 2;

                                immediate |= immediate << 4;

                                immediate |= immediate << 8;

                                immediate |= immediate << 16;

                                immediate |= immediate << 32;

                                break;

                            case 2:

                                immediate |= immediate << 4;

                                immediate |= immediate << 8;

                                immediate |= immediate << 16;

                                immediate |= immediate << 32;

                                break;

                            case 3:

                                immediate |= immediate << 8;

                                immediate |= immediate << 16;

                                immediate |= immediate << 32;

                                break;

                            case 4:

                                immediate |= immediate << 16;

                                immediate |= immediate << 32;

                                break;

                            case 5:

                                immediate |= immediate << 32;

                                break;

                        }

                        // 5 - logE can underflow to -1, but we shift this bogus result

                        // out of the masked area.

                        int sizeEncoding = (1 << (5 - logE)) - 1;

                        int s = ((sizeEncoding << (logE + 1)) & 0x3f) | (nrOnes - 1);

                        table[nrImms++] = new Immediate(immediate, /* is64bit */e == 64, s, r);

                    }

                }

            }

            Arrays.sort(table);

            assert nrImms == nrImmediates : nrImms + " instead of " + nrImmediates + " in table.";

            assert checkDuplicates(table) : "Duplicate values in table.";

            return table;

        }

        private static boolean checkDuplicates(Immediate[] table) {

            for (int i = 0; i < table.length - 1; i++) {

                if (table[i].imm >= table[i + 1].imm) {

                    return false;

                }

            }

            return true;

        }

    }

    private static final int RdOffset = 0;

    private static final int Rs1Offset = 5;

    private static final int Rs2Offset = 16;

    private static final int Rs3Offset = 10;

    private static final int RtOffset = 0;

    private static final int RnOffset = 5;

    private static final int Rt2Offset = 10;

    /* Helper functions */

    private static int rd(Register reg) {

        return reg.encoding << RdOffset;

    }

    private static int rs1(Register reg) {

        return reg.encoding << Rs1Offset;

    }

    private static int rs2(Register reg) {

        return reg.encoding << Rs2Offset;

    }

    private static int rs3(Register reg) {

        return reg.encoding << Rs3Offset;

    }

    private static int rt(Register reg) {

        return reg.encoding << RtOffset;

    }

    private static int rt2(Register reg) {

        return reg.encoding << Rt2Offset;

    }

    private static int rn(Register reg) {

        return reg.encoding << RnOffset;

    }

    private static int maskField(int sizeInBits, int n) {

        assert NumUtil.isSignedNbit(sizeInBits, n);

        return n & NumUtil.getNbitNumberInt(sizeInBits);

    }

    /**

     * Enumeration of all different lane types of SIMD register.

     *

     * Byte(B):8b/lane; HalfWord(H):16b/lane; Word(S):32b/lane; DoubleWord(D):64b/lane.

     */

    public enum SIMDElementSize {

        Byte(0, 8),

        HalfWord(1, 16),

        Word(2, 32),

        DoubleWord(3, 64);

        public final int encoding;

        public final int nbits;

        SIMDElementSize(int encoding, int nbits) {

            this.encoding = encoding;

            this.nbits = nbits;

        }

    }

    /**

     * Enumeration of all different instruction kinds: General32/64 are the general instructions

     * (integer, branch, etc.), for 32-, respectively 64-bit operands. FP32/64 is the encoding for

     * the 32/64bit float operations. SIMDByte/HalfWord/Word/DoubleWord is the encoding for SIMD

     * instructions

     */

    protected enum InstructionType {

        General32(0b00 << 30, 32, true),

        General64(0b10 << 30, 64, true),

        FP32(0x00000000, 32, false),

        FP64(0x00400000, 64, false),

        SIMDByte(0x01, 8, false),

        SIMDHalfWord(0x02, 16, false),

        SIMDWord(0x04, 32, false),

        SIMDDoubleWord(0x08, 64, false);

        public final int encoding;

        public final int width;

        public final boolean isGeneral;

        InstructionType(int encoding, int width, boolean isGeneral) {

            this.encoding = encoding;

            this.width = width;

            this.isGeneral = isGeneral;

        }

        public static InstructionType generalFromSize(int size) {

            assert size == 32 || size == 64;

            return size == 32 ? General32 : General64;

        }

        public static InstructionType floatFromSize(int size) {

            assert size == 32 || size == 64;

            return size == 32 ? FP32 : FP64;

        }

        public static InstructionType simdFromSize(int size) {

            switch (size) {

                case 8:

                    return SIMDByte;

                case 16:

                    return SIMDHalfWord;

                case 32:

                    return SIMDWord;

                case 64:

                    return SIMDDoubleWord;

                default:

                    throw GraalError.shouldNotReachHere();

            }

        }

    }

    private static final int ImmediateOffset = 10;

    private static final int ImmediateRotateOffset = 16;

    private static final int ImmediateSizeOffset = 22;

    private static final int ExtendTypeOffset = 13;

    private static final int AddSubImmOp = 0x11000000;

    private static final int AddSubShift12 = 0b01 << 22;

    private static final int AddSubSetFlag = 0x20000000;

    private static final int LogicalImmOp = 0x12000000;

    private static final int MoveWideImmOp = 0x12800000;

    private static final int MoveWideImmOffset = 5;

    private static final int MoveWideShiftOffset = 21;

    private static final int BitfieldImmOp = 0x13000000;

    private static final int AddSubShiftedOp = 0x0B000000;

    private static final int ShiftTypeOffset = 22;

    private static final int AddSubExtendedOp = 0x0B200000;

    private static final int MulOp = 0x1B000000;

    private static final int DataProcessing1SourceOp = 0x5AC00000;

    private static final int DataProcessing2SourceOp = 0x1AC00000;

    private static final int Fp1SourceOp = 0x1E204000;

    private static final int Fp2SourceOp = 0x1E200800;

    private static final int Fp3SourceOp = 0x1F000000;

    private static final int FpConvertOp = 0x1E200000;

    private static final int FpImmOp = 0x1E201000;

    private static final int FpImmOffset = 13;

    private static final int FpCmpOp = 0x1E202000;

    private static final int FpCmpeOp = 0x1E202010;

    private static final int PcRelImmHiOffset = 5;

    private static final int PcRelImmLoOffset = 29;

    private static final int PcRelImmOp = 0x10000000;

    private static final int UnconditionalBranchImmOp = 0x14000000;

    private static final int UnconditionalBranchRegOp = 0xD6000000;

    private static final int CompareBranchOp = 0x34000000;

    private static final int ConditionalBranchImmOffset = 5;

    private static final int ConditionalSelectOp = 0x1A800000;

    private static final int ConditionalConditionOffset = 12;

    private static final int LoadStoreScaledOp = 0b111_0_01_00 << 22;

    private static final int LoadStoreUnscaledOp = 0b111_0_00_00 << 22;

    private static final int LoadStoreRegisterOp = 0b111_0_00_00_1 << 21 | 0b10 << 10;

    private static final int LoadLiteralOp = 0x18000000;

    private static final int LoadStorePostIndexedOp = 0b111_0_00_00_0 << 21 | 0b01 << 10;

    private static final int LoadStorePreIndexedOp = 0b111_0_00_00_0 << 21 | 0b11 << 10;

    private static final int LoadStoreUnscaledImmOffset = 12;

    private static final int LoadStoreScaledImmOffset = 10;

    private static final int LoadStoreScaledRegOffset = 12;

    private static final int LoadStoreIndexedImmOffset = 12;

    private static final int LoadStoreTransferSizeOffset = 30;

    private static final int LoadStoreFpFlagOffset = 26;

    private static final int LoadLiteralImmeOffset = 5;