/*

 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#ifndef SHARE_OPTO_MACHNODE_HPP

#define SHARE_OPTO_MACHNODE_HPP

#include "opto/callnode.hpp"

#include "opto/matcher.hpp"

#include "opto/multnode.hpp"

#include "opto/node.hpp"

#include "opto/regmask.hpp"

class BiasedLockingCounters;

class BufferBlob;

class CodeBuffer;

class JVMState;

class MachCallDynamicJavaNode;

class MachCallJavaNode;

class MachCallLeafNode;

class MachCallNode;

class MachCallRuntimeNode;

class MachCallStaticJavaNode;

class MachEpilogNode;

class MachIfNode;

class MachNullCheckNode;

class MachOper;

class MachProjNode;

class MachPrologNode;

class MachReturnNode;

class MachSafePointNode;

class MachSpillCopyNode;

class Matcher;

class PhaseRegAlloc;

class RegMask;

class RTMLockingCounters;

class State;

//---------------------------MachOper------------------------------------------

class MachOper : public ResourceObj {

public:

  // Allocate right next to the MachNodes in the same arena

  void *operator new(size_t x) throw() {

    Compile* C = Compile::current();

    return C->node_arena()->Amalloc_D(x);

  }

  // Opcode

  virtual uint opcode() const = 0;

  // Number of input edges.

  // Generally at least 1

  virtual uint num_edges() const { return 1; }

  // Array of Register masks

  virtual const RegMask *in_RegMask(int index) const;

  // Methods to output the encoding of the operand

  // Negate conditional branches.  Error for non-branch Nodes

  virtual void negate();

  // Return the value requested

  // result register lookup, corresponding to int_format

  virtual int  reg(PhaseRegAlloc *ra_, const Node *node)   const;

  // input register lookup, corresponding to ext_format

  virtual int  reg(PhaseRegAlloc *ra_, const Node *node, int idx)   const;

  // helpers for MacroAssembler generation from ADLC

  Register  as_Register(PhaseRegAlloc *ra_, const Node *node)   const {

    return ::as_Register(reg(ra_, node));

  }

  Register  as_Register(PhaseRegAlloc *ra_, const Node *node, int idx)   const {

    return ::as_Register(reg(ra_, node, idx));

  }

  FloatRegister  as_FloatRegister(PhaseRegAlloc *ra_, const Node *node)   const {

    return ::as_FloatRegister(reg(ra_, node));

  }

  FloatRegister  as_FloatRegister(PhaseRegAlloc *ra_, const Node *node, int idx)   const {

    return ::as_FloatRegister(reg(ra_, node, idx));

  }

#if defined(IA32) || defined(AMD64)

  XMMRegister  as_XMMRegister(PhaseRegAlloc *ra_, const Node *node)   const {

    return ::as_XMMRegister(reg(ra_, node));

  }

  XMMRegister  as_XMMRegister(PhaseRegAlloc *ra_, const Node *node, int idx)   const {

    return ::as_XMMRegister(reg(ra_, node, idx));

  }

#endif

  // CondRegister reg converter

#if defined(PPC64)

  ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node) const {

    return ::as_ConditionRegister(reg(ra_, node));

  }

  ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {

    return ::as_ConditionRegister(reg(ra_, node, idx));

  }

  VectorRegister as_VectorRegister(PhaseRegAlloc *ra_, const Node *node) const {

    return ::as_VectorRegister(reg(ra_, node));

  }

  VectorRegister as_VectorRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {

    return ::as_VectorRegister(reg(ra_, node, idx));

  }

  VectorSRegister as_VectorSRegister(PhaseRegAlloc *ra_, const Node *node) const {

    return ::as_VectorSRegister(reg(ra_, node));

  }

  VectorSRegister as_VectorSRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {

    return ::as_VectorSRegister(reg(ra_, node, idx));

  }

#endif

  virtual intptr_t  constant() const;

  virtual relocInfo::relocType constant_reloc() const;

  virtual jdouble constantD() const;

  virtual jfloat  constantF() const;

  virtual jlong   constantL() const;

  virtual TypeOopPtr *oop() const;

  virtual int  ccode() const;

  // A zero, default, indicates this value is not needed.

  // May need to lookup the base register, as done in int_ and ext_format

  virtual int  base (PhaseRegAlloc *ra_, const Node *node, int idx) const;

  virtual int  index(PhaseRegAlloc *ra_, const Node *node, int idx) const;

  virtual int  scale() const;

  // Parameters needed to support MEMORY_INTERFACE access to stackSlot

  virtual int  disp (PhaseRegAlloc *ra_, const Node *node, int idx) const;

  // Check for PC-Relative displacement

  virtual relocInfo::relocType disp_reloc() const;

  virtual int  constant_disp() const;   // usu. 0, may return Type::OffsetBot

  virtual int  base_position()  const;  // base edge position, or -1

  virtual int  index_position() const;  // index edge position, or -1

  // Access the TypeKlassPtr of operands with a base==RegI and disp==RegP

  // Only returns non-null value for i486.ad's indOffset32X

  virtual const TypePtr *disp_as_type() const { return NULL; }

  // Return the label

  virtual Label *label() const;

  // Return the method's address

  virtual intptr_t  method() const;

  // Hash and compare over operands are currently identical

  virtual uint  hash() const;

  virtual bool  cmp( const MachOper &oper ) const;

  // Virtual clone, since I do not know how big the MachOper is.

  virtual MachOper *clone() const = 0;

  // Return ideal Type from simple operands.  Fail for complex operands.

  virtual const Type *type() const;

  // Set an integer offset if we have one, or error otherwise

  virtual void set_con( jint c0 ) { ShouldNotReachHere();  }

#ifndef PRODUCT

  // Return name of operand

  virtual const char    *Name() const { return "???";}

  // Methods to output the text version of the operand

  virtual void int_format(PhaseRegAlloc *,const MachNode *node, outputStream *st) const = 0;

  virtual void ext_format(PhaseRegAlloc *,const MachNode *node,int idx, outputStream *st) const=0;

  virtual void dump_spec(outputStream *st) const; // Print per-operand info

  // Check whether o is a valid oper.

  static bool notAnOper(const MachOper *o) {

    if (o == NULL)                   return true;

    if (((intptr_t)o & 1) != 0)      return true;

    if (*(address*)o == badAddress)  return true;  // kill by Node::destruct

    return false;

  }

#endif // !PRODUCT

};

//------------------------------MachNode---------------------------------------

// Base type for all machine specific nodes.  All node classes generated by the

// ADLC inherit from this class.

class MachNode : public Node {

public:

  MachNode() : Node((uint)0), _barrier(0), _num_opnds(0), _opnds(NULL) {

    init_class_id(Class_Mach);

  }

  // Required boilerplate

  virtual uint size_of() const { return sizeof(MachNode); }

  virtual int  Opcode() const;          // Always equal to MachNode

  virtual uint rule() const = 0;        // Machine-specific opcode

  // Number of inputs which come before the first operand.

  // Generally at least 1, to skip the Control input

  virtual uint oper_input_base() const { return 1; }

  // Position of constant base node in node's inputs. -1 if

  // no constant base node input.

  virtual uint mach_constant_base_node_input() const { return (uint)-1; }

  uint8_t barrier_data() const { return _barrier; }

  void set_barrier_data(uint data) { _barrier = data; }

  // Copy inputs and operands to new node of instruction.

  // Called from cisc_version() and short_branch_version().

  // !!!! The method's body is defined in ad_<arch>.cpp file.

  void fill_new_machnode(MachNode *n) const;

  // Return an equivalent instruction using memory for cisc_operand position

  virtual MachNode *cisc_version(int offset);

  // Modify this instruction's register mask to use stack version for cisc_operand

  virtual void use_cisc_RegMask();

  // Support for short branches

  bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; }

  // Avoid back to back some instructions on some CPUs.

  enum AvoidBackToBackFlag { AVOID_NONE = 0,

                             AVOID_BEFORE = Flag_avoid_back_to_back_before,

                             AVOID_AFTER = Flag_avoid_back_to_back_after,

                             AVOID_BEFORE_AND_AFTER = AVOID_BEFORE | AVOID_AFTER };

  bool avoid_back_to_back(AvoidBackToBackFlag flag_value) const {

    return (flags() & flag_value) == flag_value;

  }

  // instruction implemented with a call

  bool has_call() const { return (flags() & Flag_has_call) != 0; }

  // First index in _in[] corresponding to operand, or -1 if there is none

  int  operand_index(uint operand) const;

  int  operand_index(const MachOper *oper) const;

  // Register class input is expected in

  virtual const RegMask &in_RegMask(uint) const;

  // cisc-spillable instructions redefine for use by in_RegMask

  virtual const RegMask *cisc_RegMask() const { return NULL; }

  // If this instruction is a 2-address instruction, then return the

  // index of the input which must match the output.  Not nessecary

  // for instructions which bind the input and output register to the

  // same singleton regiser (e.g., Intel IDIV which binds AX to be

  // both an input and an output).  It is nessecary when the input and

  // output have choices - but they must use the same choice.

  virtual uint two_adr( ) const { return 0; }

  // The GC might require some barrier metadata for machine code emission.

  uint8_t _barrier;

  // Array of complex operand pointers.  Each corresponds to zero or

  // more leafs.  Must be set by MachNode constructor to point to an

  // internal array of MachOpers.  The MachOper array is sized by

  // specific MachNodes described in the ADL.

  uint _num_opnds;

  MachOper **_opnds;

  uint  num_opnds() const { return _num_opnds; }

  // Emit bytes into cbuf

  virtual void  emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;

  // Expand node after register allocation.

  // Node is replaced by several nodes in the postalloc expand phase.

  // Corresponding methods are generated for nodes if they specify

  // postalloc_expand. See block.cpp for more documentation.

  virtual bool requires_postalloc_expand() const { return false; }

  virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);

  // Size of instruction in bytes

  virtual uint  size(PhaseRegAlloc *ra_) const;

  // Helper function that computes size by emitting code

  virtual uint  emit_size(PhaseRegAlloc *ra_) const;

  // Return the alignment required (in units of relocInfo::addr_unit())

  // for this instruction (must be a power of 2)

  virtual int   alignment_required() const { return 1; }

  // Return the padding (in bytes) to be emitted before this

  // instruction to properly align it.

  virtual int   compute_padding(int current_offset) const { return 0; }

  // Return number of relocatable values contained in this instruction

  virtual int   reloc() const { return 0; }

  // Return number of words used for double constants in this instruction

  virtual int   ins_num_consts() const { return 0; }

  // Hash and compare over operands.  Used to do GVN on machine Nodes.

  virtual uint  hash() const;

  virtual bool  cmp( const Node &n ) const;

  // Expand method for MachNode, replaces nodes representing pseudo

  // instructions with a set of nodes which represent real machine

  // instructions and compute the same value.

  virtual MachNode *Expand( State *, Node_List &proj_list, Node* mem ) { return this; }

  // Bottom_type call; value comes from operand0

  virtual const class Type *bottom_type() const { return _opnds[0]->type(); }

  virtual uint ideal_reg() const {

    const Type *t = _opnds[0]->type();

    if (t == TypeInt::CC) {

      return Op_RegFlags;

    } else {

      return t->ideal_reg();

    }

  }

  // If this is a memory op, return the base pointer and fixed offset.

  // If there are no such, return NULL.  If there are multiple addresses

  // or the address is indeterminate (rare cases) then return (Node*)-1,

  // which serves as node bottom.

  // If the offset is not statically determined, set it to Type::OffsetBot.

  // This method is free to ignore stack slots if that helps.

  #define TYPE_PTR_SENTINAL  ((const TypePtr*)-1)

  // Passing TYPE_PTR_SENTINAL as adr_type asks for computation of the adr_type if possible

  const Node* get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const;

  // Helper for get_base_and_disp: find the base and index input nodes.

  // Returns the MachOper as determined by memory_operand(), for use, if

  // needed by the caller. If (MachOper *)-1 is returned, base and index

  // are set to NodeSentinel. If (MachOper *) NULL is returned, base and

  // index are set to NULL.

  const MachOper* memory_inputs(Node* &base, Node* &index) const;

  // Helper for memory_inputs:  Which operand carries the necessary info?

  // By default, returns NULL, which means there is no such operand.

  // If it returns (MachOper*)-1, this means there are multiple memories.

  virtual const MachOper* memory_operand() const { return NULL; }

  // Call "get_base_and_disp" to decide which category of memory is used here.

  virtual const class TypePtr *adr_type() const;

  // Apply peephole rule(s) to this instruction

  virtual MachNode *peephole(Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted);

  // Top-level ideal Opcode matched

  virtual int ideal_Opcode()     const { return Op_Node; }

  // Adds the label for the case

  virtual void add_case_label( int switch_val, Label* blockLabel);

  // Set the absolute address for methods

  virtual void method_set( intptr_t addr );

  // Should we clone rather than spill this instruction?

  bool rematerialize() const;

  // Get the pipeline info

  static const Pipeline *pipeline_class();

  virtual const Pipeline *pipeline() const;

  // Returns true if this node is a check that can be implemented with a trap.

  virtual bool is_TrapBasedCheckNode() const { return false; }

#ifndef PRODUCT

  virtual const char *Name() const = 0; // Machine-specific name

  virtual void dump_spec(outputStream *st) const; // Print per-node info

  void         dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual

#endif

};

//------------------------------MachIdealNode----------------------------

// Machine specific versions of nodes that must be defined by user.

// These are not converted by matcher from ideal nodes to machine nodes

// but are inserted into the code by the compiler.

class MachIdealNode : public MachNode {

public:

  MachIdealNode( ) {}

  // Define the following defaults for non-matched machine nodes

  virtual uint oper_input_base() const { return 0; }

  virtual uint rule()            const { return 9999999; }

  virtual const class Type *bottom_type() const { return _opnds == NULL ? Type::CONTROL : MachNode::bottom_type(); }

};

//------------------------------MachTypeNode----------------------------

// Machine Nodes that need to retain a known Type.

class MachTypeNode : public MachNode {

  virtual uint size_of() const { return sizeof(*this); } // Size is bigger

public:

  MachTypeNode( ) {}

  const Type *_bottom_type;

  virtual const class Type *bottom_type() const { return _bottom_type; }

#ifndef PRODUCT

  virtual void dump_spec(outputStream *st) const;

#endif

};

//------------------------------MachBreakpointNode----------------------------

// Machine breakpoint or interrupt Node

class MachBreakpointNode : public MachIdealNode {

public:

  MachBreakpointNode( ) {}

  virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;

  virtual uint size(PhaseRegAlloc *ra_) const;

#ifndef PRODUCT

  virtual const char *Name() const { return "Breakpoint"; }

  virtual void format( PhaseRegAlloc *, outputStream *st ) const;

#endif

};

//------------------------------MachConstantBaseNode--------------------------

// Machine node that represents the base address of the constant table.

class MachConstantBaseNode : public MachIdealNode {

public:

  static const RegMask& _out_RegMask;  // We need the out_RegMask statically in MachConstantNode::in_RegMask().

public:

  MachConstantBaseNode() : MachIdealNode() {

    init_class_id(Class_MachConstantBase);

  }

  virtual const class Type* bottom_type() const { return TypeRawPtr::NOTNULL; }

  virtual uint ideal_reg() const { return Op_RegP; }

  virtual uint oper_input_base() const { return 1; }

  virtual bool requires_postalloc_expand() const;

  virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);

  virtual void emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const;

  virtual uint size(PhaseRegAlloc* ra_) const;

  virtual bool pinned() const { return UseRDPCForConstantTableBase; }

  static const RegMask& static_out_RegMask() { return _out_RegMask; }

  virtual const RegMask& out_RegMask() const { return static_out_RegMask(); }

#ifndef PRODUCT

  virtual const char* Name() const { return "MachConstantBaseNode"; }

  virtual void format(PhaseRegAlloc*, outputStream* st) const;

#endif

};

//------------------------------MachConstantNode-------------------------------

// Machine node that holds a constant which is stored in the constant table.

class MachConstantNode : public MachTypeNode {

protected:

  Compile::Constant _constant;  // This node's constant.

public:

  MachConstantNode() : MachTypeNode() {

    init_class_id(Class_MachConstant);

  }

  virtual void eval_constant(Compile* C) {

#ifdef ASSERT

    tty->print("missing MachConstantNode eval_constant function: ");

    dump();

#endif

    ShouldNotCallThis();

  }

  virtual const RegMask &in_RegMask(uint idx) const {

    if (idx == mach_constant_base_node_input())

      return MachConstantBaseNode::static_out_RegMask();

    return MachNode::in_RegMask(idx);

  }

  // Input edge of MachConstantBaseNode.

  virtual uint mach_constant_base_node_input() const { return req() - 1; }

  int  constant_offset();

  int  constant_offset() const { return ((MachConstantNode*) this)->constant_offset(); }

  // Unchecked version to avoid assertions in debug output.

  int  constant_offset_unchecked() const;

};

//------------------------------MachUEPNode-----------------------------------

// Machine Unvalidated Entry Point Node

class MachUEPNode : public MachIdealNode {

public:

  MachUEPNode( ) {}

  virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;

  virtual uint size(PhaseRegAlloc *ra_) const;

#ifndef PRODUCT

  virtual const char *Name() const { return "Unvalidated-Entry-Point"; }

  virtual void format( PhaseRegAlloc *, outputStream *st ) const;

#endif

};

//------------------------------MachPrologNode--------------------------------

// Machine function Prolog Node

class MachPrologNode : public MachIdealNode {

public:

  MachPrologNode( ) {}

  virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;

  virtual uint size(PhaseRegAlloc *ra_) const;

  virtual int reloc() const;

#ifndef PRODUCT

  virtual const char *Name() const { return "Prolog"; }

  virtual void format( PhaseRegAlloc *, outputStream *st ) const;

#endif

};

//------------------------------MachEpilogNode--------------------------------

// Machine function Epilog Node

class MachEpilogNode : public MachIdealNode {

public:

  MachEpilogNode(bool do_poll = false) : _do_polling(do_poll) {}