| author | chegar |
| Thu, 17 Oct 2019 20:54:25 +0100 | |
| branch | datagramsocketimpl-branch |
| changeset 58679 | 9c3209ff7550 |
| parent 58678 | 9cf78a70fa4f |
| parent 58019 | 86b95fc6ca32 |
| permissions | -rw-r--r-- |
| 42065 | 1 |
// |
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
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// Copyright (c) 2017, 2019, Oracle and/or its affiliates. All rights reserved. |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
3 |
// Copyright (c) 2017, 2019 SAP SE. All rights reserved. |
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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// |
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// This code is free software; you can redistribute it and/or modify it |
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// under the terms of the GNU General Public License version 2 only, as |
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// published by the Free Software Foundation. |
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// |
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// This code is distributed in the hope that it will be useful, but WITHOUT |
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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// version 2 for more details (a copy is included in the LICENSE file that |
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// accompanied this code). |
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// |
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// You should have received a copy of the GNU General Public License version |
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// 2 along with this work; if not, write to the Free Software Foundation, |
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// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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// |
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// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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// or visit www.oracle.com if you need additional information or have any |
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// questions. |
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// |
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// z/Architecture Architecture Description File |
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// Major contributions by AS, JL, LS. |
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// |
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// Following information is derived from private mail communication |
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// (Oct. 2011). |
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// |
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// General branch target alignment considerations |
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// |
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// z/Architecture does not imply a general branch target alignment requirement. |
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// There are side effects and side considerations, though, which may |
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// provide some performance benefit. These are: |
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// - Align branch target on octoword (32-byte) boundary |
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// On more recent models (from z9 on), I-fetch is done on a Octoword |
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// (32 bytes at a time) basis. To avoid I-fetching unnecessary |
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// instructions, branch targets should be 32-byte aligend. If this |
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// exact alingment cannot be achieved, having the branch target in |
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// the first doubleword still provides some benefit. |
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// - Avoid branch targets at the end of cache lines (> 64 bytes distance). |
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// Sequential instruction prefetching after the branch target starts |
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// immediately after having fetched the octoword containing the |
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// branch target. When I-fetching crosses a cache line, there may be |
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// a small stall. The worst case: the branch target (at the end of |
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// a cache line) is a L1 I-cache miss and the next line as well. |
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// Then, the entire target line must be filled first (to contine at the |
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// branch target). Only then can the next sequential line be filled. |
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// - Avoid multiple poorly predicted branches in a row. |
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// |
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||
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//----------REGISTER DEFINITION BLOCK------------------------------------------ |
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// This information is used by the matcher and the register allocator to |
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// describe individual registers and classes of registers within the target |
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// architecture. |
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register %{
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//----------Architecture Description Register Definitions---------------------- |
|
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// General Registers |
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// "reg_def" name (register save type, C convention save type, |
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// ideal register type, encoding); |
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// |
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// Register Save Types: |
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// |
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// NS = No-Save: The register allocator assumes that these registers |
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// can be used without saving upon entry to the method, & |
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// that they do not need to be saved at call sites. |
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// |
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// SOC = Save-On-Call: The register allocator assumes that these registers |
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// can be used without saving upon entry to the method, |
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// but that they must be saved at call sites. |
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// |
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// SOE = Save-On-Entry: The register allocator assumes that these registers |
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// must be saved before using them upon entry to the |
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// method, but they do not need to be saved at call sites. |
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// |
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// AS = Always-Save: The register allocator assumes that these registers |
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// must be saved before using them upon entry to the |
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// method, & that they must be saved at call sites. |
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// |
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// Ideal Register Type is used to determine how to save & restore a |
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// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get |
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// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. |
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// |
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// The encoding number is the actual bit-pattern placed into the opcodes. |
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// z/Architecture register definitions, based on the z/Architecture Principles |
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// of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement, |
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// 5th Edition, March 2001. |
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// |
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// For each 64-bit register we must define two registers: the register |
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// itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half', |
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// e.g. Z_R3_H, which is needed by the allocator, but is not used |
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// for stores, loads, etc. |
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// Integer/Long Registers |
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// ---------------------------- |
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// z/Architecture has 16 64-bit integer registers. |
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// types: v = volatile, nv = non-volatile, s = system |
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reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1 |
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reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next()); |
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reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2 |
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reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next()); |
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reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret |
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reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next()); |
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reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2 |
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reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next()); |
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reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3 |
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reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next()); |
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reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4 |
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reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next()); |
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reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5 |
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reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next()); |
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reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg()); |
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reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next()); |
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reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg()); |
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reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next()); |
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reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg()); |
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reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next()); |
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reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg()); |
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reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next()); |
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reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg()); |
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reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next()); |
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reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg()); |
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reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next()); |
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reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg()); |
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reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next()); |
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reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc |
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reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next()); |
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reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP |
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reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next()); |
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// Float/Double Registers |
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// The rules of ADL require that double registers be defined in pairs. |
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// Each pair must be two 32-bit values, but not necessarily a pair of |
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// single float registers. In each pair, ADLC-assigned register numbers |
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// must be adjacent, with the lower number even. Finally, when the |
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// CPU stores such a register pair to memory, the word associated with |
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// the lower ADLC-assigned number must be stored to the lower address. |
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// z/Architecture has 16 64-bit floating-point registers. Each can store a single |
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// or double precision floating-point value. |
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// types: v = volatile, nv = non-volatile, s = system |
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reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret |
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reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next()); |
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reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg()); |
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reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next()); |
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reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2 |
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reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next()); |
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reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg()); |
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reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next()); |
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reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3 |
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reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next()); |
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reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg()); |
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reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next()); |
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reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg()); |
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reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next()); |
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reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg()); |
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reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next()); |
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reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg()); |
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reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next()); |
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reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg()); |
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reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next()); |
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reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg()); |
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reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next()); |
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reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg()); |
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reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next()); |
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reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg()); |
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reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next()); |
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reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg()); |
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reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next()); |
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reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg()); |
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reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next()); |
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reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg()); |
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reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next()); |
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// Special Registers |
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// Condition Codes Flag Registers |
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// z/Architecture has the PSW (program status word) that contains |
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// (among other information) the condition code. We treat this |
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// part of the PSW as a condition register CR. It consists of 4 |
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// bits. Floating point instructions influence the same condition register CR. |
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reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile |
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// Specify priority of register selection within phases of register |
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// allocation. Highest priority is first. A useful heuristic is to |
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// give registers a low priority when they are required by machine |
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// instructions, and choose no-save registers before save-on-call, and |
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// save-on-call before save-on-entry. Registers which participate in |
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// fix calling sequences should come last. Registers which are used |
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// as pairs must fall on an even boundary. |
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// It's worth about 1% on SPEC geomean to get this right. |
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// Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration |
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// in adGlobals_s390.hpp which defines the <register>_num values, e.g. |
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// Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not) |
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// the same as Z_R3->encoding()! Furthermore, we cannot make any |
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// assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num. |
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// Additionally, the function |
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// static enum RC rc_class(OptoReg::Name reg) |
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// maps a given <register>_num value to its chunk type (except for flags) |
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// and its current implementation relies on chunk0 and chunk1 having a |
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// size of 64 each. |
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alloc_class chunk0( |
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// chunk0 contains *all* 32 integer registers halves. |
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// potential SOE regs |
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Z_R13,Z_R13_H, |
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Z_R12,Z_R12_H, |
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Z_R11,Z_R11_H, |
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Z_R10,Z_R10_H, |
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Z_R9,Z_R9_H, |
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Z_R8,Z_R8_H, |
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Z_R7,Z_R7_H, |
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Z_R1,Z_R1_H, |
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Z_R0,Z_R0_H, |
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// argument registers |
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Z_R6,Z_R6_H, |
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Z_R5,Z_R5_H, |
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Z_R4,Z_R4_H, |
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Z_R3,Z_R3_H, |
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Z_R2,Z_R2_H, |
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// special registers |
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Z_R14,Z_R14_H, |
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Z_R15,Z_R15_H |
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); |
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||
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alloc_class chunk1( |
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// Chunk1 contains *all* 64 floating-point registers halves. |
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Z_F15,Z_F15_H, |
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Z_F14,Z_F14_H, |
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Z_F13,Z_F13_H, |
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Z_F12,Z_F12_H, |
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Z_F11,Z_F11_H, |
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Z_F10,Z_F10_H, |
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Z_F9,Z_F9_H, |
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Z_F8,Z_F8_H, |
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// scratch register |
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Z_F7,Z_F7_H, |
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Z_F5,Z_F5_H, |
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Z_F3,Z_F3_H, |
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Z_F1,Z_F1_H, |
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// argument registers |
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Z_F6,Z_F6_H, |
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Z_F4,Z_F4_H, |
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Z_F2,Z_F2_H, |
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Z_F0,Z_F0_H |
|
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); |
|
269 |
||
270 |
alloc_class chunk2( |
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Z_CR |
|
272 |
); |
|
273 |
||
274 |
||
275 |
//-------Architecture Description Register Classes----------------------- |
|
276 |
||
277 |
// Several register classes are automatically defined based upon |
|
278 |
// information in this architecture description. |
|
279 |
||
280 |
// 1) reg_class inline_cache_reg (as defined in frame section) |
|
281 |
// 2) reg_class compiler_method_oop_reg (as defined in frame section) |
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282 |
// 2) reg_class interpreter_method_oop_reg (as defined in frame section) |
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283 |
// 3) reg_class stack_slots(/* one chunk of stack-based "registers" */) |
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284 |
||
285 |
// Integer Register Classes |
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286 |
reg_class z_int_reg( |
|
287 |
/*Z_R0*/ // R0 |
|
288 |
/*Z_R1*/ |
|
289 |
Z_R2, |
|
290 |
Z_R3, |
|
291 |
Z_R4, |
|
292 |
Z_R5, |
|
293 |
Z_R6, |
|
294 |
Z_R7, |
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295 |
/*Z_R8,*/ // Z_thread |
|
296 |
Z_R9, |
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297 |
Z_R10, |
|
298 |
Z_R11, |
|
299 |
Z_R12, |
|
300 |
Z_R13 |
|
301 |
/*Z_R14*/ // return_pc |
|
302 |
/*Z_R15*/ // SP |
|
303 |
); |
|
304 |
||
305 |
reg_class z_no_odd_int_reg( |
|
306 |
/*Z_R0*/ // R0 |
|
307 |
/*Z_R1*/ |
|
308 |
Z_R2, |
|
309 |
Z_R3, |
|
310 |
Z_R4, |
|
311 |
/*Z_R5,*/ // odd part of fix register pair |
|
312 |
Z_R6, |
|
313 |
Z_R7, |
|
314 |
/*Z_R8,*/ // Z_thread |
|
315 |
Z_R9, |
|
316 |
Z_R10, |
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317 |
Z_R11, |
|
318 |
Z_R12, |
|
319 |
Z_R13 |
|
320 |
/*Z_R14*/ // return_pc |
|
321 |
/*Z_R15*/ // SP |
|
322 |
); |
|
323 |
||
324 |
reg_class z_no_arg_int_reg( |
|
325 |
/*Z_R0*/ // R0 |
|
326 |
/*Z_R1*/ // scratch |
|
327 |
/*Z_R2*/ |
|
328 |
/*Z_R3*/ |
|
329 |
/*Z_R4*/ |
|
330 |
/*Z_R5*/ |
|
331 |
/*Z_R6*/ |
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332 |
Z_R7, |
|
333 |
/*Z_R8*/ // Z_thread |
|
334 |
Z_R9, |
|
335 |
Z_R10, |
|
336 |
Z_R11, |
|
337 |
Z_R12, |
|
338 |
Z_R13 |
|
339 |
/*Z_R14*/ // return_pc |
|
340 |
/*Z_R15*/ // SP |
|
341 |
); |
|
342 |
||
343 |
reg_class z_rarg1_int_reg(Z_R2); |
|
344 |
reg_class z_rarg2_int_reg(Z_R3); |
|
345 |
reg_class z_rarg3_int_reg(Z_R4); |
|
346 |
reg_class z_rarg4_int_reg(Z_R5); |
|
347 |
reg_class z_rarg5_int_reg(Z_R6); |
|
348 |
||
349 |
// Pointer Register Classes |
|
350 |
||
351 |
// 64-bit build means 64-bit pointers means hi/lo pairs. |
|
352 |
||
353 |
reg_class z_rarg5_ptrN_reg(Z_R6); |
|
354 |
||
355 |
reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2); |
|
356 |
reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3); |
|
357 |
reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4); |
|
358 |
reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5); |
|
359 |
reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6); |
|
360 |
reg_class z_thread_ptr_reg(Z_R8_H,Z_R8); |
|
361 |
||
362 |
reg_class z_ptr_reg( |
|
363 |
/*Z_R0_H,Z_R0*/ // R0 |
|
364 |
/*Z_R1_H,Z_R1*/ |
|
365 |
Z_R2_H,Z_R2, |
|
366 |
Z_R3_H,Z_R3, |
|
367 |
Z_R4_H,Z_R4, |
|
368 |
Z_R5_H,Z_R5, |
|
369 |
Z_R6_H,Z_R6, |
|
370 |
Z_R7_H,Z_R7, |
|
371 |
/*Z_R8_H,Z_R8,*/ // Z_thread |
|
372 |
Z_R9_H,Z_R9, |
|
373 |
Z_R10_H,Z_R10, |
|
374 |
Z_R11_H,Z_R11, |
|
375 |
Z_R12_H,Z_R12, |
|
376 |
Z_R13_H,Z_R13 |
|
377 |
/*Z_R14_H,Z_R14*/ // return_pc |
|
378 |
/*Z_R15_H,Z_R15*/ // SP |
|
379 |
); |
|
380 |
||
381 |
reg_class z_lock_ptr_reg( |
|
382 |
/*Z_R0_H,Z_R0*/ // R0 |
|
383 |
/*Z_R1_H,Z_R1*/ |
|
384 |
Z_R2_H,Z_R2, |
|
385 |
Z_R3_H,Z_R3, |
|
386 |
Z_R4_H,Z_R4, |
|
387 |
/*Z_R5_H,Z_R5,*/ |
|
388 |
/*Z_R6_H,Z_R6,*/ |
|
389 |
Z_R7_H,Z_R7, |
|
390 |
/*Z_R8_H,Z_R8,*/ // Z_thread |
|
391 |
Z_R9_H,Z_R9, |
|
392 |
Z_R10_H,Z_R10, |
|
393 |
Z_R11_H,Z_R11, |
|
394 |
Z_R12_H,Z_R12, |
|
395 |
Z_R13_H,Z_R13 |
|
396 |
/*Z_R14_H,Z_R14*/ // return_pc |
|
397 |
/*Z_R15_H,Z_R15*/ // SP |
|
398 |
); |
|
399 |
||
400 |
reg_class z_no_arg_ptr_reg( |
|
401 |
/*Z_R0_H,Z_R0*/ // R0 |
|
402 |
/*Z_R1_H,Z_R1*/ // scratch |
|
403 |
/*Z_R2_H,Z_R2*/ |
|
404 |
/*Z_R3_H,Z_R3*/ |
|
405 |
/*Z_R4_H,Z_R4*/ |
|
406 |
/*Z_R5_H,Z_R5*/ |
|
407 |
/*Z_R6_H,Z_R6*/ |
|
408 |
Z_R7_H, Z_R7, |
|
409 |
/*Z_R8_H,Z_R8*/ // Z_thread |
|
410 |
Z_R9_H,Z_R9, |
|
411 |
Z_R10_H,Z_R10, |
|
412 |
Z_R11_H,Z_R11, |
|
413 |
Z_R12_H,Z_R12, |
|
414 |
Z_R13_H,Z_R13 |
|
415 |
/*Z_R14_H,Z_R14*/ // return_pc |
|
416 |
/*Z_R15_H,Z_R15*/ // SP |
|
417 |
); |
|
418 |
||
419 |
// Special class for storeP instructions, which can store SP or RPC to |
|
420 |
// TLS. (Note: Do not generalize this to "any_reg". If you add |
|
421 |
// another register, such as FP, to this mask, the allocator may try |
|
422 |
// to put a temp in it.) |
|
423 |
// Register class for memory access base registers, |
|
424 |
// This class is a superset of z_ptr_reg including Z_thread. |
|
425 |
reg_class z_memory_ptr_reg( |
|
426 |
/*Z_R0_H,Z_R0*/ // R0 |
|
427 |
/*Z_R1_H,Z_R1*/ |
|
428 |
Z_R2_H,Z_R2, |
|
429 |
Z_R3_H,Z_R3, |
|
430 |
Z_R4_H,Z_R4, |
|
431 |
Z_R5_H,Z_R5, |
|
432 |
Z_R6_H,Z_R6, |
|
433 |
Z_R7_H,Z_R7, |
|
434 |
Z_R8_H,Z_R8, // Z_thread |
|
435 |
Z_R9_H,Z_R9, |
|
436 |
Z_R10_H,Z_R10, |
|
437 |
Z_R11_H,Z_R11, |
|
438 |
Z_R12_H,Z_R12, |
|
439 |
Z_R13_H,Z_R13 |
|
440 |
/*Z_R14_H,Z_R14*/ // return_pc |
|
441 |
/*Z_R15_H,Z_R15*/ // SP |
|
442 |
); |
|
443 |
||
444 |
// Other special pointer regs. |
|
445 |
reg_class z_r1_regP(Z_R1_H,Z_R1); |
|
446 |
reg_class z_r9_regP(Z_R9_H,Z_R9); |
|
447 |
||
448 |
||
449 |
// Long Register Classes |
|
450 |
||
451 |
reg_class z_rarg1_long_reg(Z_R2_H,Z_R2); |
|
452 |
reg_class z_rarg2_long_reg(Z_R3_H,Z_R3); |
|
453 |
reg_class z_rarg3_long_reg(Z_R4_H,Z_R4); |
|
454 |
reg_class z_rarg4_long_reg(Z_R5_H,Z_R5); |
|
455 |
reg_class z_rarg5_long_reg(Z_R6_H,Z_R6); |
|
456 |
||
457 |
// Longs in 1 register. Aligned adjacent hi/lo pairs. |
|
458 |
reg_class z_long_reg( |
|
459 |
/*Z_R0_H,Z_R0*/ // R0 |
|
460 |
/*Z_R1_H,Z_R1*/ |
|
461 |
Z_R2_H,Z_R2, |
|
462 |
Z_R3_H,Z_R3, |
|
463 |
Z_R4_H,Z_R4, |
|
464 |
Z_R5_H,Z_R5, |
|
465 |
Z_R6_H,Z_R6, |
|
466 |
Z_R7_H,Z_R7, |
|
467 |
/*Z_R8_H,Z_R8,*/ // Z_thread |
|
468 |
Z_R9_H,Z_R9, |
|
469 |
Z_R10_H,Z_R10, |
|
470 |
Z_R11_H,Z_R11, |
|
471 |
Z_R12_H,Z_R12, |
|
472 |
Z_R13_H,Z_R13 |
|
473 |
/*Z_R14_H,Z_R14,*/ // return_pc |
|
474 |
/*Z_R15_H,Z_R15*/ // SP |
|
475 |
); |
|
476 |
||
|
54542
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
477 |
// z_long_reg without even registers |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
478 |
reg_class z_long_odd_reg( |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
479 |
/*Z_R0_H,Z_R0*/ // R0 |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
480 |
/*Z_R1_H,Z_R1*/ |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
481 |
Z_R3_H,Z_R3, |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
482 |
Z_R5_H,Z_R5, |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
483 |
Z_R7_H,Z_R7, |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
484 |
Z_R9_H,Z_R9, |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
485 |
Z_R11_H,Z_R11, |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
486 |
Z_R13_H,Z_R13 |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
487 |
/*Z_R14_H,Z_R14,*/ // return_pc |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
488 |
/*Z_R15_H,Z_R15*/ // SP |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
489 |
); |
| 42065 | 490 |
|
491 |
// Special Class for Condition Code Flags Register |
|
492 |
||
493 |
reg_class z_condition_reg( |
|
494 |
Z_CR |
|
495 |
); |
|
496 |
||
497 |
// Scratch register for late profiling. Callee saved. |
|
498 |
reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2); |
|
499 |
||
500 |
||
501 |
// Float Register Classes |
|
502 |
||
503 |
reg_class z_flt_reg( |
|
504 |
Z_F0, |
|
505 |
/*Z_F1,*/ // scratch |
|
506 |
Z_F2, |
|
507 |
Z_F3, |
|
508 |
Z_F4, |
|
509 |
Z_F5, |
|
510 |
Z_F6, |
|
511 |
Z_F7, |
|
512 |
Z_F8, |
|
513 |
Z_F9, |
|
514 |
Z_F10, |
|
515 |
Z_F11, |
|
516 |
Z_F12, |
|
517 |
Z_F13, |
|
518 |
Z_F14, |
|
519 |
Z_F15 |
|
520 |
); |
|
521 |
reg_class z_rscratch1_flt_reg(Z_F1); |
|
522 |
||
523 |
// Double precision float registers have virtual `high halves' that |
|
524 |
// are needed by the allocator. |
|
525 |
reg_class z_dbl_reg( |
|
526 |
Z_F0,Z_F0_H, |
|
527 |
/*Z_F1,Z_F1_H,*/ // scratch |
|
528 |
Z_F2,Z_F2_H, |
|
529 |
Z_F3,Z_F3_H, |
|
530 |
Z_F4,Z_F4_H, |
|
531 |
Z_F5,Z_F5_H, |
|
532 |
Z_F6,Z_F6_H, |
|
533 |
Z_F7,Z_F7_H, |
|
534 |
Z_F8,Z_F8_H, |
|
535 |
Z_F9,Z_F9_H, |
|
536 |
Z_F10,Z_F10_H, |
|
537 |
Z_F11,Z_F11_H, |
|
538 |
Z_F12,Z_F12_H, |
|
539 |
Z_F13,Z_F13_H, |
|
540 |
Z_F14,Z_F14_H, |
|
541 |
Z_F15,Z_F15_H |
|
542 |
); |
|
543 |
reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H); |
|
544 |
||
545 |
%} |
|
546 |
||
547 |
//----------DEFINITION BLOCK--------------------------------------------------- |
|
548 |
// Define 'name --> value' mappings to inform the ADLC of an integer valued name. |
|
549 |
// Current support includes integer values in the range [0, 0x7FFFFFFF]. |
|
550 |
// Format: |
|
551 |
// int_def <name> (<int_value>, <expression>); |
|
552 |
// Generated Code in ad_<arch>.hpp |
|
553 |
// #define <name> (<expression>) |
|
554 |
// // value == <int_value> |
|
555 |
// Generated code in ad_<arch>.cpp adlc_verification() |
|
556 |
// assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>"); |
|
557 |
// |
|
558 |
definitions %{
|
|
559 |
// The default cost (of an ALU instruction). |
|
560 |
int_def DEFAULT_COST ( 100, 100); |
|
561 |
int_def DEFAULT_COST_LOW ( 80, 80); |
|
562 |
int_def DEFAULT_COST_HIGH ( 120, 120); |
|
563 |
int_def HUGE_COST (1000000, 1000000); |
|
564 |
||
565 |
// Put an advantage on REG_MEM vs. MEM+REG_REG operations. |
|
566 |
int_def ALU_REG_COST ( 100, DEFAULT_COST); |
|
567 |
int_def ALU_MEMORY_COST ( 150, 150); |
|
568 |
||
569 |
// Memory refs are twice as expensive as run-of-the-mill. |
|
570 |
int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20); |
|
571 |
int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST); |
|
572 |
int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20); |
|
573 |
||
574 |
// Branches are even more expensive. |
|
575 |
int_def BRANCH_COST ( 300, DEFAULT_COST * 3); |
|
576 |
int_def CALL_COST ( 300, DEFAULT_COST * 3); |
|
577 |
%} |
|
578 |
||
579 |
source %{
|
|
580 |
||
581 |
#ifdef PRODUCT |
|
582 |
#define BLOCK_COMMENT(str) |
|
583 |
#define BIND(label) __ bind(label) |
|
584 |
#else |
|
585 |
#define BLOCK_COMMENT(str) __ block_comment(str) |
|
586 |
#define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":") |
|
587 |
#endif |
|
588 |
||
589 |
#define __ _masm. |
|
590 |
||
591 |
#define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6 |
|
592 |
#define Z_DISP3_SIZE 6 |
|
593 |
||
594 |
// Tertiary op of a LoadP or StoreP encoding. |
|
595 |
#define REGP_OP true |
|
596 |
||
597 |
// Given a register encoding, produce an Integer Register object. |
|
598 |
static Register reg_to_register_object(int register_encoding); |
|
599 |
||
600 |
// **************************************************************************** |
|
601 |
||
602 |
// REQUIRED FUNCTIONALITY |
|
603 |
||
604 |
// !!!!! Special hack to get all type of calls to specify the byte offset |
|
605 |
// from the start of the call to the point where the return address |
|
606 |
// will point. |
|
607 |
||
608 |
int MachCallStaticJavaNode::ret_addr_offset() {
|
|
609 |
if (_method) {
|
|
610 |
return 8; |
|
611 |
} else {
|
|
612 |
return MacroAssembler::call_far_patchable_ret_addr_offset(); |
|
613 |
} |
|
614 |
} |
|
615 |
||
616 |
int MachCallDynamicJavaNode::ret_addr_offset() {
|
|
617 |
// Consider size of receiver type profiling (C2 tiers). |
|
618 |
int profile_receiver_type_size = 0; |
|
619 |
||
620 |
int vtable_index = this->_vtable_index; |
|
621 |
if (vtable_index == -4) {
|
|
622 |
return 14 + profile_receiver_type_size; |
|
623 |
} else {
|
|
624 |
assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); |
|
625 |
return 36 + profile_receiver_type_size; |
|
626 |
} |
|
627 |
} |
|
628 |
||
629 |
int MachCallRuntimeNode::ret_addr_offset() {
|
|
630 |
return 12 + MacroAssembler::call_far_patchable_ret_addr_offset(); |
|
631 |
} |
|
632 |
||
633 |
// Compute padding required for nodes which need alignment |
|
634 |
// |
|
635 |
// The addresses of the call instructions needs to be 4-byte aligned to |
|
636 |
// ensure that they don't span a cache line so that they are atomically patchable. |
|
637 |
// The actual calls get emitted at different offsets within the node emitters. |
|
638 |
// ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted. |
|
639 |
||
640 |
int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
|
|
641 |
return (0 - current_offset) & 2; |
|
642 |
} |
|
643 |
||
644 |
int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
|
|
645 |
return (6 - current_offset) & 2; |
|
646 |
} |
|
647 |
||
648 |
int CallRuntimeDirectNode::compute_padding(int current_offset) const {
|
|
649 |
return (12 - current_offset) & 2; |
|
650 |
} |
|
651 |
||
652 |
int CallLeafDirectNode::compute_padding(int current_offset) const {
|
|
653 |
return (12 - current_offset) & 2; |
|
654 |
} |
|
655 |
||
656 |
int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
|
|
657 |
return (12 - current_offset) & 2; |
|
658 |
} |
|
659 |
||
660 |
// Indicate if the safepoint node needs the polling page as an input. |
|
661 |
// Since z/Architecture does not have absolute addressing, it does. |
|
662 |
bool SafePointNode::needs_polling_address_input() {
|
|
663 |
return true; |
|
664 |
} |
|
665 |
||
666 |
void emit_nop(CodeBuffer &cbuf) {
|
|
667 |
MacroAssembler _masm(&cbuf); |
|
668 |
__ z_nop(); |
|
669 |
} |
|
670 |
||
671 |
// Emit an interrupt that is caught by the debugger (for debugging compiler). |
|
672 |
void emit_break(CodeBuffer &cbuf) {
|
|
673 |
MacroAssembler _masm(&cbuf); |
|
674 |
__ z_illtrap(); |
|
675 |
} |
|
676 |
||
677 |
#if !defined(PRODUCT) |
|
678 |
void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
|
|
679 |
os->print("TA");
|
|
680 |
} |
|
681 |
#endif |
|
682 |
||
683 |
void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
684 |
emit_break(cbuf); |
|
685 |
} |
|
686 |
||
687 |
uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
|
|
688 |
return MachNode::size(ra_); |
|
689 |
} |
|
690 |
||
691 |
static inline void z_emit16(CodeBuffer &cbuf, long value) {
|
|
692 |
// 32bit instructions may become sign extended. |
|
693 |
assert(value >= 0, "unintended sign extension (int->long)"); |
|
694 |
assert(value < (1L << 16), "instruction too large"); |
|
695 |
*((unsigned short*)(cbuf.insts_end())) = (unsigned short)value; |
|
696 |
cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short)); |
|
697 |
} |
|
698 |
||
699 |
static inline void z_emit32(CodeBuffer &cbuf, long value) {
|
|
700 |
// 32bit instructions may become sign extended. |
|
701 |
assert(value < (1L << 32), "instruction too large"); |
|
702 |
*((unsigned int*)(cbuf.insts_end())) = (unsigned int)value; |
|
703 |
cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int)); |
|
704 |
} |
|
705 |
||
706 |
static inline void z_emit48(CodeBuffer &cbuf, long value) {
|
|
707 |
// 32bit instructions may become sign extended. |
|
708 |
assert(value >= 0, "unintended sign extension (int->long)"); |
|
709 |
assert(value < (1L << 48), "instruction too large"); |
|
710 |
value = value<<16; |
|
711 |
memcpy(cbuf.insts_end(), (unsigned char*)&value, 6); |
|
712 |
cbuf.set_insts_end(cbuf.insts_end() + 6); |
|
713 |
} |
|
714 |
||
715 |
static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) {
|
|
716 |
if (value < 0) {
|
|
717 |
// There obviously has been an unintended sign extension (int->long). Revert it. |
|
718 |
value = (long)((unsigned long)((unsigned int)value)); |
|
719 |
} |
|
720 |
||
721 |
if (value < (1L << 16)) { // 2-byte instruction
|
|
722 |
z_emit16(cbuf, value); |
|
723 |
return 2; |
|
724 |
} |
|
725 |
||
726 |
if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store
|
|
727 |
z_emit32(cbuf, value); |
|
728 |
return 4; |
|
729 |
} |
|
730 |
||
731 |
// 6-byte instruction, probably unaligned store. |
|
732 |
z_emit48(cbuf, value); |
|
733 |
return 6; |
|
734 |
} |
|
735 |
||
736 |
// Check effective address (at runtime) for required alignment. |
|
737 |
static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) {
|
|
738 |
MacroAssembler _masm(&cbuf); |
|
739 |
||
740 |
__ z_lay(Z_R0, disp, index, base); |
|
741 |
__ z_nill(Z_R0, alignment-1); |
|
742 |
__ z_brc(Assembler::bcondEqual, +3); |
|
743 |
__ z_illtrap(); |
|
744 |
} |
|
745 |
||
746 |
int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype, |
|
747 |
PhaseRegAlloc* ra_, bool is_native_call = false) {
|
|
748 |
__ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp(). |
|
749 |
address old_mark = __ inst_mark(); |
|
750 |
unsigned int start_off = __ offset(); |
|
751 |
||
752 |
if (is_native_call) {
|
|
753 |
ShouldNotReachHere(); |
|
754 |
} |
|
755 |
||
756 |
if (rtype == relocInfo::runtime_call_w_cp_type) {
|
|
757 |
assert((__ offset() & 2) == 0, "misaligned emit_call_reloc"); |
|
758 |
address call_addr = __ call_c_opt((address)entry_point); |
|
759 |
if (call_addr == NULL) {
|
|
760 |
Compile::current()->env()->record_out_of_memory_failure(); |
|
761 |
return -1; |
|
762 |
} |
|
763 |
} else {
|
|
764 |
assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type || |
|
765 |
rtype == relocInfo::static_call_type, "unexpected rtype"); |
|
766 |
__ relocate(rtype); |
|
767 |
// BRASL must be prepended with a nop to identify it in the instruction stream. |
|
768 |
__ z_nop(); |
|
769 |
__ z_brasl(Z_R14, (address)entry_point); |
|
770 |
} |
|
771 |
||
772 |
unsigned int ret_off = __ offset(); |
|
773 |
||
774 |
return (ret_off - start_off); |
|
775 |
} |
|
776 |
||
777 |
static int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) {
|
|
778 |
__ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp(). |
|
779 |
address old_mark = __ inst_mark(); |
|
780 |
unsigned int start_off = __ offset(); |
|
781 |
||
782 |
relocInfo::relocType rtype = rspec.type(); |
|
783 |
assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type, |
|
784 |
"unexpected rtype"); |
|
785 |
||
786 |
__ relocate(rspec); |
|
787 |
__ z_nop(); |
|
788 |
__ z_brasl(Z_R14, (address)entry_point); |
|
789 |
||
790 |
unsigned int ret_off = __ offset(); |
|
791 |
||
792 |
return (ret_off - start_off); |
|
793 |
} |
|
794 |
||
795 |
//============================================================================= |
|
796 |
||
797 |
const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask; |
|
798 |
int Compile::ConstantTable::calculate_table_base_offset() const {
|
|
799 |
return 0; // absolute addressing, no offset |
|
800 |
} |
|
801 |
||
802 |
bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
|
|
803 |
void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
|
|
804 |
ShouldNotReachHere(); |
|
805 |
} |
|
806 |
||
807 |
// Even with PC-relative TOC addressing, we still need this node. |
|
808 |
// Float loads/stores do not support PC-relative addresses. |
|
809 |
void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
|
|
810 |
MacroAssembler _masm(&cbuf); |
|
811 |
Register Rtoc = as_Register(ra_->get_encode(this)); |
|
812 |
__ load_toc(Rtoc); |
|
813 |
} |
|
814 |
||
815 |
uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
|
|
816 |
// PCrelative TOC access. |
|
817 |
return 6; // sizeof(LARL) |
|
818 |
} |
|
819 |
||
820 |
#if !defined(PRODUCT) |
|
821 |
void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
|
|
822 |
Register r = as_Register(ra_->get_encode(this)); |
|
823 |
st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name());
|
|
824 |
} |
|
825 |
#endif |
|
826 |
||
827 |
//============================================================================= |
|
828 |
||
829 |
#if !defined(PRODUCT) |
|
830 |
void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
|
|
831 |
Compile* C = ra_->C; |
|
832 |
st->print_cr("--- MachPrologNode ---");
|
|
833 |
st->print("\t");
|
|
834 |
for (int i = 0; i < OptoPrologueNops; i++) {
|
|
835 |
st->print_cr("NOP"); st->print("\t");
|
|
836 |
} |
|
837 |
||
838 |
if (VerifyThread) {
|
|
839 |
st->print_cr("Verify_Thread");
|
|
840 |
st->print("\t");
|
|
841 |
} |
|
842 |
||
843 |
long framesize = C->frame_size_in_bytes(); |
|
844 |
int bangsize = C->bang_size_in_bytes(); |
|
845 |
||
846 |
// Calls to C2R adapters often do not accept exceptional returns. |
|
847 |
// We require that their callers must bang for them. But be |
|
848 |
// careful, because some VM calls (such as call site linkage) can |
|
849 |
// use several kilobytes of stack. But the stack safety zone should |
|
850 |
// account for that. See bugs 4446381, 4468289, 4497237. |
|
851 |
if (C->need_stack_bang(bangsize) && UseStackBanging) {
|
|
852 |
st->print_cr("# stack bang"); st->print("\t");
|
|
853 |
} |
|
854 |
st->print_cr("push_frame %d", (int)-framesize);
|
|
855 |
st->print("\t");
|
|
856 |
} |
|
857 |
#endif |
|
858 |
||
859 |
void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
860 |
Compile* C = ra_->C; |
|
861 |
MacroAssembler _masm(&cbuf); |
|
862 |
||
863 |
__ verify_thread(); |
|
864 |
||
865 |
size_t framesize = C->frame_size_in_bytes(); |
|
866 |
size_t bangsize = C->bang_size_in_bytes(); |
|
867 |
||
868 |
assert(framesize % wordSize == 0, "must preserve wordSize alignment"); |
|
869 |
||
|
55343
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
870 |
if (C->clinit_barrier_on_entry()) {
|
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
871 |
assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started"); |
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
872 |
|
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
873 |
Label L_skip_barrier; |
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
874 |
Register klass = Z_R1_scratch; |
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
875 |
|
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
876 |
// Notify OOP recorder (don't need the relocation) |
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
877 |
AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding()); |
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
878 |
__ load_const_optimized(klass, md.value()); |
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
879 |
__ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/); |
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
880 |
|
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
881 |
__ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub()); |
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
882 |
__ z_br(klass); |
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
883 |
|
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
884 |
__ bind(L_skip_barrier); |
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
885 |
} |
|
03d417fd7d9a
8224827: Implement fast class initialization checks on s390
mdoerr
parents:
54960
diff
changeset
|
886 |
|
| 42065 | 887 |
// Calls to C2R adapters often do not accept exceptional returns. |
888 |
// We require that their callers must bang for them. But be |
|
889 |
// careful, because some VM calls (such as call site linkage) can |
|
890 |
// use several kilobytes of stack. But the stack safety zone should |
|
891 |
// account for that. See bugs 4446381, 4468289, 4497237. |
|
892 |
if (C->need_stack_bang(bangsize) && UseStackBanging) {
|
|
893 |
__ generate_stack_overflow_check(bangsize); |
|
894 |
} |
|
895 |
||
896 |
assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!"); |
|
897 |
__ save_return_pc(); |
|
898 |
||
899 |
// The z/Architecture abi is already accounted for in `framesize' via the |
|
900 |
// 'out_preserve_stack_slots' declaration. |
|
901 |
__ push_frame((unsigned int)framesize/*includes JIT ABI*/); |
|
902 |
||
903 |
if (C->has_mach_constant_base_node()) {
|
|
904 |
// NOTE: We set the table base offset here because users might be |
|
905 |
// emitted before MachConstantBaseNode. |
|
906 |
Compile::ConstantTable& constant_table = C->constant_table(); |
|
907 |
constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
|
908 |
} |
|
909 |
} |
|
910 |
||
911 |
uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
|
|
912 |
// Variable size. Determine dynamically. |
|
913 |
return MachNode::size(ra_); |
|
914 |
} |
|
915 |
||
916 |
int MachPrologNode::reloc() const {
|
|
917 |
// Return number of relocatable values contained in this instruction. |
|
918 |
return 1; // One reloc entry for load_const(toc). |
|
919 |
} |
|
920 |
||
921 |
//============================================================================= |
|
922 |
||
923 |
#if !defined(PRODUCT) |
|
924 |
void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
|
|
925 |
os->print_cr("epilog");
|
|
926 |
os->print("\t");
|
|
927 |
if (do_polling() && ra_->C->is_method_compilation()) {
|
|
928 |
os->print_cr("load_from_polling_page Z_R1_scratch");
|
|
929 |
os->print("\t");
|
|
930 |
} |
|
931 |
} |
|
932 |
#endif |
|
933 |
||
934 |
void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
935 |
MacroAssembler _masm(&cbuf); |
|
936 |
Compile* C = ra_->C; |
|
937 |
__ verify_thread(); |
|
938 |
||
939 |
// If this does safepoint polling, then do it here. |
|
940 |
bool need_polling = do_polling() && C->is_method_compilation(); |
|
941 |
||
942 |
// Pop frame, restore return_pc, and all stuff needed by interpreter. |
|
943 |
int frame_size_in_bytes = Assembler::align((C->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes); |
|
|
46726
7801367e3cc9
8180659: [s390] micro-optimization in resize_frame_absolute()
lucy
parents:
46378
diff
changeset
|
944 |
__ pop_frame_restore_retPC(frame_size_in_bytes); |
| 42065 | 945 |
|
|
43420
a056d6465ef9
8172049: [s390] Implement "JEP 270: Reserved Stack Areas for Critical Sections".
goetz
parents:
42897
diff
changeset
|
946 |
if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
|
|
a056d6465ef9
8172049: [s390] Implement "JEP 270: Reserved Stack Areas for Critical Sections".
goetz
parents:
42897
diff
changeset
|
947 |
__ reserved_stack_check(Z_R14); |
|
a056d6465ef9
8172049: [s390] Implement "JEP 270: Reserved Stack Areas for Critical Sections".
goetz
parents:
42897
diff
changeset
|
948 |
} |
|
a056d6465ef9
8172049: [s390] Implement "JEP 270: Reserved Stack Areas for Critical Sections".
goetz
parents:
42897
diff
changeset
|
949 |
|
|
a056d6465ef9
8172049: [s390] Implement "JEP 270: Reserved Stack Areas for Critical Sections".
goetz
parents:
42897
diff
changeset
|
950 |
// Touch the polling page. |
| 42065 | 951 |
if (need_polling) {
|
|
48332
651a95f30dfb
8193257: PPC64, s390 implementation for Thread-local handshakes
mdoerr
parents:
48094
diff
changeset
|
952 |
if (SafepointMechanism::uses_thread_local_poll()) {
|
|
651a95f30dfb
8193257: PPC64, s390 implementation for Thread-local handshakes
mdoerr
parents:
48094
diff
changeset
|
953 |
__ z_lg(Z_R1_scratch, Address(Z_thread, Thread::polling_page_offset())); |
|
651a95f30dfb
8193257: PPC64, s390 implementation for Thread-local handshakes
mdoerr
parents:
48094
diff
changeset
|
954 |
} else {
|
|
651a95f30dfb
8193257: PPC64, s390 implementation for Thread-local handshakes
mdoerr
parents:
48094
diff
changeset
|
955 |
AddressLiteral pp(os::get_polling_page()); |
|
651a95f30dfb
8193257: PPC64, s390 implementation for Thread-local handshakes
mdoerr
parents:
48094
diff
changeset
|
956 |
__ load_const_optimized(Z_R1_scratch, pp); |
|
651a95f30dfb
8193257: PPC64, s390 implementation for Thread-local handshakes
mdoerr
parents:
48094
diff
changeset
|
957 |
} |
| 42065 | 958 |
// We need to mark the code position where the load from the safepoint |
959 |
// polling page was emitted as relocInfo::poll_return_type here. |
|
960 |
__ relocate(relocInfo::poll_return_type); |
|
961 |
__ load_from_polling_page(Z_R1_scratch); |
|
962 |
} |
|
963 |
} |
|
964 |
||
965 |
uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
|
|
|
43420
a056d6465ef9
8172049: [s390] Implement "JEP 270: Reserved Stack Areas for Critical Sections".
goetz
parents:
42897
diff
changeset
|
966 |
// Variable size. determine dynamically. |
| 42065 | 967 |
return MachNode::size(ra_); |
968 |
} |
|
969 |
||
970 |
int MachEpilogNode::reloc() const {
|
|
971 |
// Return number of relocatable values contained in this instruction. |
|
972 |
return 1; // One for load_from_polling_page. |
|
973 |
} |
|
974 |
||
975 |
const Pipeline * MachEpilogNode::pipeline() const {
|
|
976 |
return MachNode::pipeline_class(); |
|
977 |
} |
|
978 |
||
979 |
int MachEpilogNode::safepoint_offset() const {
|
|
980 |
assert(do_polling(), "no return for this epilog node"); |
|
981 |
return 0; |
|
982 |
} |
|
983 |
||
984 |
//============================================================================= |
|
985 |
||
986 |
// Figure out which register class each belongs in: rc_int, rc_float, rc_stack. |
|
987 |
enum RC { rc_bad, rc_int, rc_float, rc_stack };
|
|
988 |
||
989 |
static enum RC rc_class(OptoReg::Name reg) {
|
|
990 |
// Return the register class for the given register. The given register |
|
991 |
// reg is a <register>_num value, which is an index into the MachRegisterNumbers |
|
992 |
// enumeration in adGlobals_s390.hpp. |
|
993 |
||
994 |
if (reg == OptoReg::Bad) {
|
|
995 |
return rc_bad; |
|
996 |
} |
|
997 |
||
998 |
// We have 32 integer register halves, starting at index 0. |
|
999 |
if (reg < 32) {
|
|
1000 |
return rc_int; |
|
1001 |
} |
|
1002 |
||
1003 |
// We have 32 floating-point register halves, starting at index 32. |
|
1004 |
if (reg < 32+32) {
|
|
1005 |
return rc_float; |
|
1006 |
} |
|
1007 |
||
1008 |
// Between float regs & stack are the flags regs. |
|
1009 |
assert(reg >= OptoReg::stack0(), "blow up if spilling flags"); |
|
1010 |
return rc_stack; |
|
1011 |
} |
|
1012 |
||
1013 |
// Returns size as obtained from z_emit_instr. |
|
1014 |
static unsigned int z_ld_st_helper(CodeBuffer *cbuf, const char *op_str, unsigned long opcode, |
|
1015 |
int reg, int offset, bool do_print, outputStream *os) {
|
|
1016 |
||
1017 |
if (cbuf) {
|
|
1018 |
if (opcode > (1L<<32)) {
|
|
1019 |
return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) | |
|
1020 |
Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48)); |
|
1021 |
} else {
|
|
1022 |
return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) | |
|
1023 |
Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32)); |
|
1024 |
} |
|
1025 |
} |
|
1026 |
||
1027 |
#if !defined(PRODUCT) |
|
1028 |
if (do_print) {
|
|
1029 |
os->print("%s %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset);
|
|
1030 |
} |
|
1031 |
#endif |
|
1032 |
return (opcode > (1L << 32)) ? 6 : 4; |
|
1033 |
} |
|
1034 |
||
1035 |
static unsigned int z_mvc_helper(CodeBuffer *cbuf, int len, int dst_off, int src_off, bool do_print, outputStream *os) {
|
|
1036 |
if (cbuf) {
|
|
1037 |
MacroAssembler _masm(cbuf); |
|
1038 |
__ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP); |
|
1039 |
} |
|
1040 |
||
1041 |
#if !defined(PRODUCT) |
|
1042 |
else if (do_print) {
|
|
1043 |
os->print("MVC %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off);
|
|
1044 |
} |
|
1045 |
#endif |
|
1046 |
||
1047 |
return 6; |
|
1048 |
} |
|
1049 |
||
1050 |
uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const {
|
|
1051 |
// Get registers to move. |
|
1052 |
OptoReg::Name src_hi = ra_->get_reg_second(in(1)); |
|
1053 |
OptoReg::Name src_lo = ra_->get_reg_first(in(1)); |
|
1054 |
OptoReg::Name dst_hi = ra_->get_reg_second(this); |
|
1055 |
OptoReg::Name dst_lo = ra_->get_reg_first(this); |
|
1056 |
||
1057 |
enum RC src_hi_rc = rc_class(src_hi); |
|
1058 |
enum RC src_lo_rc = rc_class(src_lo); |
|
1059 |
enum RC dst_hi_rc = rc_class(dst_hi); |
|
1060 |
enum RC dst_lo_rc = rc_class(dst_lo); |
|
1061 |
||
1062 |
assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); |
|
1063 |
bool is64 = (src_hi_rc != rc_bad); |
|
1064 |
assert(!is64 || |
|
1065 |
((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi), |
|
1066 |
"expected aligned-adjacent pairs"); |
|
1067 |
||
1068 |
// Generate spill code! |
|
1069 |
||
1070 |
if (src_lo == dst_lo && src_hi == dst_hi) {
|
|
1071 |
return 0; // Self copy, no move. |
|
1072 |
} |
|
1073 |
||
1074 |
int src_offset = ra_->reg2offset(src_lo); |
|
1075 |
int dst_offset = ra_->reg2offset(dst_lo); |
|
1076 |
bool print = !do_size; |
|
1077 |
bool src12 = Immediate::is_uimm12(src_offset); |
|
1078 |
bool dst12 = Immediate::is_uimm12(dst_offset); |
|
1079 |
||
1080 |
const char *mnemo = NULL; |
|
1081 |
unsigned long opc = 0; |
|
1082 |
||
1083 |
// Memory->Memory Spill. Use Z_R0 to hold the value. |
|
1084 |
if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
|
|
1085 |
||
1086 |
assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack), |
|
1087 |
"expected same type of move for high parts"); |
|
1088 |
||
1089 |
if (src12 && dst12) {
|
|
1090 |
return z_mvc_helper(cbuf, is64 ? 8 : 4, dst_offset, src_offset, print, os); |
|
1091 |
} |
|
1092 |
||
1093 |
int r0 = Z_R0_num; |
|
1094 |
if (is64) {
|
|
1095 |
return z_ld_st_helper(cbuf, "LG ", LG_ZOPC, r0, src_offset, print, os) + |
|
1096 |
z_ld_st_helper(cbuf, "STG ", STG_ZOPC, r0, dst_offset, print, os); |
|
1097 |
} |
|
1098 |
||
1099 |
return z_ld_st_helper(cbuf, "LY ", LY_ZOPC, r0, src_offset, print, os) + |
|
1100 |
z_ld_st_helper(cbuf, "STY ", STY_ZOPC, r0, dst_offset, print, os); |
|
1101 |
} |
|
1102 |
||
1103 |
// Check for float->int copy. Requires a trip through memory. |
|
1104 |
if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
|
|
1105 |
Unimplemented(); // Unsafe, do not remove! |
|
1106 |
} |
|
1107 |
||
1108 |
// Check for integer reg-reg copy. |
|
1109 |
if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
|
|
1110 |
if (cbuf) {
|
|
1111 |
MacroAssembler _masm(cbuf); |
|
1112 |
Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); |
|
1113 |
Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); |
|
1114 |
__ z_lgr(Rdst, Rsrc); |
|
1115 |
return 4; |
|
1116 |
} |
|
1117 |
#if !defined(PRODUCT) |
|
1118 |
// else |
|
1119 |
if (print) {
|
|
1120 |
os->print("LGR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
|
|
1121 |
} |
|
1122 |
#endif |
|
1123 |
return 4; |
|
1124 |
} |
|
1125 |
||
1126 |
// Check for integer store. |
|
1127 |
if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
|
|
1128 |
assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack), |
|
1129 |
"expected same type of move for high parts"); |
|
1130 |
||
1131 |
if (is64) {
|
|
1132 |
return z_ld_st_helper(cbuf, "STG ", STG_ZOPC, src_lo, dst_offset, print, os); |
|
1133 |
} |
|
1134 |
||
1135 |
// else |
|
1136 |
mnemo = dst12 ? "ST " : "STY "; |
|
1137 |
opc = dst12 ? ST_ZOPC : STY_ZOPC; |
|
1138 |
||
1139 |
return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); |
|
1140 |
} |
|
1141 |
||
1142 |
// Check for integer load |
|
1143 |
// Always load cOops zero-extended. That doesn't hurt int loads. |
|
1144 |
if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
|
|
1145 |
||
1146 |
assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack), |
|
1147 |
"expected same type of move for high parts"); |
|
1148 |
||
1149 |
mnemo = is64 ? "LG " : "LLGF"; |
|
1150 |
opc = is64 ? LG_ZOPC : LLGF_ZOPC; |
|
1151 |
||
1152 |
return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); |
|
1153 |
} |
|
1154 |
||
1155 |
// Check for float reg-reg copy. |
|
1156 |
if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
|
|
1157 |
if (cbuf) {
|
|
1158 |
MacroAssembler _masm(cbuf); |
|
1159 |
FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); |
|
1160 |
FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); |
|
1161 |
__ z_ldr(Rdst, Rsrc); |
|
1162 |
return 2; |
|
1163 |
} |
|
1164 |
#if !defined(PRODUCT) |
|
1165 |
// else |
|
1166 |
if (print) {
|
|
1167 |
os->print("LDR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
|
|
1168 |
} |
|
1169 |
#endif |
|
1170 |
return 2; |
|
1171 |
} |
|
1172 |
||
1173 |
// Check for float store. |
|
1174 |
if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
|
|
1175 |
assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack), |
|
1176 |
"expected same type of move for high parts"); |
|
1177 |
||
1178 |
if (is64) {
|
|
1179 |
mnemo = dst12 ? "STD " : "STDY "; |
|
1180 |
opc = dst12 ? STD_ZOPC : STDY_ZOPC; |
|
1181 |
return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); |
|
1182 |
} |
|
1183 |
// else |
|
1184 |
||
1185 |
mnemo = dst12 ? "STE " : "STEY "; |
|
1186 |
opc = dst12 ? STE_ZOPC : STEY_ZOPC; |
|
1187 |
return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); |
|
1188 |
} |
|
1189 |
||
1190 |
// Check for float load. |
|
1191 |
if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
|
|
1192 |
assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack), |
|
1193 |
"expected same type of move for high parts"); |
|
1194 |
||
1195 |
if (is64) {
|
|
1196 |
mnemo = src12 ? "LD " : "LDY "; |
|
1197 |
opc = src12 ? LD_ZOPC : LDY_ZOPC; |
|
1198 |
return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); |
|
1199 |
} |
|
1200 |
// else |
|
1201 |
||
1202 |
mnemo = src12 ? "LE " : "LEY "; |
|
1203 |
opc = src12 ? LE_ZOPC : LEY_ZOPC; |
|
1204 |
return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); |
|
1205 |
} |
|
1206 |
||
1207 |
// -------------------------------------------------------------------- |
|
1208 |
// Check for hi bits still needing moving. Only happens for misaligned |
|
1209 |
// arguments to native calls. |
|
1210 |
if (src_hi == dst_hi) {
|
|
1211 |
return 0; // Self copy, no move. |
|
1212 |
} |
|
1213 |
||
1214 |
assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); |
|
1215 |
Unimplemented(); // Unsafe, do not remove! |
|
1216 |
||
1217 |
return 0; // never reached, but make the compiler shut up! |
|
1218 |
} |
|
1219 |
||
1220 |
#if !defined(PRODUCT) |
|
1221 |
void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
|
|
1222 |
if (ra_ && ra_->node_regs_max_index() > 0) {
|
|
1223 |
implementation(NULL, ra_, false, os); |
|
1224 |
} else {
|
|
1225 |
if (req() == 2 && in(1)) {
|
|
1226 |
os->print("N%d = N%d\n", _idx, in(1)->_idx);
|
|
1227 |
} else {
|
|
1228 |
const char *c = "(";
|
|
1229 |
os->print("N%d = ", _idx);
|
|
1230 |
for (uint i = 1; i < req(); ++i) {
|
|
1231 |
os->print("%sN%d", c, in(i)->_idx);
|
|
1232 |
c = ", "; |
|
1233 |
} |
|
1234 |
os->print(")");
|
|
1235 |
} |
|
1236 |
} |
|
1237 |
} |
|
1238 |
#endif |
|
1239 |
||
1240 |
void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
1241 |
implementation(&cbuf, ra_, false, NULL); |
|
1242 |
} |
|
1243 |
||
1244 |
uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
|
|
1245 |
return implementation(NULL, ra_, true, NULL); |
|
1246 |
} |
|
1247 |
||
1248 |
//============================================================================= |
|
1249 |
||
1250 |
#if !defined(PRODUCT) |
|
1251 |
void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const {
|
|
1252 |
os->print("NOP # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size());
|
|
1253 |
} |
|
1254 |
#endif |
|
1255 |
||
1256 |
void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ra_) const {
|
|
1257 |
MacroAssembler _masm(&cbuf); |
|
1258 |
||
1259 |
int rem_space = 0; |
|
1260 |
if (!(ra_->C->in_scratch_emit_size())) {
|
|
1261 |
rem_space = cbuf.insts()->remaining(); |
|
1262 |
if (rem_space <= _count*2 + 8) {
|
|
1263 |
tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space);
|
|
1264 |
} |
|
1265 |
} |
|
1266 |
||
1267 |
for (int i = 0; i < _count; i++) {
|
|
1268 |
__ z_nop(); |
|
1269 |
} |
|
1270 |
||
1271 |
if (!(ra_->C->in_scratch_emit_size())) {
|
|
1272 |
if (rem_space <= _count*2 + 8) {
|
|
1273 |
int rem_space2 = cbuf.insts()->remaining(); |
|
1274 |
tty->print_cr(", after = %d", rem_space2);
|
|
1275 |
} |
|
1276 |
} |
|
1277 |
} |
|
1278 |
||
1279 |
uint MachNopNode::size(PhaseRegAlloc *ra_) const {
|
|
1280 |
return 2 * _count; |
|
1281 |
} |
|
1282 |
||
1283 |
#if !defined(PRODUCT) |
|
1284 |
void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
|
|
1285 |
int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); |
|
1286 |
if (ra_ && ra_->node_regs_max_index() > 0) {
|
|
1287 |
int reg = ra_->get_reg_first(this); |
|
1288 |
os->print("ADDHI %s, SP, %d\t//box node", Matcher::regName[reg], offset);
|
|
1289 |
} else {
|
|
1290 |
os->print("ADDHI N%d = SP + %d\t// box node", _idx, offset);
|
|
1291 |
} |
|
1292 |
} |
|
1293 |
#endif |
|
1294 |
||
1295 |
// Take care of the size function, if you make changes here! |
|
1296 |
void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
1297 |
MacroAssembler _masm(&cbuf); |
|
1298 |
||
1299 |
int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); |
|
1300 |
int reg = ra_->get_encode(this); |
|
1301 |
__ z_lay(as_Register(reg), offset, Z_SP); |
|
1302 |
} |
|
1303 |
||
1304 |
uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
|
|
1305 |
// BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) |
|
1306 |
return 6; |
|
1307 |
} |
|
1308 |
||
1309 |
%} // end source section |
|
1310 |
||
1311 |
//----------SOURCE BLOCK------------------------------------------------------- |
|
1312 |
// This is a block of C++ code which provides values, functions, and |
|
1313 |
// definitions necessary in the rest of the architecture description |
|
1314 |
||
1315 |
source_hpp %{
|
|
1316 |
||
1317 |
// Header information of the source block. |
|
1318 |
// Method declarations/definitions which are used outside |
|
1319 |
// the ad-scope can conveniently be defined here. |
|
1320 |
// |
|
1321 |
// To keep related declarations/definitions/uses close together, |
|
1322 |
// we switch between source %{ }% and source_hpp %{ }% freely as needed.
|
|
1323 |
||
1324 |
//-------------------------------------------------------------- |
|
1325 |
// Used for optimization in Compile::Shorten_branches |
|
1326 |
//-------------------------------------------------------------- |
|
1327 |
||
1328 |
class CallStubImpl {
|
|
1329 |
public: |
|
1330 |
||
1331 |
// call trampolines |
|
1332 |
// Size of call trampoline stub. For add'l comments, see size_java_to_interp(). |
|
1333 |
static uint size_call_trampoline() {
|
|
1334 |
return 0; // no call trampolines on this platform |
|
1335 |
} |
|
1336 |
||
1337 |
// call trampolines |
|
1338 |
// Number of relocations needed by a call trampoline stub. |
|
1339 |
static uint reloc_call_trampoline() {
|
|
1340 |
return 0; // No call trampolines on this platform. |
|
1341 |
} |
|
1342 |
}; |
|
1343 |
||
1344 |
%} // end source_hpp section |
|
1345 |
||
1346 |
source %{
|
|
1347 |
||
1348 |
#if !defined(PRODUCT) |
|
1349 |
void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
|
|
1350 |
os->print_cr("---- MachUEPNode ----");
|
|
1351 |
os->print_cr("\tTA");
|
|
1352 |
os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()");
|
|
1353 |
os->print_cr("\tBR(Z_R1)");
|
|
1354 |
os->print_cr("\tTA # pad with illtraps");
|
|
1355 |
os->print_cr("\t...");
|
|
1356 |
os->print_cr("\tTA");
|
|
1357 |
os->print_cr("\tLTGR Z_R2, Z_R2");
|
|
1358 |
os->print_cr("\tBRU ic_miss");
|
|
1359 |
} |
|
1360 |
#endif |
|
1361 |
||
1362 |
void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
1363 |
MacroAssembler _masm(&cbuf); |
|
1364 |
const int ic_miss_offset = 2; |
|
1365 |
||
1366 |
// Inline_cache contains a klass. |
|
1367 |
Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); |
|
1368 |
// ARG1 is the receiver oop. |
|
1369 |
Register R2_receiver = Z_ARG1; |
|
1370 |
int klass_offset = oopDesc::klass_offset_in_bytes(); |
|
1371 |
AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub()); |
|
1372 |
Register R1_ic_miss_stub_addr = Z_R1_scratch; |
|
1373 |
||
1374 |
// Null check of receiver. |
|
1375 |
// This is the null check of the receiver that actually should be |
|
1376 |
// done in the caller. It's here because in case of implicit null |
|
1377 |
// checks we get it for free. |
|
1378 |
assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()), |
|
1379 |
"second word in oop should not require explicit null check."); |
|
1380 |
if (!ImplicitNullChecks) {
|
|
1381 |
Label valid; |
|
1382 |
if (VM_Version::has_CompareBranch()) {
|
|
1383 |
__ z_cgij(R2_receiver, 0, Assembler::bcondNotEqual, valid); |
|
1384 |
} else {
|
|
1385 |
__ z_ltgr(R2_receiver, R2_receiver); |
|
1386 |
__ z_bre(valid); |
|
1387 |
} |
|
1388 |
// The ic_miss_stub will handle the null pointer exception. |
|
1389 |
__ load_const_optimized(R1_ic_miss_stub_addr, icmiss); |
|
1390 |
__ z_br(R1_ic_miss_stub_addr); |
|
1391 |
__ bind(valid); |
|
1392 |
} |
|
1393 |
||
1394 |
// Check whether this method is the proper implementation for the class of |
|
1395 |
// the receiver (ic miss check). |
|
1396 |
{
|
|
1397 |
Label valid; |
|
1398 |
// Compare cached class against klass from receiver. |
|
1399 |
// This also does an implicit null check! |
|
1400 |
__ compare_klass_ptr(ic_klass, klass_offset, R2_receiver, false); |
|
1401 |
__ z_bre(valid); |
|
1402 |
// The inline cache points to the wrong method. Call the |
|
1403 |
// ic_miss_stub to find the proper method. |
|
1404 |
__ load_const_optimized(R1_ic_miss_stub_addr, icmiss); |
|
1405 |
__ z_br(R1_ic_miss_stub_addr); |
|
1406 |
__ bind(valid); |
|
1407 |
} |
|
1408 |
} |
|
1409 |
||
1410 |
uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
|
|
1411 |
// Determine size dynamically. |
|
1412 |
return MachNode::size(ra_); |
|
1413 |
} |
|
1414 |
||
1415 |
//============================================================================= |
|
1416 |
||
1417 |
%} // interrupt source section |
|
1418 |
||
1419 |
source_hpp %{ // Header information of the source block.
|
|
1420 |
||
1421 |
class HandlerImpl {
|
|
1422 |
public: |
|
1423 |
||
1424 |
static int emit_exception_handler(CodeBuffer &cbuf); |
|
1425 |
static int emit_deopt_handler(CodeBuffer& cbuf); |
|
1426 |
||
1427 |
static uint size_exception_handler() {
|
|
1428 |
return NativeJump::max_instruction_size(); |
|
1429 |
} |
|
1430 |
||
1431 |
static uint size_deopt_handler() {
|
|
1432 |
return NativeCall::max_instruction_size(); |
|
1433 |
} |
|
1434 |
}; |
|
1435 |
||
1436 |
%} // end source_hpp section |
|
1437 |
||
1438 |
source %{
|
|
1439 |
||
1440 |
// This exception handler code snippet is placed after the method's |
|
1441 |
// code. It is the return point if an exception occurred. it jumps to |
|
1442 |
// the exception blob. |
|
1443 |
// |
|
1444 |
// If the method gets deoptimized, the method and this code snippet |
|
1445 |
// get patched. |
|
1446 |
// |
|
1447 |
// 1) Trampoline code gets patched into the end of this exception |
|
1448 |
// handler. the trampoline code jumps to the deoptimization blob. |
|
1449 |
// |
|
1450 |
// 2) The return address in the method's code will get patched such |
|
1451 |
// that it jumps to the trampoline. |
|
1452 |
// |
|
1453 |
// 3) The handler will get patched such that it does not jump to the |
|
1454 |
// exception blob, but to an entry in the deoptimization blob being |
|
1455 |
// aware of the exception. |
|
1456 |
int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
|
|
1457 |
Register temp_reg = Z_R1; |
|
1458 |
MacroAssembler _masm(&cbuf); |
|
1459 |
||
1460 |
address base = __ start_a_stub(size_exception_handler()); |
|
1461 |
if (base == NULL) {
|
|
1462 |
return 0; // CodeBuffer::expand failed |
|
1463 |
} |
|
1464 |
||
1465 |
int offset = __ offset(); |
|
1466 |
// Use unconditional pc-relative jump with 32-bit range here. |
|
1467 |
__ load_const_optimized(temp_reg, (address)OptoRuntime::exception_blob()->content_begin()); |
|
1468 |
__ z_br(temp_reg); |
|
1469 |
||
1470 |
assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
|
1471 |
||
1472 |
__ end_a_stub(); |
|
1473 |
||
1474 |
return offset; |
|
1475 |
} |
|
1476 |
||
1477 |
// Emit deopt handler code. |
|
1478 |
int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
|
|
1479 |
MacroAssembler _masm(&cbuf); |
|
1480 |
address base = __ start_a_stub(size_deopt_handler()); |
|
1481 |
||
1482 |
if (base == NULL) {
|
|
1483 |
return 0; // CodeBuffer::expand failed |
|
1484 |
} |
|
1485 |
||
1486 |
int offset = __ offset(); |
|
1487 |
||
1488 |
// Size_deopt_handler() must be exact on zarch, so for simplicity |
|
1489 |
// we do not use load_const_opt here. |
|
1490 |
__ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack()); |
|
1491 |
__ call(Z_R1); |
|
1492 |
assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); |
|
1493 |
||
1494 |
__ end_a_stub(); |
|
1495 |
return offset; |
|
1496 |
} |
|
1497 |
||
1498 |
//============================================================================= |
|
1499 |
||
1500 |
||
1501 |
// Given a register encoding, produce an Integer Register object. |
|
1502 |
static Register reg_to_register_object(int register_encoding) {
|
|
1503 |
assert(Z_R12->encoding() == Z_R12_enc, "wrong coding"); |
|
1504 |
return as_Register(register_encoding); |
|
1505 |
} |
|
1506 |
||
1507 |
const bool Matcher::match_rule_supported(int opcode) {
|
|
1508 |
if (!has_match_rule(opcode)) return false; |
|
1509 |
||
1510 |
switch (opcode) {
|
|
1511 |
case Op_CountLeadingZerosI: |
|
1512 |
case Op_CountLeadingZerosL: |
|
1513 |
case Op_CountTrailingZerosI: |
|
1514 |
case Op_CountTrailingZerosL: |
|
|
42556
c03d98321ad1
8169317: [s390] Various minor bug fixes and adaptions.
goetz
parents:
42065
diff
changeset
|
1515 |
// Implementation requires FLOGR instruction, which is available since z9. |
|
c03d98321ad1
8169317: [s390] Various minor bug fixes and adaptions.
goetz
parents:
42065
diff
changeset
|
1516 |
return true; |
| 42065 | 1517 |
|
1518 |
case Op_ReverseBytesI: |
|
1519 |
case Op_ReverseBytesL: |
|
1520 |
return UseByteReverseInstruction; |
|
1521 |
||
1522 |
// PopCount supported by H/W from z/Architecture G5 (z196) on. |
|
1523 |
case Op_PopCountI: |
|
1524 |
case Op_PopCountL: |
|
1525 |
return UsePopCountInstruction && VM_Version::has_PopCount(); |
|
1526 |
||
1527 |
case Op_StrComp: |
|
1528 |
return SpecialStringCompareTo; |
|
1529 |
case Op_StrEquals: |
|
1530 |
return SpecialStringEquals; |
|
1531 |
case Op_StrIndexOf: |
|
1532 |
case Op_StrIndexOfChar: |
|
1533 |
return SpecialStringIndexOf; |
|
1534 |
||
1535 |
case Op_GetAndAddI: |
|
1536 |
case Op_GetAndAddL: |
|
1537 |
return true; |
|
1538 |
// return VM_Version::has_AtomicMemWithImmALUOps(); |
|
1539 |
case Op_GetAndSetI: |
|
1540 |
case Op_GetAndSetL: |
|
1541 |
case Op_GetAndSetP: |
|
1542 |
case Op_GetAndSetN: |
|
1543 |
return true; // General CAS implementation, always available. |
|
1544 |
||
1545 |
default: |
|
1546 |
return true; // Per default match rules are supported. |
|
1547 |
// BUT: make sure match rule is not disabled by a false predicate! |
|
1548 |
} |
|
1549 |
||
1550 |
return true; // Per default match rules are supported. |
|
1551 |
// BUT: make sure match rule is not disabled by a false predicate! |
|
1552 |
} |
|
1553 |
||
1554 |
const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
|
|
1555 |
// TODO |
|
1556 |
// Identify extra cases that we might want to provide match rules for |
|
1557 |
// e.g. Op_ vector nodes and other intrinsics while guarding with vlen. |
|
1558 |
bool ret_value = match_rule_supported(opcode); |
|
1559 |
// Add rules here. |
|
1560 |
||
1561 |
return ret_value; // Per default match rules are supported. |
|
1562 |
} |
|
1563 |
||
1564 |
int Matcher::regnum_to_fpu_offset(int regnum) {
|
|
1565 |
ShouldNotReachHere(); |
|
1566 |
return regnum - 32; // The FP registers are in the second chunk. |
|
1567 |
} |
|
1568 |
||
1569 |
const bool Matcher::has_predicated_vectors(void) {
|
|
1570 |
return false; |
|
1571 |
} |
|
1572 |
||
1573 |
const int Matcher::float_pressure(int default_pressure_threshold) {
|
|
1574 |
return default_pressure_threshold; |
|
1575 |
} |
|
1576 |
||
1577 |
const bool Matcher::convL2FSupported(void) {
|
|
1578 |
return true; // False means that conversion is done by runtime call. |
|
1579 |
} |
|
1580 |
||
1581 |
//----------SUPERWORD HELPERS---------------------------------------- |
|
1582 |
||
1583 |
// Vector width in bytes. |
|
1584 |
const int Matcher::vector_width_in_bytes(BasicType bt) {
|
|
1585 |
assert(MaxVectorSize == 8, ""); |
|
1586 |
return 8; |
|
1587 |
} |
|
1588 |
||
1589 |
// Vector ideal reg. |
|
| 46378 | 1590 |
const uint Matcher::vector_ideal_reg(int size) {
|
| 42065 | 1591 |
assert(MaxVectorSize == 8 && size == 8, ""); |
1592 |
return Op_RegL; |
|
1593 |
} |
|
1594 |
||
1595 |
// Limits on vector size (number of elements) loaded into vector. |
|
1596 |
const int Matcher::max_vector_size(const BasicType bt) {
|
|
1597 |
assert(is_java_primitive(bt), "only primitive type vectors"); |
|
1598 |
return vector_width_in_bytes(bt)/type2aelembytes(bt); |
|
1599 |
} |
|
1600 |
||
1601 |
const int Matcher::min_vector_size(const BasicType bt) {
|
|
1602 |
return max_vector_size(bt); // Same as max. |
|
1603 |
} |
|
1604 |
||
| 46378 | 1605 |
const uint Matcher::vector_shift_count_ideal_reg(int size) {
|
| 42065 | 1606 |
fatal("vector shift is not supported");
|
1607 |
return Node::NotAMachineReg; |
|
1608 |
} |
|
1609 |
||
1610 |
// z/Architecture does support misaligned store/load at minimal extra cost. |
|
1611 |
const bool Matcher::misaligned_vectors_ok() {
|
|
1612 |
return true; |
|
1613 |
} |
|
1614 |
||
1615 |
// Not yet ported to z/Architecture. |
|
1616 |
const bool Matcher::pass_original_key_for_aes() {
|
|
1617 |
return false; |
|
1618 |
} |
|
1619 |
||
1620 |
// RETURNS: whether this branch offset is short enough that a short |
|
1621 |
// branch can be used. |
|
1622 |
// |
|
1623 |
// If the platform does not provide any short branch variants, then |
|
1624 |
// this method should return `false' for offset 0. |
|
1625 |
// |
|
1626 |
// `Compile::Fill_buffer' will decide on basis of this information |
|
1627 |
// whether to do the pass `Compile::Shorten_branches' at all. |
|
1628 |
// |
|
1629 |
// And `Compile::Shorten_branches' will decide on basis of this |
|
1630 |
// information whether to replace particular branch sites by short |
|
1631 |
// ones. |
|
1632 |
bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
|
|
1633 |
// On zarch short branches use a 16 bit signed immediate that |
|
1634 |
// is the pc-relative offset in halfword (= 2 bytes) units. |
|
1635 |
return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0); |
|
1636 |
} |
|
1637 |
||
1638 |
const bool Matcher::isSimpleConstant64(jlong value) {
|
|
1639 |
// Probably always true, even if a temp register is required. |
|
1640 |
return true; |
|
1641 |
} |
|
1642 |
||
1643 |
// Should correspond to setting above |
|
1644 |
const bool Matcher::init_array_count_is_in_bytes = false; |
|
1645 |
||
1646 |
// Suppress CMOVL. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet. |
|
1647 |
const int Matcher::long_cmove_cost() { return ConditionalMoveLimit; }
|
|
1648 |
||
1649 |
// Suppress CMOVF. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet. |
|
1650 |
const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
|
|
1651 |
||
1652 |
// Does the CPU require postalloc expand (see block.cpp for description of postalloc expand)? |
|
1653 |
const bool Matcher::require_postalloc_expand = false; |
|
1654 |
||
1655 |
// Do we need to mask the count passed to shift instructions or does |
|
1656 |
// the cpu only look at the lower 5/6 bits anyway? |
|
1657 |
// 32bit shifts mask in emitter, 64bit shifts need no mask. |
|
1658 |
// Constant shift counts are handled in Ideal phase. |
|
1659 |
const bool Matcher::need_masked_shift_count = false; |
|
1660 |
||
1661 |
// Set this as clone_shift_expressions. |
|
1662 |
bool Matcher::narrow_oop_use_complex_address() {
|
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
1663 |
if (CompressedOops::base() == NULL && CompressedOops::shift() == 0) return true; |
| 42065 | 1664 |
return false; |
1665 |
} |
|
1666 |
||
1667 |
bool Matcher::narrow_klass_use_complex_address() {
|
|
1668 |
NOT_LP64(ShouldNotCallThis()); |
|
1669 |
assert(UseCompressedClassPointers, "only for compressed klass code"); |
|
1670 |
// TODO HS25: z port if (MatchDecodeNodes) return true; |
|
1671 |
return false; |
|
1672 |
} |
|
1673 |
||
1674 |
bool Matcher::const_oop_prefer_decode() {
|
|
1675 |
// Prefer ConN+DecodeN over ConP in simple compressed oops mode. |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
1676 |
return CompressedOops::base() == NULL; |
| 42065 | 1677 |
} |
1678 |
||
1679 |
bool Matcher::const_klass_prefer_decode() {
|
|
1680 |
// Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode. |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
1681 |
return CompressedKlassPointers::base() == NULL; |
| 42065 | 1682 |
} |
1683 |
||
1684 |
// Is it better to copy float constants, or load them directly from memory? |
|
1685 |
// Most RISCs will have to materialize an address into a |
|
1686 |
// register first, so they would do better to copy the constant from stack. |
|
1687 |
const bool Matcher::rematerialize_float_constants = false; |
|
1688 |
||
1689 |
// If CPU can load and store mis-aligned doubles directly then no fixup is |
|
1690 |
// needed. Else we split the double into 2 integer pieces and move it |
|
1691 |
// piece-by-piece. Only happens when passing doubles into C code as the |
|
1692 |
// Java calling convention forces doubles to be aligned. |
|
1693 |
const bool Matcher::misaligned_doubles_ok = true; |
|
1694 |
||
1695 |
// Advertise here if the CPU requires explicit rounding operations |
|
1696 |
// to implement the UseStrictFP mode. |
|
1697 |
const bool Matcher::strict_fp_requires_explicit_rounding = false; |
|
1698 |
||
1699 |
// Do floats take an entire double register or just half? |
|
1700 |
// |
|
1701 |
// A float in resides in a zarch double register. When storing it by |
|
1702 |
// z_std, it cannot be restored in C-code by reloading it as a double |
|
1703 |
// and casting it into a float afterwards. |
|
1704 |
bool Matcher::float_in_double() { return false; }
|
|
1705 |
||
1706 |
// Do ints take an entire long register or just half? |
|
1707 |
// The relevant question is how the int is callee-saved: |
|
1708 |
// the whole long is written but de-opt'ing will have to extract |
|
1709 |
// the relevant 32 bits. |
|
1710 |
const bool Matcher::int_in_long = true; |
|
1711 |
||
1712 |
// Constants for c2c and c calling conventions. |
|
1713 |
||
1714 |
const MachRegisterNumbers z_iarg_reg[5] = {
|
|
1715 |
Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num |
|
1716 |
}; |
|
1717 |
||
1718 |
const MachRegisterNumbers z_farg_reg[4] = {
|
|
1719 |
Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num |
|
1720 |
}; |
|
1721 |
||
1722 |
const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]); |
|
1723 |
||
1724 |
const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]); |
|
1725 |
||
1726 |
// Return whether or not this register is ever used as an argument. This |
|
1727 |
// function is used on startup to build the trampoline stubs in generateOptoStub. |
|
1728 |
// Registers not mentioned will be killed by the VM call in the trampoline, and |
|
1729 |
// arguments in those registers not be available to the callee. |
|
1730 |
bool Matcher::can_be_java_arg(int reg) {
|
|
1731 |
// We return true for all registers contained in z_iarg_reg[] and |
|
1732 |
// z_farg_reg[] and their virtual halves. |
|
1733 |
// We must include the virtual halves in order to get STDs and LDs |
|
1734 |
// instead of STWs and LWs in the trampoline stubs. |
|
1735 |
||
1736 |
if (reg == Z_R2_num || reg == Z_R2_H_num || |
|
1737 |
reg == Z_R3_num || reg == Z_R3_H_num || |
|
1738 |
reg == Z_R4_num || reg == Z_R4_H_num || |
|
1739 |
reg == Z_R5_num || reg == Z_R5_H_num || |
|
1740 |
reg == Z_R6_num || reg == Z_R6_H_num) {
|
|
1741 |
return true; |
|
1742 |
} |
|
1743 |
||
1744 |
if (reg == Z_F0_num || reg == Z_F0_H_num || |
|
1745 |
reg == Z_F2_num || reg == Z_F2_H_num || |
|
1746 |
reg == Z_F4_num || reg == Z_F4_H_num || |
|
1747 |
reg == Z_F6_num || reg == Z_F6_H_num) {
|
|
1748 |
return true; |
|
1749 |
} |
|
1750 |
||
1751 |
return false; |
|
1752 |
} |
|
1753 |
||
1754 |
bool Matcher::is_spillable_arg(int reg) {
|
|
1755 |
return can_be_java_arg(reg); |
|
1756 |
} |
|
1757 |
||
1758 |
bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
|
|
1759 |
return false; |
|
1760 |
} |
|
1761 |
||
1762 |
// Register for DIVI projection of divmodI |
|
1763 |
RegMask Matcher::divI_proj_mask() {
|
|
1764 |
return _Z_RARG4_INT_REG_mask; |
|
1765 |
} |
|
1766 |
||
1767 |
// Register for MODI projection of divmodI |
|
1768 |
RegMask Matcher::modI_proj_mask() {
|
|
1769 |
return _Z_RARG3_INT_REG_mask; |
|
1770 |
} |
|
1771 |
||
1772 |
// Register for DIVL projection of divmodL |
|
1773 |
RegMask Matcher::divL_proj_mask() {
|
|
1774 |
return _Z_RARG4_LONG_REG_mask; |
|
1775 |
} |
|
1776 |
||
1777 |
// Register for MODL projection of divmodL |
|
1778 |
RegMask Matcher::modL_proj_mask() {
|
|
1779 |
return _Z_RARG3_LONG_REG_mask; |
|
1780 |
} |
|
1781 |
||
1782 |
// Copied from sparc. |
|
1783 |
const RegMask Matcher::method_handle_invoke_SP_save_mask() {
|
|
1784 |
return RegMask(); |
|
1785 |
} |
|
1786 |
||
1787 |
const bool Matcher::convi2l_type_required = true; |
|
1788 |
||
1789 |
// Should the Matcher clone shifts on addressing modes, expecting them |
|
1790 |
// to be subsumed into complex addressing expressions or compute them |
|
1791 |
// into registers? |
|
1792 |
bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
|
|
1793 |
return clone_base_plus_offset_address(m, mstack, address_visited); |
|
1794 |
} |
|
1795 |
||
1796 |
void Compile::reshape_address(AddPNode* addp) {
|
|
1797 |
} |
|
1798 |
||
1799 |
%} // source |
|
1800 |
||
1801 |
//----------ENCODING BLOCK----------------------------------------------------- |
|
1802 |
// This block specifies the encoding classes used by the compiler to output |
|
1803 |
// byte streams. Encoding classes are parameterized macros used by |
|
1804 |
// Machine Instruction Nodes in order to generate the bit encoding of the |
|
1805 |
// instruction. Operands specify their base encoding interface with the |
|
1806 |
// interface keyword. There are currently supported four interfaces, |
|
1807 |
// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an |
|
1808 |
// operand to generate a function which returns its register number when |
|
1809 |
// queried. CONST_INTER causes an operand to generate a function which |
|
1810 |
// returns the value of the constant when queried. MEMORY_INTER causes an |
|
1811 |
// operand to generate four functions which return the Base Register, the |
|
1812 |
// Index Register, the Scale Value, and the Offset Value of the operand when |
|
1813 |
// queried. COND_INTER causes an operand to generate six functions which |
|
1814 |
// return the encoding code (ie - encoding bits for the instruction) |
|
1815 |
// associated with each basic boolean condition for a conditional instruction. |
|
1816 |
// |
|
1817 |
// Instructions specify two basic values for encoding. Again, a function |
|
1818 |
// is available to check if the constant displacement is an oop. They use the |
|
1819 |
// ins_encode keyword to specify their encoding classes (which must be |
|
1820 |
// a sequence of enc_class names, and their parameters, specified in |
|
1821 |
// the encoding block), and they use the |
|
1822 |
// opcode keyword to specify, in order, their primary, secondary, and |
|
1823 |
// tertiary opcode. Only the opcode sections which a particular instruction |
|
1824 |
// needs for encoding need to be specified. |
|
1825 |
encode %{
|
|
1826 |
enc_class enc_unimplemented %{
|
|
1827 |
MacroAssembler _masm(&cbuf); |
|
1828 |
__ unimplemented("Unimplemented mach node encoding in AD file.", 13);
|
|
1829 |
%} |
|
1830 |
||
1831 |
enc_class enc_untested %{
|
|
1832 |
#ifdef ASSERT |
|
1833 |
MacroAssembler _masm(&cbuf); |
|
1834 |
__ untested("Untested mach node encoding in AD file.");
|
|
1835 |
#endif |
|
1836 |
%} |
|
1837 |
||
1838 |
enc_class z_rrform(iRegI dst, iRegI src) %{
|
|
1839 |
assert((($primary >> 14) & 0x03) == 0, "Instruction format error"); |
|
1840 |
assert( ($primary >> 16) == 0, "Instruction format error"); |
|
1841 |
z_emit16(cbuf, $primary | |
|
1842 |
Assembler::reg($dst$$reg,8,16) | |
|
1843 |
Assembler::reg($src$$reg,12,16)); |
|
1844 |
%} |
|
1845 |
||
1846 |
enc_class z_rreform(iRegI dst1, iRegI src2) %{
|
|
1847 |
assert((($primary >> 30) & 0x03) == 2, "Instruction format error"); |
|
1848 |
z_emit32(cbuf, $primary | |
|
1849 |
Assembler::reg($dst1$$reg,24,32) | |
|
1850 |
Assembler::reg($src2$$reg,28,32)); |
|
1851 |
%} |
|
1852 |
||
1853 |
enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{
|
|
1854 |
assert((($primary >> 30) & 0x03) == 2, "Instruction format error"); |
|
1855 |
z_emit32(cbuf, $primary | |
|
1856 |
Assembler::reg($dst1$$reg,24,32) | |
|
1857 |
Assembler::reg($src2$$reg,28,32) | |
|
1858 |
Assembler::reg($src3$$reg,16,32)); |
|
1859 |
%} |
|
1860 |
||
1861 |
enc_class z_riform_signed(iRegI dst, immI16 src) %{
|
|
1862 |
assert((($primary>>30) & 0x03) == 2, "Instruction format error"); |
|
1863 |
z_emit32(cbuf, $primary | |
|
1864 |
Assembler::reg($dst$$reg,8,32) | |
|
1865 |
Assembler::simm16($src$$constant,16,32)); |
|
1866 |
%} |
|
1867 |
||
1868 |
enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{
|
|
1869 |
assert((($primary>>30) & 0x03) == 2, "Instruction format error"); |
|
1870 |
z_emit32(cbuf, $primary | |
|
1871 |
Assembler::reg($dst$$reg,8,32) | |
|
1872 |
Assembler::uimm16($src$$constant,16,32)); |
|
1873 |
%} |
|
1874 |
||
1875 |
enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{
|
|
1876 |
assert((($primary>>46) & 0x03) == 3, "Instruction format error"); |
|
1877 |
z_emit48(cbuf, $primary | |
|
1878 |
Assembler::reg($dst1$$reg,8,48) | |
|
1879 |
Assembler::reg($src3$$reg,12,48) | |
|
1880 |
Assembler::simm16($src2$$constant,16,48)); |
|
1881 |
%} |
|
1882 |
||
1883 |
enc_class z_rilform_signed(iRegI dst, immL32 src) %{
|
|
1884 |
assert((($primary>>46) & 0x03) == 3, "Instruction format error"); |
|
1885 |
z_emit48(cbuf, $primary | |
|
1886 |
Assembler::reg($dst$$reg,8,48) | |
|
1887 |
Assembler::simm32($src$$constant,16,48)); |
|
1888 |
%} |
|
1889 |
||
1890 |
enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{
|
|
1891 |
assert((($primary>>46) & 0x03) == 3, "Instruction format error"); |
|
1892 |
z_emit48(cbuf, $primary | |
|
1893 |
Assembler::reg($dst$$reg,8,48) | |
|
1894 |
Assembler::uimm32($src$$constant,16,48)); |
|
1895 |
%} |
|
1896 |
||
1897 |
enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{
|
|
1898 |
z_emit48(cbuf, $primary | |
|
1899 |
Assembler::reg($dst$$reg,8,48) | |
|
1900 |
Assembler::reg($src1$$reg,12,48) | |
|
1901 |
Assembler::simm20($src2$$constant)); |
|
1902 |
%} |
|
1903 |
||
1904 |
enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{
|
|
1905 |
z_emit48(cbuf, $primary | |
|
1906 |
Assembler::reg($dst$$reg,8,48) | |
|
1907 |
Assembler::reg($src$$reg,12,48) | |
|
1908 |
Assembler::reg($shft$$reg,16,48) | |
|
1909 |
Assembler::simm20(0)); |
|
1910 |
%} |
|
1911 |
||
1912 |
enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
|
|
1913 |
assert((($primary>>30) & 0x03) == 1, "Instruction format error"); |
|
1914 |
z_emit32(cbuf, $primary | |
|
1915 |
Assembler::reg($dst$$reg,8,32) | |
|
1916 |
Assembler::reg($src1$$reg,12,32) | |
|
1917 |
Assembler::reg($src2$$reg,16,32) | |
|
1918 |
Assembler::uimm12($con$$constant,20,32)); |
|
1919 |
%} |
|
1920 |
||
1921 |
enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{
|
|
1922 |
assert((($primary>>30) & 0x03) == 1, "Instruction format error"); |
|
1923 |
z_emit32(cbuf, $primary | |
|
1924 |
Assembler::reg($dst$$reg,8,32) | |
|
1925 |
Assembler::reg($src$$reg,16,32) | |
|
1926 |
Assembler::uimm12($con$$constant,20,32)); |
|
1927 |
%} |
|
1928 |
||
1929 |
enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
|
|
1930 |
z_emit48(cbuf, $primary | |
|
1931 |
Assembler::reg($dst$$reg,8,48) | |
|
1932 |
Assembler::reg($src1$$reg,12,48) | |
|
1933 |
Assembler::reg($src2$$reg,16,48) | |
|
1934 |
Assembler::simm20($con$$constant)); |
|
1935 |
%} |
|
1936 |
||
1937 |
enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{
|
|
1938 |
z_emit48(cbuf, $primary | |
|
1939 |
Assembler::reg($dst$$reg,8,48) | |
|
1940 |
Assembler::reg($src$$reg,16,48) | |
|
1941 |
Assembler::simm20($con$$constant)); |
|
1942 |
%} |
|
1943 |
||
1944 |
// Direct memory arithmetic. |
|
1945 |
enc_class z_siyform(memoryRSY mem, immI8 src) %{
|
|
1946 |
int disp = $mem$$disp; |
|
1947 |
Register base = reg_to_register_object($mem$$base); |
|
1948 |
int con = $src$$constant; |
|
1949 |
||
1950 |
assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU"); |
|
1951 |
z_emit_inst(cbuf, $primary | |
|
1952 |
Assembler::regz(base,16,48) | |
|
1953 |
Assembler::simm20(disp) | |
|
1954 |
Assembler::simm8(con,8,48)); |
|
1955 |
%} |
|
1956 |
||
1957 |
enc_class z_silform(memoryRS mem, immI16 src) %{
|
|
1958 |
z_emit_inst(cbuf, $primary | |
|
1959 |
Assembler::regz(reg_to_register_object($mem$$base),16,48) | |
|
1960 |
Assembler::uimm12($mem$$disp,20,48) | |
|
1961 |
Assembler::simm16($src$$constant,32,48)); |
|
1962 |
%} |
|
1963 |
||
1964 |
// Encoder for FP ALU reg/mem instructions (support only short displacements). |
|
1965 |
enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{
|
|
1966 |
Register Ridx = $mem$$index$$Register; |
|
1967 |
if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
|
|
1968 |
if ($primary > (1L << 32)) {
|
|
1969 |
z_emit_inst(cbuf, $primary | |
|
1970 |
Assembler::reg($dst$$reg, 8, 48) | |
|
1971 |
Assembler::uimm12($mem$$disp, 20, 48) | |
|
1972 |
Assembler::reg(Ridx, 12, 48) | |
|
1973 |
Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); |
|
1974 |
} else {
|
|
1975 |
z_emit_inst(cbuf, $primary | |
|
1976 |
Assembler::reg($dst$$reg, 8, 32) | |
|
1977 |
Assembler::uimm12($mem$$disp, 20, 32) | |
|
1978 |
Assembler::reg(Ridx, 12, 32) | |
|
1979 |
Assembler::regz(reg_to_register_object($mem$$base), 16, 32)); |
|
1980 |
} |
|
1981 |
%} |
|
1982 |
||
1983 |
enc_class z_form_rt_mem(iRegI dst, memory mem) %{
|
|
1984 |
Register Ridx = $mem$$index$$Register; |
|
1985 |
if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
|
|
1986 |
if ($primary > (1L<<32)) {
|
|
1987 |
z_emit_inst(cbuf, $primary | |
|
1988 |
Assembler::reg($dst$$reg, 8, 48) | |
|
1989 |
Assembler::simm20($mem$$disp) | |
|
1990 |
Assembler::reg(Ridx, 12, 48) | |
|
1991 |
Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); |
|
1992 |
} else {
|
|
1993 |
z_emit_inst(cbuf, $primary | |
|
1994 |
Assembler::reg($dst$$reg, 8, 32) | |
|
1995 |
Assembler::uimm12($mem$$disp, 20, 32) | |
|
1996 |
Assembler::reg(Ridx, 12, 32) | |
|
1997 |
Assembler::regz(reg_to_register_object($mem$$base), 16, 32)); |
|
1998 |
} |
|
1999 |
%} |
|
2000 |
||
2001 |
enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{
|
|
2002 |
int isize = $secondary > 1L << 32 ? 48 : 32; |
|
2003 |
Register Ridx = $mem$$index$$Register; |
|
2004 |
if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
|
|
2005 |
||
2006 |
if (Displacement::is_shortDisp((long)$mem$$disp)) {
|
|
2007 |
z_emit_inst(cbuf, $secondary | |
|
2008 |
Assembler::reg($dst$$reg, 8, isize) | |
|
2009 |
Assembler::uimm12($mem$$disp, 20, isize) | |
|
2010 |
Assembler::reg(Ridx, 12, isize) | |
|
2011 |
Assembler::regz(reg_to_register_object($mem$$base), 16, isize)); |
|
2012 |
} else if (Displacement::is_validDisp((long)$mem$$disp)) {
|
|
2013 |
z_emit_inst(cbuf, $primary | |
|
2014 |
Assembler::reg($dst$$reg, 8, 48) | |
|
2015 |
Assembler::simm20($mem$$disp) | |
|
2016 |
Assembler::reg(Ridx, 12, 48) | |
|
2017 |
Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); |
|
2018 |
} else {
|
|
2019 |
MacroAssembler _masm(&cbuf); |
|
2020 |
__ load_const_optimized(Z_R1_scratch, $mem$$disp); |
|
2021 |
if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); }
|
|
2022 |
z_emit_inst(cbuf, $secondary | |
|
2023 |
Assembler::reg($dst$$reg, 8, isize) | |
|
2024 |
Assembler::uimm12(0, 20, isize) | |
|
2025 |
Assembler::reg(Z_R1_scratch, 12, isize) | |
|
2026 |
Assembler::regz(reg_to_register_object($mem$$base), 16, isize)); |
|
2027 |
} |
|
2028 |
%} |
|
2029 |
||
2030 |
enc_class z_enc_brul(Label lbl) %{
|
|
2031 |
MacroAssembler _masm(&cbuf); |
|
2032 |
Label* p = $lbl$$label; |
|
2033 |
||
2034 |
// 'p' is `NULL' when this encoding class is used only to |
|
2035 |
// determine the size of the encoded instruction. |
|
2036 |
// Use a bound dummy label in that case. |
|
2037 |
Label d; |
|
2038 |
__ bind(d); |
|
2039 |
Label& l = (NULL == p) ? d : *(p); |
|
2040 |
__ z_brul(l); |
|
2041 |
%} |
|
2042 |
||
2043 |
enc_class z_enc_bru(Label lbl) %{
|
|
2044 |
MacroAssembler _masm(&cbuf); |
|
2045 |
Label* p = $lbl$$label; |
|
2046 |
||
2047 |
// 'p' is `NULL' when this encoding class is used only to |
|
2048 |
// determine the size of the encoded instruction. |
|
2049 |
// Use a bound dummy label in that case. |
|
2050 |
Label d; |
|
2051 |
__ bind(d); |
|
2052 |
Label& l = (NULL == p) ? d : *(p); |
|
2053 |
__ z_bru(l); |
|
2054 |
%} |
|
2055 |
||
2056 |
enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{
|
|
2057 |
MacroAssembler _masm(&cbuf); |
|
2058 |
Label* p = $lbl$$label; |
|
2059 |
||
2060 |
// 'p' is `NULL' when this encoding class is used only to |
|
2061 |
// determine the size of the encoded instruction. |
|
2062 |
// Use a bound dummy label in that case. |
|
2063 |
Label d; |
|
2064 |
__ bind(d); |
|
2065 |
Label& l = (NULL == p) ? d : *(p); |
|
2066 |
__ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); |
|
2067 |
%} |
|
2068 |
||
2069 |
enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{
|
|
2070 |
MacroAssembler _masm(&cbuf); |
|
2071 |
Label* p = $lbl$$label; |
|
2072 |
||
2073 |
// 'p' is `NULL' when this encoding class is used only to |
|
2074 |
// determine the size of the encoded instruction. |
|
2075 |
// Use a bound dummy label in that case. |
|
2076 |
Label d; |
|
2077 |
__ bind(d); |
|
2078 |
Label& l = (NULL == p) ? d : *(p); |
|
2079 |
__ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l); |
|
2080 |
%} |
|
2081 |
||
2082 |
enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
|
|
2083 |
MacroAssembler _masm(&cbuf); |
|
2084 |
Label* p = $lbl$$label; |
|
2085 |
||
2086 |
// 'p' is `NULL' when this encoding class is used only to |
|
2087 |
// determine the size of the encoded instruction. |
|
2088 |
// Use a bound dummy label in that case. |
|
2089 |
Label d; |
|
2090 |
__ bind(d); |
|
2091 |
Label& l = (NULL == p) ? d : *(p); |
|
2092 |
Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; |
|
2093 |
unsigned long instr = $primary; |
|
2094 |
if (instr == CRJ_ZOPC) {
|
|
2095 |
__ z_crj($src1$$Register, $src2$$Register, cc, l); |
|
2096 |
} else if (instr == CLRJ_ZOPC) {
|
|
2097 |
__ z_clrj($src1$$Register, $src2$$Register, cc, l); |
|
2098 |
} else if (instr == CGRJ_ZOPC) {
|
|
2099 |
__ z_cgrj($src1$$Register, $src2$$Register, cc, l); |
|
2100 |
} else {
|
|
2101 |
guarantee(instr == CLGRJ_ZOPC, "opcode not implemented"); |
|
2102 |
__ z_clgrj($src1$$Register, $src2$$Register, cc, l); |
|
2103 |
} |
|
2104 |
%} |
|
2105 |
||
2106 |
enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
|
|
2107 |
MacroAssembler _masm(&cbuf); |
|
2108 |
Label* p = $lbl$$label; |
|
2109 |
||
2110 |
// 'p' is `NULL' when this encoding class is used only to |
|
2111 |
// determine the size of the encoded instruction. |
|
2112 |
// Use a bound dummy label in that case. |
|
2113 |
Label d; |
|
2114 |
__ bind(d); |
|
2115 |
Label& l = (NULL == p) ? d : *(p); |
|
2116 |
||
2117 |
unsigned long instr = $primary; |
|
2118 |
if (instr == CR_ZOPC) {
|
|
2119 |
__ z_cr($src1$$Register, $src2$$Register); |
|
2120 |
} else if (instr == CLR_ZOPC) {
|
|
2121 |
__ z_clr($src1$$Register, $src2$$Register); |
|
2122 |
} else if (instr == CGR_ZOPC) {
|
|
2123 |
__ z_cgr($src1$$Register, $src2$$Register); |
|
2124 |
} else {
|
|
2125 |
guarantee(instr == CLGR_ZOPC, "opcode not implemented"); |
|
2126 |
__ z_clgr($src1$$Register, $src2$$Register); |
|
2127 |
} |
|
2128 |
||
2129 |
__ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); |
|
2130 |
%} |
|
2131 |
||
2132 |
enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
|
|
2133 |
MacroAssembler _masm(&cbuf); |
|
2134 |
Label* p = $lbl$$label; |
|
2135 |
||
2136 |
// 'p' is `NULL' when this encoding class is used only to |
|
2137 |
// determine the size of the encoded instruction. |
|
2138 |
// Use a bound dummy label in that case. |
|
2139 |
Label d; |
|
2140 |
__ bind(d); |
|
2141 |
Label& l = (NULL == p) ? d : *(p); |
|
2142 |
||
2143 |
Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; |
|
2144 |
unsigned long instr = $primary; |
|
2145 |
if (instr == CIJ_ZOPC) {
|
|
2146 |
__ z_cij($src1$$Register, $src2$$constant, cc, l); |
|
2147 |
} else if (instr == CLIJ_ZOPC) {
|
|
2148 |
__ z_clij($src1$$Register, $src2$$constant, cc, l); |
|
2149 |
} else if (instr == CGIJ_ZOPC) {
|
|
2150 |
__ z_cgij($src1$$Register, $src2$$constant, cc, l); |
|
2151 |
} else {
|
|
2152 |
guarantee(instr == CLGIJ_ZOPC, "opcode not implemented"); |
|
2153 |
__ z_clgij($src1$$Register, $src2$$constant, cc, l); |
|
2154 |
} |
|
2155 |
%} |
|
2156 |
||
2157 |
enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
|
|
2158 |
MacroAssembler _masm(&cbuf); |
|
2159 |
Label* p = $lbl$$label; |
|
2160 |
||
2161 |
// 'p' is `NULL' when this encoding class is used only to |
|
2162 |
// determine the size of the encoded instruction. |
|
2163 |
// Use a bound dummy label in that case. |
|
2164 |
Label d; |
|
2165 |
__ bind(d); |
|
2166 |
Label& l = (NULL == p) ? d : *(p); |
|
2167 |
||
2168 |
unsigned long instr = $primary; |
|
2169 |
if (instr == CHI_ZOPC) {
|
|
2170 |
__ z_chi($src1$$Register, $src2$$constant); |
|
2171 |
} else if (instr == CLFI_ZOPC) {
|
|
2172 |
__ z_clfi($src1$$Register, $src2$$constant); |
|
2173 |
} else if (instr == CGHI_ZOPC) {
|
|
2174 |
__ z_cghi($src1$$Register, $src2$$constant); |
|
2175 |
} else {
|
|
2176 |
guarantee(instr == CLGFI_ZOPC, "opcode not implemented"); |
|
2177 |
__ z_clgfi($src1$$Register, $src2$$constant); |
|
2178 |
} |
|
2179 |
||
2180 |
__ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); |
|
2181 |
%} |
|
2182 |
||
2183 |
// Call from Java to runtime. |
|
2184 |
enc_class z_enc_java_to_runtime_call(method meth) %{
|
|
2185 |
MacroAssembler _masm(&cbuf); |
|
2186 |
||
2187 |
// Save return pc before call to the place where we need it, since |
|
2188 |
// callee doesn't. |
|
2189 |
unsigned int start_off = __ offset(); |
|
2190 |
// Compute size of "larl + stg + call_c_opt". |
|
2191 |
const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size(); |
|
2192 |
__ get_PC(Z_R14, size_of_code); |
|
2193 |
__ save_return_pc(); |
|
2194 |
assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off); |
|
2195 |
||
2196 |
assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call"); |
|
2197 |
address call_addr = __ call_c_opt((address)$meth$$method); |
|
2198 |
if (call_addr == NULL) {
|
|
2199 |
Compile::current()->env()->record_out_of_memory_failure(); |
|
2200 |
return; |
|
2201 |
} |
|
2202 |
||
2203 |
#ifdef ASSERT |
|
2204 |
// Plausibility check for size_of_code assumptions. |
|
2205 |
unsigned int actual_ret_off = __ offset(); |
|
2206 |
assert(start_off + size_of_code == actual_ret_off, "wrong return_pc"); |
|
2207 |
#endif |
|
2208 |
%} |
|
2209 |
||
2210 |
enc_class z_enc_java_static_call(method meth) %{
|
|
2211 |
// Call to fixup routine. Fixup routine uses ScopeDesc info to determine |
|
2212 |
// whom we intended to call. |
|
2213 |
MacroAssembler _masm(&cbuf); |
|
2214 |
int ret_offset = 0; |
|
2215 |
||
2216 |
if (!_method) {
|
|
2217 |
ret_offset = emit_call_reloc(_masm, $meth$$method, |
|
2218 |
relocInfo::runtime_call_w_cp_type, ra_); |
|
2219 |
} else {
|
|
2220 |
int method_index = resolved_method_index(cbuf); |
|
2221 |
if (_optimized_virtual) {
|
|
2222 |
ret_offset = emit_call_reloc(_masm, $meth$$method, |
|
2223 |
opt_virtual_call_Relocation::spec(method_index)); |
|
2224 |
} else {
|
|
2225 |
ret_offset = emit_call_reloc(_masm, $meth$$method, |
|
2226 |
static_call_Relocation::spec(method_index)); |
|
2227 |
} |
|
2228 |
} |
|
2229 |
assert(__ inst_mark() != NULL, "emit_call_reloc must set_inst_mark()"); |
|
2230 |
||
2231 |
if (_method) { // Emit stub for static call.
|
|
2232 |
address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); |
|
2233 |
if (stub == NULL) {
|
|
2234 |
ciEnv::current()->record_failure("CodeCache is full");
|
|
2235 |
return; |
|
2236 |
} |
|
2237 |
} |
|
2238 |
%} |
|
2239 |
||
2240 |
// Java dynamic call |
|
2241 |
enc_class z_enc_java_dynamic_call(method meth) %{
|
|
2242 |
MacroAssembler _masm(&cbuf); |
|
2243 |
unsigned int start_off = __ offset(); |
|
2244 |
||
2245 |
int vtable_index = this->_vtable_index; |
|
2246 |
if (vtable_index == -4) {
|
|
2247 |
Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); |
|
2248 |
address virtual_call_oop_addr = NULL; |
|
2249 |
||
2250 |
AddressLiteral empty_ic((address) Universe::non_oop_word()); |
|
2251 |
virtual_call_oop_addr = __ pc(); |
|
2252 |
bool success = __ load_const_from_toc(ic_reg, empty_ic); |
|
2253 |
if (!success) {
|
|
2254 |
Compile::current()->env()->record_out_of_memory_failure(); |
|
2255 |
return; |
|
2256 |
} |
|
2257 |
||
2258 |
// Call to fixup routine. Fixup routine uses ScopeDesc info |
|
2259 |
// to determine who we intended to call. |
|
2260 |
int method_index = resolved_method_index(cbuf); |
|
2261 |
__ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index)); |
|
2262 |
unsigned int ret_off = __ offset(); |
|
2263 |
assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off); |
|
2264 |
ret_off += emit_call_reloc(_masm, $meth$$method, relocInfo::none, ra_); |
|
2265 |
assert(_method, "lazy_constant may be wrong when _method==null"); |
|
2266 |
} else {
|
|
2267 |
assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); |
|
2268 |
// Go through the vtable. Get receiver klass. Receiver already |
|
2269 |
// checked for non-null. If we'll go thru a C2I adapter, the |
|
2270 |
// interpreter expects method in Z_method. |
|
|
50162
f9fe56417050
8202713: Create a MacroAssembler::access_load/store_at wrapper for S390 and PPC
mdoerr
parents:
49943
diff
changeset
|
2271 |
// Use Z_method to temporarily hold the klass oop. |
|
f9fe56417050
8202713: Create a MacroAssembler::access_load/store_at wrapper for S390 and PPC
mdoerr
parents:
49943
diff
changeset
|
2272 |
// Z_R1_scratch is destroyed. |
| 42065 | 2273 |
__ load_klass(Z_method, Z_R2); |
2274 |
||
2275 |
int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes(); |
|
2276 |
int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); |
|
2277 |
||
2278 |
if (Displacement::is_validDisp(v_off) ) {
|
|
2279 |
// Can use load instruction with large offset. |
|
2280 |
__ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/)); |
|
2281 |
} else {
|
|
2282 |
// Worse case, must load offset into register. |
|
2283 |
__ load_const(Z_R1_scratch, v_off); |
|
2284 |
__ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/)); |
|
2285 |
} |
|
2286 |
// NOTE: for vtable dispatches, the vtable entry will never be |
|
2287 |
// null. However it may very well end up in handle_wrong_method |
|
2288 |
// if the method is abstract for the particular class. |
|
2289 |
__ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset())); |
|
2290 |
// Call target. Either compiled code or C2I adapter. |
|
2291 |
__ z_basr(Z_R14, Z_R1_scratch); |
|
2292 |
unsigned int ret_off = __ offset(); |
|
2293 |
} |
|
2294 |
%} |
|
2295 |
||
2296 |
enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{
|
|
2297 |
MacroAssembler _masm(&cbuf); |
|
2298 |
Register Rdst = reg_to_register_object($dst$$reg); |
|
2299 |
Register Rsrc = reg_to_register_object($src$$reg); |
|
2300 |
||
2301 |
// Don't emit code if operands are identical (same register). |
|
2302 |
if (Rsrc != Rdst) {
|
|
2303 |
Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; |
|
2304 |
||
2305 |
if (VM_Version::has_LoadStoreConditional()) {
|
|
2306 |
__ z_locgr(Rdst, Rsrc, cc); |
|
2307 |
} else {
|
|
2308 |
// Branch if not (cmp cr). |
|
2309 |
Label done; |
|
2310 |
__ z_brc(Assembler::inverse_condition(cc), done); |
|
2311 |
__ z_lgr(Rdst, Rsrc); // Used for int and long+ptr. |
|
2312 |
__ bind(done); |
|
2313 |
} |
|
2314 |
} |
|
2315 |
%} |
|
2316 |
||
2317 |
enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{
|
|
2318 |
MacroAssembler _masm(&cbuf); |
|
2319 |
Register Rdst = reg_to_register_object($dst$$reg); |
|
2320 |
int Csrc = $src$$constant; |
|
2321 |
Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; |
|
2322 |
Label done; |
|
2323 |
// Branch if not (cmp cr). |
|
2324 |
__ z_brc(Assembler::inverse_condition(cc), done); |
|
2325 |
if (Csrc == 0) {
|
|
2326 |
// Don't set CC. |
|
2327 |
__ clear_reg(Rdst, true, false); // Use for int, long & ptr. |
|
2328 |
} else {
|
|
2329 |
__ z_lghi(Rdst, Csrc); // Use for int, long & ptr. |
|
2330 |
} |
|
2331 |
__ bind(done); |
|
2332 |
%} |
|
2333 |
||
2334 |
enc_class z_enc_cctobool(iRegI res) %{
|
|
2335 |
MacroAssembler _masm(&cbuf); |
|
2336 |
Register Rres = reg_to_register_object($res$$reg); |
|
2337 |
||
2338 |
if (VM_Version::has_LoadStoreConditional()) {
|
|
2339 |
__ load_const_optimized(Z_R0_scratch, 0L); // false (failed) |
|
2340 |
__ load_const_optimized(Rres, 1L); // true (succeed) |
|
2341 |
__ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual); |
|
2342 |
} else {
|
|
2343 |
Label done; |
|
2344 |
__ load_const_optimized(Rres, 0L); // false (failed) |
|
2345 |
__ z_brne(done); // Assume true to be the common case. |
|
2346 |
__ load_const_optimized(Rres, 1L); // true (succeed) |
|
2347 |
__ bind(done); |
|
2348 |
} |
|
2349 |
%} |
|
2350 |
||
2351 |
enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{
|
|
2352 |
MacroAssembler _masm(&cbuf); |
|
2353 |
Register Rcomp = reg_to_register_object($compare_value$$reg); |
|
2354 |
Register Rnew = reg_to_register_object($exchange_value$$reg); |
|
2355 |
Register Raddr = reg_to_register_object($addr_ptr$$reg); |
|
2356 |
||
2357 |
__ z_cs(Rcomp, Rnew, 0, Raddr); |
|
2358 |
%} |
|
2359 |
||
2360 |
enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{
|
|
2361 |
MacroAssembler _masm(&cbuf); |
|
2362 |
Register Rcomp = reg_to_register_object($compare_value$$reg); |
|
2363 |
Register Rnew = reg_to_register_object($exchange_value$$reg); |
|
2364 |
Register Raddr = reg_to_register_object($addr_ptr$$reg); |
|
2365 |
||
2366 |
__ z_csg(Rcomp, Rnew, 0, Raddr); |
|
2367 |
%} |
|
2368 |
||
2369 |
enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{
|
|
2370 |
MacroAssembler _masm(&cbuf); |
|
2371 |
Register Rdst = reg_to_register_object($dst$$reg); |
|
2372 |
Register Rtmp = reg_to_register_object($tmp$$reg); |
|
2373 |
guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF"); |
|
2374 |
Label retry; |
|
2375 |
||
2376 |
// Iterate until swap succeeds. |
|
2377 |
__ z_llgf(Rtmp, $mem$$Address); // current contents |
|
2378 |
__ bind(retry); |
|
2379 |
// Calculate incremented value. |
|
2380 |
__ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value. |
|
2381 |
__ z_brne(retry); // Yikes, concurrent update, need to retry. |
|
2382 |
__ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value. |
|
2383 |
%} |
|
2384 |
||
2385 |
enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{
|
|
2386 |
MacroAssembler _masm(&cbuf); |
|
2387 |
Register Rdst = reg_to_register_object($dst$$reg); |
|
2388 |
Register Rtmp = reg_to_register_object($tmp$$reg); |
|
2389 |
guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF"); |
|
2390 |
Label retry; |
|
2391 |
||
2392 |
// Iterate until swap succeeds. |
|
2393 |
__ z_lg(Rtmp, $mem$$Address); // current contents |
|
2394 |
__ bind(retry); |
|
2395 |
// Calculate incremented value. |
|
2396 |
__ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value. |
|
2397 |
__ z_brne(retry); // Yikes, concurrent update, need to retry. |
|
2398 |
__ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value. |
|
2399 |
%} |
|
2400 |
||
2401 |
%} // encode |
|
2402 |
||
2403 |
source %{
|
|
2404 |
||
2405 |
// Check whether outs are all Stores. If so, we can omit clearing the upper |
|
2406 |
// 32 bits after encoding. |
|
2407 |
static bool all_outs_are_Stores(const Node *n) {
|
|
2408 |
for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) {
|
|
2409 |
Node *out = n->fast_out(k); |
|
2410 |
if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) {
|
|
2411 |
// Most other outs are SpillCopy, but there are various other. |
|
2412 |
// jvm98 has arond 9% Encodes where we return false. |
|
2413 |
return false; |
|
2414 |
} |
|
2415 |
} |
|
2416 |
return true; |
|
2417 |
} |
|
2418 |
||
2419 |
%} // source |
|
2420 |
||
2421 |
||
2422 |
//----------FRAME-------------------------------------------------------------- |
|
2423 |
// Definition of frame structure and management information. |
|
2424 |
||
2425 |
frame %{
|
|
2426 |
// What direction does stack grow in (assumed to be same for native & Java). |
|
2427 |
stack_direction(TOWARDS_LOW); |
|
2428 |
||
2429 |
// These two registers define part of the calling convention between |
|
2430 |
// compiled code and the interpreter. |
|
2431 |
||
2432 |
// Inline Cache Register |
|
2433 |
inline_cache_reg(Z_R9); // Z_inline_cache |
|
2434 |
||
2435 |
// Argument pointer for I2C adapters |
|
2436 |
// |
|
2437 |
// Tos is loaded in run_compiled_code to Z_ARG5=Z_R6. |
|
2438 |
// interpreter_arg_ptr_reg(Z_R6); |
|
2439 |
||
2440 |
// Temporary in compiled entry-points |
|
2441 |
// compiler_method_oop_reg(Z_R1);//Z_R1_scratch |
|
2442 |
||
2443 |
// Method Oop Register when calling interpreter |
|
2444 |
interpreter_method_oop_reg(Z_R9);//Z_method |
|
2445 |
||
2446 |
// Optional: name the operand used by cisc-spilling to access |
|
2447 |
// [stack_pointer + offset]. |
|
2448 |
cisc_spilling_operand_name(indOffset12); |
|
2449 |
||
2450 |
// Number of stack slots consumed by a Monitor enter. |
|
2451 |
sync_stack_slots(frame::jit_monitor_size_in_4_byte_units); |
|
2452 |
||
2453 |
// Compiled code's Frame Pointer |
|
2454 |
// |
|
2455 |
// z/Architecture stack pointer |
|
2456 |
frame_pointer(Z_R15); // Z_SP |
|
2457 |
||
2458 |
// Interpreter stores its frame pointer in a register which is |
|
2459 |
// stored to the stack by I2CAdaptors. I2CAdaptors convert from |
|
2460 |
// interpreted java to compiled java. |
|
2461 |
// |
|
2462 |
// Z_state holds pointer to caller's cInterpreter. |
|
2463 |
interpreter_frame_pointer(Z_R7); // Z_state |
|
2464 |
||
2465 |
// Use alignment_in_bytes instead of log_2_of_alignment_in_bits. |
|
2466 |
stack_alignment(frame::alignment_in_bytes); |
|
2467 |
||
2468 |
in_preserve_stack_slots(frame::jit_in_preserve_size_in_4_byte_units); |
|
2469 |
||
2470 |
// A `slot' is assumed 4 bytes here! |
|
2471 |
// out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units); |
|
2472 |
||
2473 |
// Number of outgoing stack slots killed above the |
|
2474 |
// out_preserve_stack_slots for calls to C. Supports the var-args |
|
2475 |
// backing area for register parms. |
|
2476 |
varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size)); |
|
2477 |
||
2478 |
// The after-PROLOG location of the return address. Location of |
|
2479 |
// return address specifies a type (REG or STACK) and a number |
|
2480 |
// representing the register number (i.e. - use a register name) or |
|
2481 |
// stack slot. |
|
2482 |
return_addr(REG Z_R14); |
|
2483 |
||
2484 |
// This is the body of the function |
|
2485 |
// |
|
2486 |
// void Matcher::calling_convention(OptoRegPair* sig /* array of ideal regs */, |
|
2487 |
// uint length /* length of array */, |
|
2488 |
// bool is_outgoing) |
|
2489 |
// |
|
2490 |
// The `sig' array is to be updated. Sig[j] represents the location |
|
2491 |
// of the j-th argument, either a register or a stack slot. |
|
2492 |
||
2493 |
// Body of function which returns an integer array locating |
|
2494 |
// arguments either in registers or in stack slots. Passed an array |
|
2495 |
// of ideal registers called "sig" and a "length" count. Stack-slot |
|
2496 |
// offsets are based on outgoing arguments, i.e. a CALLER setting up |
|
2497 |
// arguments for a CALLEE. Incoming stack arguments are |
|
2498 |
// automatically biased by the preserve_stack_slots field above. |
|
2499 |
calling_convention %{
|
|
2500 |
// No difference between ingoing/outgoing just pass false. |
|
2501 |
SharedRuntime::java_calling_convention(sig_bt, regs, length, false); |
|
2502 |
%} |
|
2503 |
||
2504 |
// Body of function which returns an integer array locating |
|
2505 |
// arguments either in registers or in stack slots. Passed an array |
|
2506 |
// of ideal registers called "sig" and a "length" count. Stack-slot |
|
2507 |
// offsets are based on outgoing arguments, i.e. a CALLER setting up |
|
2508 |
// arguments for a CALLEE. Incoming stack arguments are |
|
2509 |
// automatically biased by the preserve_stack_slots field above. |
|
2510 |
c_calling_convention %{
|
|
2511 |
// This is obviously always outgoing. |
|
2512 |
// C argument must be in register AND stack slot. |
|
2513 |
(void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
|
2514 |
%} |
|
2515 |
||
2516 |
// Location of native (C/C++) and interpreter return values. This |
|
2517 |
// is specified to be the same as Java. In the 32-bit VM, long |
|
2518 |
// values are actually returned from native calls in O0:O1 and |
|
2519 |
// returned to the interpreter in I0:I1. The copying to and from |
|
2520 |
// the register pairs is done by the appropriate call and epilog |
|
2521 |
// opcodes. This simplifies the register allocator. |
|
2522 |
// |
|
2523 |
// Use register pair for c return value. |
|
2524 |
c_return_value %{
|
|
2525 |
assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values"); |
|
2526 |
static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
|
|
2527 |
static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
|
|
2528 |
return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); |
|
2529 |
%} |
|
2530 |
||
2531 |
// Use register pair for return value. |
|
2532 |
// Location of compiled Java return values. Same as C |
|
2533 |
return_value %{
|
|
2534 |
assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values"); |
|
2535 |
static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
|
|
2536 |
static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
|
|
2537 |
return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); |
|
2538 |
%} |
|
2539 |
%} |
|
2540 |
||
2541 |
||
2542 |
//----------ATTRIBUTES--------------------------------------------------------- |
|
2543 |
||
2544 |
//----------Operand Attributes------------------------------------------------- |
|
2545 |
op_attrib op_cost(1); // Required cost attribute |
|
2546 |
||
2547 |
//----------Instruction Attributes--------------------------------------------- |
|
2548 |
||
2549 |
// Cost attribute. required. |
|
2550 |
ins_attrib ins_cost(DEFAULT_COST); |
|
2551 |
||
2552 |
// Is this instruction a non-matching short branch variant of some |
|
2553 |
// long branch? Not required. |
|
2554 |
ins_attrib ins_short_branch(0); |
|
2555 |
||
2556 |
// Indicates this is a trap based check node and final control-flow fixup |
|
2557 |
// must generate a proper fall through. |
|
2558 |
ins_attrib ins_is_TrapBasedCheckNode(true); |
|
2559 |
||
2560 |
// Attribute of instruction to tell how many constants the instruction will generate. |
|
2561 |
// (optional attribute). Default: 0. |
|
2562 |
ins_attrib ins_num_consts(0); |
|
2563 |
||
2564 |
// Required alignment attribute (must be a power of 2) |
|
2565 |
// specifies the alignment that some part of the instruction (not |
|
2566 |
// necessarily the start) requires. If > 1, a compute_padding() |
|
2567 |
// function must be provided for the instruction. |
|
2568 |
// |
|
2569 |
// WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in |
|
2570 |
// instructions which depend on the proper alignment, because the |
|
2571 |
// desired alignment isn't guaranteed for the call to "emit()" during |
|
2572 |
// the size computation. |
|
2573 |
ins_attrib ins_alignment(1); |
|
2574 |
||
2575 |
// Enforce/prohibit rematerializations. |
|
2576 |
// - If an instruction is attributed with 'ins_cannot_rematerialize(true)' |
|
2577 |
// then rematerialization of that instruction is prohibited and the |
|
2578 |
// instruction's value will be spilled if necessary. |
|
2579 |
// - If an instruction is attributed with 'ins_should_rematerialize(true)' |
|
2580 |
// then rematerialization is enforced and the instruction's value will |
|
2581 |
// never get spilled. a copy of the instruction will be inserted if |
|
2582 |
// necessary. |
|
2583 |
// Note: this may result in rematerializations in front of every use. |
|
2584 |
// (optional attribute) |
|
2585 |
ins_attrib ins_cannot_rematerialize(false); |
|
2586 |
ins_attrib ins_should_rematerialize(false); |
|
2587 |
||
2588 |
//----------OPERANDS----------------------------------------------------------- |
|
2589 |
// Operand definitions must precede instruction definitions for correct |
|
2590 |
// parsing in the ADLC because operands constitute user defined types |
|
2591 |
// which are used in instruction definitions. |
|
2592 |
||
2593 |
//----------Simple Operands---------------------------------------------------- |
|
2594 |
// Immediate Operands |
|
2595 |
// Please note: |
|
2596 |
// Formats are generated automatically for constants and base registers. |
|
2597 |
||
2598 |
//---------------------------------------------- |
|
2599 |
// SIGNED (shorter than INT) immediate operands |
|
2600 |
//---------------------------------------------- |
|
2601 |
||
2602 |
// Byte Immediate: constant 'int -1' |
|
2603 |
operand immB_minus1() %{
|
|
2604 |
// sign-ext constant zero-ext constant |
|
2605 |
predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff)); |
|
2606 |
match(ConI); |
|
2607 |
op_cost(1); |
|
2608 |
format %{ %}
|
|
2609 |
interface(CONST_INTER); |
|
2610 |
%} |
|
2611 |
||
2612 |
// Byte Immediate: constant, but not 'int 0' nor 'int -1'. |
|
2613 |
operand immB_n0m1() %{
|
|
2614 |
// sign-ext constant zero-ext constant |
|
2615 |
predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff); |
|
2616 |
match(ConI); |
|
2617 |
op_cost(1); |
|
2618 |
format %{ %}
|
|
2619 |
interface(CONST_INTER); |
|
2620 |
%} |
|
2621 |
||
2622 |
// Short Immediate: constant 'int -1' |
|
2623 |
operand immS_minus1() %{
|
|
2624 |
// sign-ext constant zero-ext constant |
|
2625 |
predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff)); |
|
2626 |
match(ConI); |
|
2627 |
op_cost(1); |
|
2628 |
format %{ %}
|
|
2629 |
interface(CONST_INTER); |
|
2630 |
%} |
|
2631 |
||
2632 |
// Short Immediate: constant, but not 'int 0' nor 'int -1'. |
|
2633 |
operand immS_n0m1() %{
|
|
2634 |
// sign-ext constant zero-ext constant |
|
2635 |
predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff); |
|
2636 |
match(ConI); |
|
2637 |
op_cost(1); |
|
2638 |
format %{ %}
|
|
2639 |
interface(CONST_INTER); |
|
2640 |
%} |
|
2641 |
||
2642 |
//----------------------------------------- |
|
2643 |
// SIGNED INT immediate operands |
|
2644 |
//----------------------------------------- |
|
2645 |
||
2646 |
// Integer Immediate: 32-bit |
|
2647 |
operand immI() %{
|
|
2648 |
match(ConI); |
|
2649 |
op_cost(1); |
|
2650 |
format %{ %}
|
|
2651 |
interface(CONST_INTER); |
|
2652 |
%} |
|
2653 |
||
2654 |
// Int Immediate: 20-bit |
|
2655 |
operand immI20() %{
|
|
2656 |
predicate(Immediate::is_simm20(n->get_int())); |
|
2657 |
match(ConI); |
|
2658 |
op_cost(1); |
|
2659 |
format %{ %}
|
|
2660 |
interface(CONST_INTER); |
|
2661 |
%} |
|
2662 |
||
2663 |
// Integer Immediate: 16-bit |
|
2664 |
operand immI16() %{
|
|
2665 |
predicate(Immediate::is_simm16(n->get_int())); |
|
2666 |
match(ConI); |
|
2667 |
op_cost(1); |
|
2668 |
format %{ %}
|
|
2669 |
interface(CONST_INTER); |
|
2670 |
%} |
|
2671 |
||
2672 |
// Integer Immediate: 8-bit |
|
2673 |
operand immI8() %{
|
|
2674 |
predicate(Immediate::is_simm8(n->get_int())); |
|
2675 |
match(ConI); |
|
2676 |
op_cost(1); |
|
2677 |
format %{ %}
|
|
2678 |
interface(CONST_INTER); |
|
2679 |
%} |
|
2680 |
||
2681 |
// Integer Immediate: constant 'int 0' |
|
2682 |
operand immI_0() %{
|
|
2683 |
predicate(n->get_int() == 0); |
|
2684 |
match(ConI); |
|
2685 |
op_cost(1); |
|
2686 |
format %{ %}
|
|
2687 |
interface(CONST_INTER); |
|
2688 |
%} |
|
2689 |
||
2690 |
// Integer Immediate: constant 'int -1' |
|
2691 |
operand immI_minus1() %{
|
|
2692 |
predicate(n->get_int() == -1); |
|
2693 |
match(ConI); |
|
2694 |
op_cost(1); |
|
2695 |
format %{ %}
|
|
2696 |
interface(CONST_INTER); |
|
2697 |
%} |
|
2698 |
||
2699 |
// Integer Immediate: constant, but not 'int 0' nor 'int -1'. |
|
2700 |
operand immI_n0m1() %{
|
|
2701 |
predicate(n->get_int() != 0 && n->get_int() != -1); |
|
2702 |
match(ConI); |
|
2703 |
op_cost(1); |
|
2704 |
format %{ %}
|
|
2705 |
interface(CONST_INTER); |
|
2706 |
%} |
|
2707 |
||
2708 |
//------------------------------------------- |
|
2709 |
// UNSIGNED INT immediate operands |
|
2710 |
//------------------------------------------- |
|
2711 |
||
2712 |
// Unsigned Integer Immediate: 32-bit |
|
2713 |
operand uimmI() %{
|
|
2714 |
match(ConI); |
|
2715 |
op_cost(1); |
|
2716 |
format %{ %}
|
|
2717 |
interface(CONST_INTER); |
|
2718 |
%} |
|
2719 |
||
2720 |
// Unsigned Integer Immediate: 16-bit |
|
2721 |
operand uimmI16() %{
|
|
2722 |
predicate(Immediate::is_uimm16(n->get_int())); |
|
2723 |
match(ConI); |
|
2724 |
op_cost(1); |
|
2725 |
format %{ %}
|
|
2726 |
interface(CONST_INTER); |
|
2727 |
%} |
|
2728 |
||
2729 |
// Unsigned Integer Immediate: 12-bit |
|
2730 |
operand uimmI12() %{
|
|
2731 |
predicate(Immediate::is_uimm12(n->get_int())); |
|
2732 |
match(ConI); |
|
2733 |
op_cost(1); |
|
2734 |
format %{ %}
|
|
2735 |
interface(CONST_INTER); |
|
2736 |
%} |
|
2737 |
||
2738 |
// Unsigned Integer Immediate: 12-bit |
|
2739 |
operand uimmI8() %{
|
|
2740 |
predicate(Immediate::is_uimm8(n->get_int())); |
|
2741 |
match(ConI); |
|
2742 |
op_cost(1); |
|
2743 |
format %{ %}
|
|
2744 |
interface(CONST_INTER); |
|
2745 |
%} |
|
2746 |
||
2747 |
// Integer Immediate: 6-bit |
|
2748 |
operand uimmI6() %{
|
|
2749 |
predicate(Immediate::is_uimm(n->get_int(), 6)); |
|
2750 |
match(ConI); |
|
2751 |
op_cost(1); |
|
2752 |
format %{ %}
|
|
2753 |
interface(CONST_INTER); |
|
2754 |
%} |
|
2755 |
||
2756 |
// Integer Immediate: 5-bit |
|
2757 |
operand uimmI5() %{
|
|
2758 |
predicate(Immediate::is_uimm(n->get_int(), 5)); |
|
2759 |
match(ConI); |
|
2760 |
op_cost(1); |
|
2761 |
format %{ %}
|
|
2762 |
interface(CONST_INTER); |
|
2763 |
%} |
|
2764 |
||
2765 |
// Length for SS instructions, given in DWs, |
|
2766 |
// possible range [1..512], i.e. [8..4096] Bytes |
|
2767 |
// used range [1..256], i.e. [8..2048] Bytes |
|
2768 |
// operand type int |
|
2769 |
// Unsigned Integer Immediate: 9-bit |
|
2770 |
operand SSlenDW() %{
|
|
2771 |
predicate(Immediate::is_uimm8(n->get_long()-1)); |
|
2772 |
match(ConL); |
|
2773 |
op_cost(1); |
|
2774 |
format %{ %}
|
|
2775 |
interface(CONST_INTER); |
|
2776 |
%} |
|
2777 |
||
2778 |
//------------------------------------------ |
|
2779 |
// (UN)SIGNED INT specific values |
|
2780 |
//------------------------------------------ |
|
2781 |
||
2782 |
// Integer Immediate: the value 1 |
|
2783 |
operand immI_1() %{
|
|
2784 |
predicate(n->get_int() == 1); |
|
2785 |
match(ConI); |
|
2786 |
op_cost(1); |
|
2787 |
format %{ %}
|
|
2788 |
interface(CONST_INTER); |
|
2789 |
%} |
|
2790 |
||
2791 |
// Integer Immediate: the value 16. |
|
2792 |
operand immI_16() %{
|
|
2793 |
predicate(n->get_int() == 16); |
|
2794 |
match(ConI); |
|
2795 |
op_cost(1); |
|
2796 |
format %{ %}
|
|
2797 |
interface(CONST_INTER); |
|
2798 |
%} |
|
2799 |
||
2800 |
// Integer Immediate: the value 24. |
|
2801 |
operand immI_24() %{
|
|
2802 |
predicate(n->get_int() == 24); |
|
2803 |
match(ConI); |
|
2804 |
op_cost(1); |
|
2805 |
format %{ %}
|
|
2806 |
interface(CONST_INTER); |
|
2807 |
%} |
|
2808 |
||
2809 |
// Integer Immediate: the value 255 |
|
2810 |
operand immI_255() %{
|
|
2811 |
predicate(n->get_int() == 255); |
|
2812 |
match(ConI); |
|
2813 |
op_cost(1); |
|
2814 |
format %{ %}
|
|
2815 |
interface(CONST_INTER); |
|
2816 |
%} |
|
2817 |
||
2818 |
// Integer Immediate: the values 32-63 |
|
2819 |
operand immI_32_63() %{
|
|
2820 |
predicate(n->get_int() >= 32 && n->get_int() <= 63); |
|
2821 |
match(ConI); |
|
2822 |
op_cost(1); |
|
2823 |
format %{ %}
|
|
2824 |
interface(CONST_INTER); |
|
2825 |
%} |
|
2826 |
||
2827 |
// Unsigned Integer Immediate: LL-part, extended by 1s. |
|
2828 |
operand uimmI_LL1() %{
|
|
2829 |
predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000); |
|
2830 |
match(ConI); |
|
2831 |
op_cost(1); |
|
2832 |
format %{ %}
|
|
2833 |
interface(CONST_INTER); |
|
2834 |
%} |
|
2835 |
||
2836 |
// Unsigned Integer Immediate: LH-part, extended by 1s. |
|
2837 |
operand uimmI_LH1() %{
|
|
2838 |
predicate((n->get_int() & 0xFFFF) == 0xFFFF); |
|
2839 |
match(ConI); |
|
2840 |
op_cost(1); |
|
2841 |
format %{ %}
|
|
2842 |
interface(CONST_INTER); |
|
2843 |
%} |
|
2844 |
||
2845 |
//------------------------------------------ |
|
2846 |
// SIGNED LONG immediate operands |
|
2847 |
//------------------------------------------ |
|
2848 |
||
2849 |
operand immL() %{
|
|
2850 |
match(ConL); |
|
2851 |
op_cost(1); |
|
2852 |
format %{ %}
|
|
2853 |
interface(CONST_INTER); |
|
2854 |
%} |
|
2855 |
||
2856 |
// Long Immediate: 32-bit |
|
2857 |
operand immL32() %{
|
|
2858 |
predicate(Immediate::is_simm32(n->get_long())); |
|
2859 |
match(ConL); |
|
2860 |
op_cost(1); |
|
2861 |
format %{ %}
|
|
2862 |
interface(CONST_INTER); |
|
2863 |
%} |
|
2864 |
||
2865 |
// Long Immediate: 20-bit |
|
2866 |
operand immL20() %{
|
|
2867 |
predicate(Immediate::is_simm20(n->get_long())); |
|
2868 |
match(ConL); |
|
2869 |
op_cost(1); |
|
2870 |
format %{ %}
|
|
2871 |
interface(CONST_INTER); |
|
2872 |
%} |
|
2873 |
||
2874 |
// Long Immediate: 16-bit |
|
2875 |
operand immL16() %{
|
|
2876 |
predicate(Immediate::is_simm16(n->get_long())); |
|
2877 |
match(ConL); |
|
2878 |
op_cost(1); |
|
2879 |
format %{ %}
|
|
2880 |
interface(CONST_INTER); |
|
2881 |
%} |
|
2882 |
||
2883 |
// Long Immediate: 8-bit |
|
2884 |
operand immL8() %{
|
|
2885 |
predicate(Immediate::is_simm8(n->get_long())); |
|
2886 |
match(ConL); |
|
2887 |
op_cost(1); |
|
2888 |
format %{ %}
|
|
2889 |
interface(CONST_INTER); |
|
2890 |
%} |
|
2891 |
||
2892 |
//-------------------------------------------- |
|
2893 |
// UNSIGNED LONG immediate operands |
|
2894 |
//-------------------------------------------- |
|
2895 |
||
2896 |
operand uimmL32() %{
|
|
2897 |
predicate(Immediate::is_uimm32(n->get_long())); |
|
2898 |
match(ConL); |
|
2899 |
op_cost(1); |
|
2900 |
format %{ %}
|
|
2901 |
interface(CONST_INTER); |
|
2902 |
%} |
|
2903 |
||
2904 |
// Unsigned Long Immediate: 16-bit |
|
2905 |
operand uimmL16() %{
|
|
2906 |
predicate(Immediate::is_uimm16(n->get_long())); |
|
2907 |
match(ConL); |
|
2908 |
op_cost(1); |
|
2909 |
format %{ %}
|
|
2910 |
interface(CONST_INTER); |
|
2911 |
%} |
|
2912 |
||
2913 |
// Unsigned Long Immediate: 12-bit |
|
2914 |
operand uimmL12() %{
|
|
2915 |
predicate(Immediate::is_uimm12(n->get_long())); |
|
2916 |
match(ConL); |
|
2917 |
op_cost(1); |
|
2918 |
format %{ %}
|
|
2919 |
interface(CONST_INTER); |
|
2920 |
%} |
|
2921 |
||
2922 |
// Unsigned Long Immediate: 8-bit |
|
2923 |
operand uimmL8() %{
|
|
2924 |
predicate(Immediate::is_uimm8(n->get_long())); |
|
2925 |
match(ConL); |
|
2926 |
op_cost(1); |
|
2927 |
format %{ %}
|
|
2928 |
interface(CONST_INTER); |
|
2929 |
%} |
|
2930 |
||
2931 |
//------------------------------------------- |
|
2932 |
// (UN)SIGNED LONG specific values |
|
2933 |
//------------------------------------------- |
|
2934 |
||
2935 |
// Long Immediate: the value FF |
|
2936 |
operand immL_FF() %{
|
|
2937 |
predicate(n->get_long() == 0xFFL); |
|
2938 |
match(ConL); |
|
2939 |
op_cost(1); |
|
2940 |
format %{ %}
|
|
2941 |
interface(CONST_INTER); |
|
2942 |
%} |
|
2943 |
||
2944 |
// Long Immediate: the value FFFF |
|
2945 |
operand immL_FFFF() %{
|
|
2946 |
predicate(n->get_long() == 0xFFFFL); |
|
2947 |
match(ConL); |
|
2948 |
op_cost(1); |
|
2949 |
format %{ %}
|
|
2950 |
interface(CONST_INTER); |
|
2951 |
%} |
|
2952 |
||
2953 |
// Long Immediate: the value FFFFFFFF |
|
2954 |
operand immL_FFFFFFFF() %{
|
|
2955 |
predicate(n->get_long() == 0xFFFFFFFFL); |
|
2956 |
match(ConL); |
|
2957 |
op_cost(1); |
|
2958 |
format %{ %}
|
|
2959 |
interface(CONST_INTER); |
|
2960 |
%} |
|
2961 |
||
2962 |
operand immL_0() %{
|
|
2963 |
predicate(n->get_long() == 0L); |
|
2964 |
match(ConL); |
|
2965 |
op_cost(1); |
|
2966 |
format %{ %}
|
|
2967 |
interface(CONST_INTER); |
|
2968 |
%} |
|
2969 |
||
2970 |
// Unsigned Long Immediate: LL-part, extended by 1s. |
|
2971 |
operand uimmL_LL1() %{
|
|
2972 |
predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L); |
|
2973 |
match(ConL); |
|
2974 |
op_cost(1); |
|
2975 |
format %{ %}
|
|
2976 |
interface(CONST_INTER); |
|
2977 |
%} |
|
2978 |
||
2979 |
// Unsigned Long Immediate: LH-part, extended by 1s. |
|
2980 |
operand uimmL_LH1() %{
|
|
2981 |
predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL); |
|
2982 |
match(ConL); |
|
2983 |
op_cost(1); |
|
2984 |
format %{ %}
|
|
2985 |
interface(CONST_INTER); |
|
2986 |
%} |
|
2987 |
||
2988 |
// Unsigned Long Immediate: HL-part, extended by 1s. |
|
2989 |
operand uimmL_HL1() %{
|
|
2990 |
predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL); |
|
2991 |
match(ConL); |
|
2992 |
op_cost(1); |
|
2993 |
format %{ %}
|
|
2994 |
interface(CONST_INTER); |
|
2995 |
%} |
|
2996 |
||
2997 |
// Unsigned Long Immediate: HH-part, extended by 1s. |
|
2998 |
operand uimmL_HH1() %{
|
|
2999 |
predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL); |
|
3000 |
match(ConL); |
|
3001 |
op_cost(1); |
|
3002 |
format %{ %}
|
|
3003 |
interface(CONST_INTER); |
|
3004 |
%} |
|
3005 |
||
3006 |
// Long Immediate: low 32-bit mask |
|
3007 |
operand immL_32bits() %{
|
|
3008 |
predicate(n->get_long() == 0xFFFFFFFFL); |
|
3009 |
match(ConL); |
|
3010 |
op_cost(1); |
|
3011 |
format %{ %}
|
|
3012 |
interface(CONST_INTER); |
|
3013 |
%} |
|
3014 |
||
3015 |
//-------------------------------------- |
|
3016 |
// POINTER immediate operands |
|
3017 |
//-------------------------------------- |
|
3018 |
||
3019 |
// Pointer Immediate: 64-bit |
|
3020 |
operand immP() %{
|
|
3021 |
match(ConP); |
|
3022 |
op_cost(1); |
|
3023 |
format %{ %}
|
|
3024 |
interface(CONST_INTER); |
|
3025 |
%} |
|
3026 |
||
3027 |
// Pointer Immediate: 32-bit |
|
3028 |
operand immP32() %{
|
|
3029 |
predicate(Immediate::is_uimm32(n->get_ptr())); |
|
3030 |
match(ConP); |
|
3031 |
op_cost(1); |
|
3032 |
format %{ %}
|
|
3033 |
interface(CONST_INTER); |
|
3034 |
%} |
|
3035 |
||
3036 |
// Pointer Immediate: 16-bit |
|
3037 |
operand immP16() %{
|
|
3038 |
predicate(Immediate::is_uimm16(n->get_ptr())); |
|
3039 |
match(ConP); |
|
3040 |
op_cost(1); |
|
3041 |
format %{ %}
|
|
3042 |
interface(CONST_INTER); |
|
3043 |
%} |
|
3044 |
||
3045 |
// Pointer Immediate: 8-bit |
|
3046 |
operand immP8() %{
|
|
3047 |
predicate(Immediate::is_uimm8(n->get_ptr())); |
|
3048 |
match(ConP); |
|
3049 |
op_cost(1); |
|
3050 |
format %{ %}
|
|
3051 |
interface(CONST_INTER); |
|
3052 |
%} |
|
3053 |
||
3054 |
//----------------------------------- |
|
3055 |
// POINTER specific values |
|
3056 |
//----------------------------------- |
|
3057 |
||
3058 |
// Pointer Immediate: NULL |
|
3059 |
operand immP0() %{
|
|
3060 |
predicate(n->get_ptr() == 0); |
|
3061 |
match(ConP); |
|
3062 |
op_cost(1); |
|
3063 |
format %{ %}
|
|
3064 |
interface(CONST_INTER); |
|
3065 |
%} |
|
3066 |
||
3067 |
//--------------------------------------------- |
|
3068 |
// NARROW POINTER immediate operands |
|
3069 |
//--------------------------------------------- |
|
3070 |
||
3071 |
// Narrow Pointer Immediate |
|
3072 |
operand immN() %{
|
|
3073 |
match(ConN); |
|
3074 |
op_cost(1); |
|
3075 |
format %{ %}
|
|
3076 |
interface(CONST_INTER); |
|
3077 |
%} |
|
3078 |
||
3079 |
operand immNKlass() %{
|
|
3080 |
match(ConNKlass); |
|
3081 |
op_cost(1); |
|
3082 |
format %{ %}
|
|
3083 |
interface(CONST_INTER); |
|
3084 |
%} |
|
3085 |
||
3086 |
// Narrow Pointer Immediate |
|
3087 |
operand immN8() %{
|
|
3088 |
predicate(Immediate::is_uimm8(n->get_narrowcon())); |
|
3089 |
match(ConN); |
|
3090 |
op_cost(1); |
|
3091 |
format %{ %}
|
|
3092 |
interface(CONST_INTER); |
|
3093 |
%} |
|
3094 |
||
3095 |
// Narrow NULL Pointer Immediate |
|
3096 |
operand immN0() %{
|
|
3097 |
predicate(n->get_narrowcon() == 0); |
|
3098 |
match(ConN); |
|
3099 |
op_cost(1); |
|
3100 |
format %{ %}
|
|
3101 |
interface(CONST_INTER); |
|
3102 |
%} |
|
3103 |
||
3104 |
// FLOAT and DOUBLE immediate operands |
|
3105 |
||
3106 |
// Double Immediate |
|
3107 |
operand immD() %{
|
|
3108 |
match(ConD); |
|
3109 |
op_cost(1); |
|
3110 |
format %{ %}
|
|
3111 |
interface(CONST_INTER); |
|
3112 |
%} |
|
3113 |
||
3114 |
// Double Immediate: +-0 |
|
3115 |
operand immDpm0() %{
|
|
3116 |
predicate(n->getd() == 0); |
|
3117 |
match(ConD); |
|
3118 |
op_cost(1); |
|
3119 |
format %{ %}
|
|
3120 |
interface(CONST_INTER); |
|
3121 |
%} |
|
3122 |
||
3123 |
// Double Immediate: +0 |
|
3124 |
operand immDp0() %{
|
|
3125 |
predicate(jlong_cast(n->getd()) == 0); |
|
3126 |
match(ConD); |
|
3127 |
op_cost(1); |
|
3128 |
format %{ %}
|
|
3129 |
interface(CONST_INTER); |
|
3130 |
%} |
|
3131 |
||
3132 |
// Float Immediate |
|
3133 |
operand immF() %{
|
|
3134 |
match(ConF); |
|
3135 |
op_cost(1); |
|
3136 |
format %{ %}
|
|
3137 |
interface(CONST_INTER); |
|
3138 |
%} |
|
3139 |
||
3140 |
// Float Immediate: +-0 |
|
3141 |
operand immFpm0() %{
|
|
3142 |
predicate(n->getf() == 0); |
|
3143 |
match(ConF); |
|
3144 |
op_cost(1); |
|
3145 |
format %{ %}
|
|
3146 |
interface(CONST_INTER); |
|
3147 |
%} |
|
3148 |
||
3149 |
// Float Immediate: +0 |
|
3150 |
operand immFp0() %{
|
|
3151 |
predicate(jint_cast(n->getf()) == 0); |
|
3152 |
match(ConF); |
|
3153 |
op_cost(1); |
|
3154 |
format %{ %}
|
|
3155 |
interface(CONST_INTER); |
|
3156 |
%} |
|
3157 |
||
3158 |
// End of Immediate Operands |
|
3159 |
||
3160 |
// Integer Register Operands |
|
3161 |
// Integer Register |
|
3162 |
operand iRegI() %{
|
|
3163 |
constraint(ALLOC_IN_RC(z_int_reg)); |
|
3164 |
match(RegI); |
|
3165 |
match(noArg_iRegI); |
|
3166 |
match(rarg1RegI); |
|
3167 |
match(rarg2RegI); |
|
3168 |
match(rarg3RegI); |
|
3169 |
match(rarg4RegI); |
|
3170 |
match(rarg5RegI); |
|
3171 |
match(noOdd_iRegI); |
|
3172 |
match(revenRegI); |
|
3173 |
match(roddRegI); |
|
3174 |
format %{ %}
|
|
3175 |
interface(REG_INTER); |
|
3176 |
%} |
|
3177 |
||
3178 |
operand noArg_iRegI() %{
|
|
3179 |
constraint(ALLOC_IN_RC(z_no_arg_int_reg)); |
|
3180 |
match(RegI); |
|
3181 |
format %{ %}
|
|
3182 |
interface(REG_INTER); |
|
3183 |
%} |
|
3184 |
||
|
47606
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
3185 |
// revenRegI and roddRegI constitute and even-odd-pair. |
| 42065 | 3186 |
operand revenRegI() %{
|
3187 |
constraint(ALLOC_IN_RC(z_rarg3_int_reg)); |
|
3188 |
match(iRegI); |
|
3189 |
format %{ %}
|
|
3190 |
interface(REG_INTER); |
|
3191 |
%} |
|
3192 |
||
|
47606
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
3193 |
// revenRegI and roddRegI constitute and even-odd-pair. |
| 42065 | 3194 |
operand roddRegI() %{
|
3195 |
constraint(ALLOC_IN_RC(z_rarg4_int_reg)); |
|
3196 |
match(iRegI); |
|
3197 |
format %{ %}
|
|
3198 |
interface(REG_INTER); |
|
3199 |
%} |
|
3200 |
||
3201 |
operand rarg1RegI() %{
|
|
3202 |
constraint(ALLOC_IN_RC(z_rarg1_int_reg)); |
|
3203 |
match(iRegI); |
|
3204 |
format %{ %}
|
|
3205 |
interface(REG_INTER); |
|
3206 |
%} |
|
3207 |
||
3208 |
operand rarg2RegI() %{
|
|
3209 |
constraint(ALLOC_IN_RC(z_rarg2_int_reg)); |
|
3210 |
match(iRegI); |
|
3211 |
format %{ %}
|
|
3212 |
interface(REG_INTER); |
|
3213 |
%} |
|
3214 |
||
3215 |
operand rarg3RegI() %{
|
|
3216 |
constraint(ALLOC_IN_RC(z_rarg3_int_reg)); |
|
3217 |
match(iRegI); |
|
3218 |
format %{ %}
|
|
3219 |
interface(REG_INTER); |
|
3220 |
%} |
|
3221 |
||
3222 |
operand rarg4RegI() %{
|
|
3223 |
constraint(ALLOC_IN_RC(z_rarg4_int_reg)); |
|
3224 |
match(iRegI); |
|
3225 |
format %{ %}
|
|
3226 |
interface(REG_INTER); |
|
3227 |
%} |
|
3228 |
||
3229 |
operand rarg5RegI() %{
|
|
3230 |
constraint(ALLOC_IN_RC(z_rarg5_int_reg)); |
|
3231 |
match(iRegI); |
|
3232 |
format %{ %}
|
|
3233 |
interface(REG_INTER); |
|
3234 |
%} |
|
3235 |
||
3236 |
operand noOdd_iRegI() %{
|
|
3237 |
constraint(ALLOC_IN_RC(z_no_odd_int_reg)); |
|
3238 |
match(RegI); |
|
3239 |
match(revenRegI); |
|
3240 |
format %{ %}
|
|
3241 |
interface(REG_INTER); |
|
3242 |
%} |
|
3243 |
||
3244 |
// Pointer Register |
|
3245 |
operand iRegP() %{
|
|
3246 |
constraint(ALLOC_IN_RC(z_ptr_reg)); |
|
3247 |
match(RegP); |
|
3248 |
match(noArg_iRegP); |
|
3249 |
match(rarg1RegP); |
|
3250 |
match(rarg2RegP); |
|
3251 |
match(rarg3RegP); |
|
3252 |
match(rarg4RegP); |
|
3253 |
match(rarg5RegP); |
|
3254 |
match(revenRegP); |
|
3255 |
match(roddRegP); |
|
3256 |
format %{ %}
|
|
3257 |
interface(REG_INTER); |
|
3258 |
%} |
|
3259 |
||
3260 |
// thread operand |
|
3261 |
operand threadRegP() %{
|
|
3262 |
constraint(ALLOC_IN_RC(z_thread_ptr_reg)); |
|
3263 |
match(RegP); |
|
3264 |
format %{ "Z_THREAD" %}
|
|
3265 |
interface(REG_INTER); |
|
3266 |
%} |
|
3267 |
||
3268 |
operand noArg_iRegP() %{
|
|
3269 |
constraint(ALLOC_IN_RC(z_no_arg_ptr_reg)); |
|
3270 |
match(iRegP); |
|
3271 |
format %{ %}
|
|
3272 |
interface(REG_INTER); |
|
3273 |
%} |
|
3274 |
||
3275 |
operand rarg1RegP() %{
|
|
3276 |
constraint(ALLOC_IN_RC(z_rarg1_ptr_reg)); |
|
3277 |
match(iRegP); |
|
3278 |
format %{ %}
|
|
3279 |
interface(REG_INTER); |
|
3280 |
%} |
|
3281 |
||
3282 |
operand rarg2RegP() %{
|
|
3283 |
constraint(ALLOC_IN_RC(z_rarg2_ptr_reg)); |
|
3284 |
match(iRegP); |
|
3285 |
format %{ %}
|
|
3286 |
interface(REG_INTER); |
|
3287 |
%} |
|
3288 |
||
3289 |
operand rarg3RegP() %{
|
|
3290 |
constraint(ALLOC_IN_RC(z_rarg3_ptr_reg)); |
|
3291 |
match(iRegP); |
|
3292 |
format %{ %}
|
|
3293 |
interface(REG_INTER); |
|
3294 |
%} |
|
3295 |
||
3296 |
operand rarg4RegP() %{
|
|
3297 |
constraint(ALLOC_IN_RC(z_rarg4_ptr_reg)); |
|
3298 |
match(iRegP); |
|
3299 |
format %{ %}
|
|
3300 |
interface(REG_INTER); |
|
3301 |
%} |
|
3302 |
||
3303 |
operand rarg5RegP() %{
|
|
3304 |
constraint(ALLOC_IN_RC(z_rarg5_ptr_reg)); |
|
3305 |
match(iRegP); |
|
3306 |
format %{ %}
|
|
3307 |
interface(REG_INTER); |
|
3308 |
%} |
|
3309 |
||
3310 |
operand memoryRegP() %{
|
|
3311 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
|
3312 |
match(RegP); |
|
3313 |
match(iRegP); |
|
3314 |
match(threadRegP); |
|
3315 |
format %{ %}
|
|
3316 |
interface(REG_INTER); |
|
3317 |
%} |
|
3318 |
||
|
47606
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
3319 |
// revenRegP and roddRegP constitute and even-odd-pair. |
| 42065 | 3320 |
operand revenRegP() %{
|
3321 |
constraint(ALLOC_IN_RC(z_rarg3_ptr_reg)); |
|
3322 |
match(iRegP); |
|
3323 |
format %{ %}
|
|
3324 |
interface(REG_INTER); |
|
3325 |
%} |
|
3326 |
||
|
47606
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
3327 |
// revenRegP and roddRegP constitute and even-odd-pair. |
| 42065 | 3328 |
operand roddRegP() %{
|
3329 |
constraint(ALLOC_IN_RC(z_rarg4_ptr_reg)); |
|
3330 |
match(iRegP); |
|
3331 |
format %{ %}
|
|
3332 |
interface(REG_INTER); |
|
3333 |
%} |
|
3334 |
||
3335 |
operand lock_ptr_RegP() %{
|
|
3336 |
constraint(ALLOC_IN_RC(z_lock_ptr_reg)); |
|
3337 |
match(RegP); |
|
3338 |
format %{ %}
|
|
3339 |
interface(REG_INTER); |
|
3340 |
%} |
|
3341 |
||
3342 |
operand rscratch2RegP() %{
|
|
3343 |
constraint(ALLOC_IN_RC(z_rscratch2_bits64_reg)); |
|
3344 |
match(RegP); |
|
3345 |
format %{ %}
|
|
3346 |
interface(REG_INTER); |
|
3347 |
%} |
|
3348 |
||
3349 |
operand iRegN() %{
|
|
3350 |
constraint(ALLOC_IN_RC(z_int_reg)); |
|
3351 |
match(RegN); |
|
3352 |
match(noArg_iRegN); |
|
3353 |
match(rarg1RegN); |
|
3354 |
match(rarg2RegN); |
|
3355 |
match(rarg3RegN); |
|
3356 |
match(rarg4RegN); |
|
3357 |
match(rarg5RegN); |
|
3358 |
format %{ %}
|
|
3359 |
interface(REG_INTER); |
|
3360 |
%} |
|
3361 |
||
3362 |
operand noArg_iRegN() %{
|
|
3363 |
constraint(ALLOC_IN_RC(z_no_arg_int_reg)); |
|
3364 |
match(iRegN); |
|
3365 |
format %{ %}
|
|
3366 |
interface(REG_INTER); |
|
3367 |
%} |
|
3368 |
||
3369 |
operand rarg1RegN() %{
|
|
3370 |
constraint(ALLOC_IN_RC(z_rarg1_int_reg)); |
|
3371 |
match(iRegN); |
|
3372 |
format %{ %}
|
|
3373 |
interface(REG_INTER); |
|
3374 |
%} |
|
3375 |
||
3376 |
operand rarg2RegN() %{
|
|
3377 |
constraint(ALLOC_IN_RC(z_rarg2_int_reg)); |
|
3378 |
match(iRegN); |
|
3379 |
format %{ %}
|
|
3380 |
interface(REG_INTER); |
|
3381 |
%} |
|
3382 |
||
3383 |
operand rarg3RegN() %{
|
|
3384 |
constraint(ALLOC_IN_RC(z_rarg3_int_reg)); |
|
3385 |
match(iRegN); |
|
3386 |
format %{ %}
|
|
3387 |
interface(REG_INTER); |
|
3388 |
%} |
|
3389 |
||
3390 |
operand rarg4RegN() %{
|
|
3391 |
constraint(ALLOC_IN_RC(z_rarg4_int_reg)); |
|
3392 |
match(iRegN); |
|
3393 |
format %{ %}
|
|
3394 |
interface(REG_INTER); |
|
3395 |
%} |
|
3396 |
||
3397 |
operand rarg5RegN() %{
|
|
3398 |
constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg)); |
|
3399 |
match(iRegN); |
|
3400 |
format %{ %}
|
|
3401 |
interface(REG_INTER); |
|
3402 |
%} |
|
3403 |
||
3404 |
// Long Register |
|
3405 |
operand iRegL() %{
|
|
3406 |
constraint(ALLOC_IN_RC(z_long_reg)); |
|
3407 |
match(RegL); |
|
3408 |
match(revenRegL); |
|
3409 |
match(roddRegL); |
|
|
54542
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
3410 |
match(allRoddRegL); |
| 42065 | 3411 |
match(rarg1RegL); |
3412 |
match(rarg5RegL); |
|
3413 |
format %{ %}
|
|
3414 |
interface(REG_INTER); |
|
3415 |
%} |
|
3416 |
||
|
47606
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
3417 |
// revenRegL and roddRegL constitute and even-odd-pair. |
| 42065 | 3418 |
operand revenRegL() %{
|
3419 |
constraint(ALLOC_IN_RC(z_rarg3_long_reg)); |
|
3420 |
match(iRegL); |
|
3421 |
format %{ %}
|
|
3422 |
interface(REG_INTER); |
|
3423 |
%} |
|
3424 |
||
|
47606
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
3425 |
// revenRegL and roddRegL constitute and even-odd-pair. |
| 42065 | 3426 |
operand roddRegL() %{
|
3427 |
constraint(ALLOC_IN_RC(z_rarg4_long_reg)); |
|
3428 |
match(iRegL); |
|
3429 |
format %{ %}
|
|
3430 |
interface(REG_INTER); |
|
3431 |
%} |
|
3432 |
||
|
54542
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
3433 |
// available odd registers for iRegL |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
3434 |
operand allRoddRegL() %{
|
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
3435 |
constraint(ALLOC_IN_RC(z_long_odd_reg)); |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
3436 |
match(iRegL); |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
3437 |
format %{ %}
|
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
3438 |
interface(REG_INTER); |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
3439 |
%} |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
3440 |
|
| 42065 | 3441 |
operand rarg1RegL() %{
|
3442 |
constraint(ALLOC_IN_RC(z_rarg1_long_reg)); |
|
3443 |
match(iRegL); |
|
3444 |
format %{ %}
|
|
3445 |
interface(REG_INTER); |
|
3446 |
%} |
|
3447 |
||
3448 |
operand rarg5RegL() %{
|
|
3449 |
constraint(ALLOC_IN_RC(z_rarg5_long_reg)); |
|
3450 |
match(iRegL); |
|
3451 |
format %{ %}
|
|
3452 |
interface(REG_INTER); |
|
3453 |
%} |
|
3454 |
||
3455 |
// Condition Code Flag Registers |
|
3456 |
operand flagsReg() %{
|
|
3457 |
constraint(ALLOC_IN_RC(z_condition_reg)); |
|
3458 |
match(RegFlags); |
|
3459 |
format %{ "CR" %}
|
|
3460 |
interface(REG_INTER); |
|
3461 |
%} |
|
3462 |
||
3463 |
// Condition Code Flag Registers for rules with result tuples |
|
3464 |
operand TD_flagsReg() %{
|
|
3465 |
constraint(ALLOC_IN_RC(z_condition_reg)); |
|
3466 |
match(RegFlags); |
|
3467 |
format %{ "CR" %}
|
|
3468 |
interface(REG_TUPLE_DEST_INTER); |
|
3469 |
%} |
|
3470 |
||
3471 |
operand regD() %{
|
|
3472 |
constraint(ALLOC_IN_RC(z_dbl_reg)); |
|
3473 |
match(RegD); |
|
3474 |
format %{ %}
|
|
3475 |
interface(REG_INTER); |
|
3476 |
%} |
|
3477 |
||
3478 |
operand rscratchRegD() %{
|
|
3479 |
constraint(ALLOC_IN_RC(z_rscratch1_dbl_reg)); |
|
3480 |
match(RegD); |
|
3481 |
format %{ %}
|
|
3482 |
interface(REG_INTER); |
|
3483 |
%} |
|
3484 |
||
3485 |
operand regF() %{
|
|
3486 |
constraint(ALLOC_IN_RC(z_flt_reg)); |
|
3487 |
match(RegF); |
|
3488 |
format %{ %}
|
|
3489 |
interface(REG_INTER); |
|
3490 |
%} |
|
3491 |
||
3492 |
operand rscratchRegF() %{
|
|
3493 |
constraint(ALLOC_IN_RC(z_rscratch1_flt_reg)); |
|
3494 |
match(RegF); |
|
3495 |
format %{ %}
|
|
3496 |
interface(REG_INTER); |
|
3497 |
%} |
|
3498 |
||
3499 |
// Special Registers |
|
3500 |
||
3501 |
// Method Register |
|
3502 |
operand inline_cache_regP(iRegP reg) %{
|
|
3503 |
constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg |
|
3504 |
match(reg); |
|
3505 |
format %{ %}
|
|
3506 |
interface(REG_INTER); |
|
3507 |
%} |
|
3508 |
||
3509 |
operand compiler_method_oop_regP(iRegP reg) %{
|
|
3510 |
constraint(ALLOC_IN_RC(z_r1_RegP)); // compiler_method_oop_reg |
|
3511 |
match(reg); |
|
3512 |
format %{ %}
|
|
3513 |
interface(REG_INTER); |
|
3514 |
%} |
|
3515 |
||
3516 |
operand interpreter_method_oop_regP(iRegP reg) %{
|
|
3517 |
constraint(ALLOC_IN_RC(z_r9_regP)); // interpreter_method_oop_reg |
|
3518 |
match(reg); |
|
3519 |
format %{ %}
|
|
3520 |
interface(REG_INTER); |
|
3521 |
%} |
|
3522 |
||
3523 |
// Operands to remove register moves in unscaled mode. |
|
3524 |
// Match read/write registers with an EncodeP node if neither shift nor add are required. |
|
3525 |
operand iRegP2N(iRegP reg) %{
|
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
3526 |
predicate(CompressedOops::shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL); |
| 42065 | 3527 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
3528 |
match(EncodeP reg); |
|
3529 |
format %{ "$reg" %}
|
|
3530 |
interface(REG_INTER) |
|
3531 |
%} |
|
3532 |
||
3533 |
operand iRegN2P(iRegN reg) %{
|
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
3534 |
predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0 && |
| 42065 | 3535 |
_leaf->as_DecodeN()->in(0) == NULL); |
3536 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
|
3537 |
match(DecodeN reg); |
|
3538 |
format %{ "$reg" %}
|
|
3539 |
interface(REG_INTER) |
|
3540 |
%} |
|
3541 |
||
3542 |
||
3543 |
//----------Complex Operands--------------------------------------------------- |
|
3544 |
||
3545 |
// Indirect Memory Reference |
|
3546 |
operand indirect(memoryRegP base) %{
|
|
3547 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
|
3548 |
match(base); |
|
3549 |
op_cost(1); |
|
3550 |
format %{ "#0[,$base]" %}
|
|
3551 |
interface(MEMORY_INTER) %{
|
|
3552 |
base($base); |
|
3553 |
index(0xffffFFFF); // noreg |
|
3554 |
scale(0x0); |
|
3555 |
disp(0x0); |
|
3556 |
%} |
|
3557 |
%} |
|
3558 |
||
3559 |
// Indirect with Offset (long) |
|
3560 |
operand indOffset20(memoryRegP base, immL20 offset) %{
|
|
3561 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
|
3562 |
match(AddP base offset); |
|
3563 |
op_cost(1); |
|
3564 |
format %{ "$offset[,$base]" %}
|
|
3565 |
interface(MEMORY_INTER) %{
|
|
3566 |
base($base); |
|
3567 |
index(0xffffFFFF); // noreg |
|
3568 |
scale(0x0); |
|
3569 |
disp($offset); |
|
3570 |
%} |
|
3571 |
%} |
|
3572 |
||
3573 |
operand indOffset20Narrow(iRegN base, immL20 offset) %{
|
|
3574 |
predicate(Matcher::narrow_oop_use_complex_address()); |
|
3575 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
|
3576 |
match(AddP (DecodeN base) offset); |
|
3577 |
op_cost(1); |
|
3578 |
format %{ "$offset[,$base]" %}
|
|
3579 |
interface(MEMORY_INTER) %{
|
|
3580 |
base($base); |
|
3581 |
index(0xffffFFFF); // noreg |
|
3582 |
scale(0x0); |
|
3583 |
disp($offset); |
|
3584 |
%} |
|
3585 |
%} |
|
3586 |
||
3587 |
// Indirect with Offset (short) |
|
3588 |
operand indOffset12(memoryRegP base, uimmL12 offset) %{
|
|
3589 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
|
3590 |
match(AddP base offset); |
|
3591 |
op_cost(1); |
|
3592 |
format %{ "$offset[[,$base]]" %}
|
|
3593 |
interface(MEMORY_INTER) %{
|
|
3594 |
base($base); |
|
3595 |
index(0xffffFFFF); // noreg |
|
3596 |
scale(0x0); |
|
3597 |
disp($offset); |
|
3598 |
%} |
|
3599 |
%} |
|
3600 |
||
3601 |
operand indOffset12Narrow(iRegN base, uimmL12 offset) %{
|
|
3602 |
predicate(Matcher::narrow_oop_use_complex_address()); |
|
3603 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
|
3604 |
match(AddP (DecodeN base) offset); |
|
3605 |
op_cost(1); |
|
3606 |
format %{ "$offset[[,$base]]" %}
|
|
3607 |
interface(MEMORY_INTER) %{
|
|
3608 |
base($base); |
|
3609 |
index(0xffffFFFF); // noreg |
|
3610 |
scale(0x0); |
|
3611 |
disp($offset); |
|
3612 |
%} |
|
3613 |
%} |
|
3614 |
||
3615 |
// Indirect with Register Index |
|
3616 |
operand indIndex(memoryRegP base, iRegL index) %{
|
|
3617 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
|
3618 |
match(AddP base index); |
|
3619 |
op_cost(1); |
|
3620 |
format %{ "#0[($index,$base)]" %}
|
|
3621 |
interface(MEMORY_INTER) %{
|
|
3622 |
base($base); |
|
3623 |
index($index); |
|
3624 |
scale(0x0); |
|
3625 |
disp(0x0); |
|
3626 |
%} |
|
3627 |
%} |
|
3628 |
||
3629 |
// Indirect with Offset (long) and index |
|
3630 |
operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{
|
|
3631 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
|
3632 |
match(AddP (AddP base index) offset); |
|
3633 |
op_cost(1); |
|
3634 |
format %{ "$offset[($index,$base)]" %}
|
|
3635 |
interface(MEMORY_INTER) %{
|
|
3636 |
base($base); |
|
3637 |
index($index); |
|
3638 |
scale(0x0); |
|
3639 |
disp($offset); |
|
3640 |
%} |
|
3641 |
%} |
|
3642 |
||
3643 |
operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{
|
|
3644 |
predicate(Matcher::narrow_oop_use_complex_address()); |
|
3645 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
|
3646 |
match(AddP (AddP (DecodeN base) index) offset); |
|
3647 |
op_cost(1); |
|
3648 |
format %{ "$offset[($index,$base)]" %}
|
|
3649 |
interface(MEMORY_INTER) %{
|
|
3650 |
base($base); |
|
3651 |
index($index); |
|
3652 |
scale(0x0); |
|
3653 |
disp($offset); |
|
3654 |
%} |
|
3655 |
%} |
|
3656 |
||
3657 |
// Indirect with Offset (short) and index |
|
3658 |
operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{
|
|
3659 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
|
3660 |
match(AddP (AddP base index) offset); |
|
3661 |
op_cost(1); |
|
3662 |
format %{ "$offset[[($index,$base)]]" %}
|
|
3663 |
interface(MEMORY_INTER) %{
|
|
3664 |
base($base); |
|
3665 |
index($index); |
|
3666 |
scale(0x0); |
|
3667 |
disp($offset); |
|
3668 |
%} |
|
3669 |
%} |
|
3670 |
||
3671 |
operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{
|
|
3672 |
predicate(Matcher::narrow_oop_use_complex_address()); |
|
3673 |
constraint(ALLOC_IN_RC(z_memory_ptr_reg)); |
|
3674 |
match(AddP (AddP (DecodeN base) index) offset); |
|
3675 |
op_cost(1); |
|
3676 |
format %{ "$offset[[($index,$base)]]" %}
|
|
3677 |
interface(MEMORY_INTER) %{
|
|
3678 |
base($base); |
|
3679 |
index($index); |
|
3680 |
scale(0x0); |
|
3681 |
disp($offset); |
|
3682 |
%} |
|
3683 |
%} |
|
3684 |
||
3685 |
//----------Special Memory Operands-------------------------------------------- |
|
3686 |
||
3687 |
// Stack Slot Operand |
|
3688 |
// This operand is used for loading and storing temporary values on |
|
3689 |
// the stack where a match requires a value to flow through memory. |
|
3690 |
operand stackSlotI(sRegI reg) %{
|
|
3691 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
3692 |
op_cost(1); |
|
3693 |
format %{ "[$reg(stackSlotI)]" %}
|
|
3694 |
interface(MEMORY_INTER) %{
|
|
3695 |
base(0xf); // Z_SP |
|
3696 |
index(0xffffFFFF); // noreg |
|
3697 |
scale(0x0); |
|
3698 |
disp($reg); // stack offset |
|
3699 |
%} |
|
3700 |
%} |
|
3701 |
||
3702 |
operand stackSlotP(sRegP reg) %{
|
|
3703 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
3704 |
op_cost(1); |
|
3705 |
format %{ "[$reg(stackSlotP)]" %}
|
|
3706 |
interface(MEMORY_INTER) %{
|
|
3707 |
base(0xf); // Z_SP |
|
3708 |
index(0xffffFFFF); // noreg |
|
3709 |
scale(0x0); |
|
3710 |
disp($reg); // Stack Offset |
|
3711 |
%} |
|
3712 |
%} |
|
3713 |
||
3714 |
operand stackSlotF(sRegF reg) %{
|
|
3715 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
3716 |
op_cost(1); |
|
3717 |
format %{ "[$reg(stackSlotF)]" %}
|
|
3718 |
interface(MEMORY_INTER) %{
|
|
3719 |
base(0xf); // Z_SP |
|
3720 |
index(0xffffFFFF); // noreg |
|
3721 |
scale(0x0); |
|
3722 |
disp($reg); // Stack Offset |
|
3723 |
%} |
|
3724 |
%} |
|
3725 |
||
3726 |
operand stackSlotD(sRegD reg) %{
|
|
3727 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
3728 |
op_cost(1); |
|
3729 |
//match(RegD); |
|
3730 |
format %{ "[$reg(stackSlotD)]" %}
|
|
3731 |
interface(MEMORY_INTER) %{
|
|
3732 |
base(0xf); // Z_SP |
|
3733 |
index(0xffffFFFF); // noreg |
|
3734 |
scale(0x0); |
|
3735 |
disp($reg); // Stack Offset |
|
3736 |
%} |
|
3737 |
%} |
|
3738 |
||
3739 |
operand stackSlotL(sRegL reg) %{
|
|
3740 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
3741 |
op_cost(1); //match(RegL); |
|
3742 |
format %{ "[$reg(stackSlotL)]" %}
|
|
3743 |
interface(MEMORY_INTER) %{
|
|
3744 |
base(0xf); // Z_SP |
|
3745 |
index(0xffffFFFF); // noreg |
|
3746 |
scale(0x0); |
|
3747 |
disp($reg); // Stack Offset |
|
3748 |
%} |
|
3749 |
%} |
|
3750 |
||
3751 |
// Operands for expressing Control Flow |
|
3752 |
// NOTE: Label is a predefined operand which should not be redefined in |
|
3753 |
// the AD file. It is generically handled within the ADLC. |
|
3754 |
||
3755 |
//----------Conditional Branch Operands---------------------------------------- |
|
3756 |
// Comparison Op - This is the operation of the comparison, and is limited to |
|
3757 |
// the following set of codes: |
|
3758 |
// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) |
|
3759 |
// |
|
3760 |
// Other attributes of the comparison, such as unsignedness, are specified |
|
3761 |
// by the comparison instruction that sets a condition code flags register. |
|
3762 |
// That result is represented by a flags operand whose subtype is appropriate |
|
3763 |
// to the unsignedness (etc.) of the comparison. |
|
3764 |
// |
|
3765 |
// Later, the instruction which matches both the Comparison Op (a Bool) and |
|
3766 |
// the flags (produced by the Cmp) specifies the coding of the comparison op |
|
3767 |
// by matching a specific subtype of Bool operand below. |
|
3768 |
||
3769 |
// INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not |
|
3770 |
// have mask bit #3 set. |
|
3771 |
operand cmpOpT() %{
|
|
3772 |
match(Bool); |
|
3773 |
format %{ "" %}
|
|
3774 |
interface(COND_INTER) %{
|
|
3775 |
equal(0x8); // Assembler::bcondEqual |
|
3776 |
not_equal(0x6); // Assembler::bcondNotEqual |
|
3777 |
less(0x4); // Assembler::bcondLow |
|
3778 |
greater_equal(0xa); // Assembler::bcondNotLow |
|
3779 |
less_equal(0xc); // Assembler::bcondNotHigh |
|
3780 |
greater(0x2); // Assembler::bcondHigh |
|
3781 |
overflow(0x1); // Assembler::bcondOverflow |
|
3782 |
no_overflow(0xe); // Assembler::bcondNotOverflow |
|
3783 |
%} |
|
3784 |
%} |
|
3785 |
||
3786 |
// When used for floating point comparisons: unordered is treated as less. |
|
3787 |
operand cmpOpF() %{
|
|
3788 |
match(Bool); |
|
3789 |
format %{ "" %}
|
|
3790 |
interface(COND_INTER) %{
|
|
3791 |
equal(0x8); |
|
3792 |
not_equal(0x7); // Includes 'unordered'. |
|
3793 |
less(0x5); // Includes 'unordered'. |
|
3794 |
greater_equal(0xa); |
|
3795 |
less_equal(0xd); // Includes 'unordered'. |
|
3796 |
greater(0x2); |
|
3797 |
overflow(0x0); // Not meaningful on z/Architecture. |
|
3798 |
no_overflow(0x0); // leave unchanged (zero) therefore |
|
3799 |
%} |
|
3800 |
%} |
|
3801 |
||
3802 |
// "Regular" cmpOp for int comparisons, includes bit #3 (overflow). |
|
3803 |
operand cmpOp() %{
|
|
3804 |
match(Bool); |
|
3805 |
format %{ "" %}
|
|
3806 |
interface(COND_INTER) %{
|
|
3807 |
equal(0x8); |
|
3808 |
not_equal(0x7); // Includes 'unordered'. |
|
3809 |
less(0x5); // Includes 'unordered'. |
|
3810 |
greater_equal(0xa); |
|
3811 |
less_equal(0xd); // Includes 'unordered'. |
|
3812 |
greater(0x2); |
|
3813 |
overflow(0x1); // Assembler::bcondOverflow |
|
3814 |
no_overflow(0xe); // Assembler::bcondNotOverflow |
|
3815 |
%} |
|
3816 |
%} |
|
3817 |
||
3818 |
//----------OPERAND CLASSES---------------------------------------------------- |
|
3819 |
// Operand Classes are groups of operands that are used to simplify |
|
3820 |
// instruction definitions by not requiring the AD writer to specify |
|
3821 |
// seperate instructions for every form of operand when the |
|
3822 |
// instruction accepts multiple operand types with the same basic |
|
3823 |
// encoding and format. The classic case of this is memory operands. |
|
3824 |
// Indirect is not included since its use is limited to Compare & Swap |
|
3825 |
||
3826 |
// Most general memory operand, allows base, index, and long displacement. |
|
3827 |
opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow); |
|
3828 |
opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow); |
|
3829 |
||
3830 |
// General memory operand, allows base, index, and short displacement. |
|
3831 |
opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow); |
|
3832 |
||
3833 |
// Memory operand, allows only base and long displacement. |
|
3834 |
opclass memoryRSY(indirect, indOffset20, indOffset20Narrow); |
|
3835 |
||
3836 |
// Memory operand, allows only base and short displacement. |
|
3837 |
opclass memoryRS(indirect, indOffset12, indOffset12Narrow); |
|
3838 |
||
3839 |
// Operand classes to match encode and decode. |
|
3840 |
opclass iRegN_P2N(iRegN); |
|
3841 |
opclass iRegP_N2P(iRegP); |
|
3842 |
||
3843 |
||
3844 |
//----------PIPELINE----------------------------------------------------------- |
|
3845 |
pipeline %{
|
|
3846 |
||
3847 |
//----------ATTRIBUTES--------------------------------------------------------- |
|
3848 |
attributes %{
|
|
3849 |
// z/Architecture instructions are of length 2, 4, or 6 bytes. |
|
3850 |
variable_size_instructions; |
|
3851 |
instruction_unit_size = 2; |
|
3852 |
||
3853 |
// Meaningless on z/Architecture. |
|
3854 |
max_instructions_per_bundle = 1; |
|
3855 |
||
3856 |
// The z/Architecture processor fetches 64 bytes... |
|
3857 |
instruction_fetch_unit_size = 64; |
|
3858 |
||
3859 |
// ...in one line. |
|
3860 |
instruction_fetch_units = 1 |
|
3861 |
%} |
|
3862 |
||
3863 |
//----------RESOURCES---------------------------------------------------------- |
|
3864 |
// Resources are the functional units available to the machine. |
|
3865 |
resources( |
|
3866 |
Z_BR, // branch unit |
|
3867 |
Z_CR, // condition unit |
|
3868 |
Z_FX1, // integer arithmetic unit 1 |
|
3869 |
Z_FX2, // integer arithmetic unit 2 |
|
3870 |
Z_LDST1, // load/store unit 1 |
|
3871 |
Z_LDST2, // load/store unit 2 |
|
3872 |
Z_FP1, // float arithmetic unit 1 |
|
3873 |
Z_FP2, // float arithmetic unit 2 |
|
3874 |
Z_LDST = Z_LDST1 | Z_LDST2, |
|
3875 |
Z_FX = Z_FX1 | Z_FX2, |
|
3876 |
Z_FP = Z_FP1 | Z_FP2 |
|
3877 |
); |
|
3878 |
||
3879 |
//----------PIPELINE DESCRIPTION----------------------------------------------- |
|
3880 |
// Pipeline Description specifies the stages in the machine's pipeline. |
|
3881 |
pipe_desc( |
|
3882 |
// TODO: adapt |
|
3883 |
Z_IF, // instruction fetch |
|
3884 |
Z_IC, |
|
3885 |
Z_D0, // decode |
|
3886 |
Z_D1, // decode |
|
3887 |
Z_D2, // decode |
|
3888 |
Z_D3, // decode |
|
3889 |
Z_Xfer1, |
|
3890 |
Z_GD, // group definition |
|
3891 |
Z_MP, // map |
|
3892 |
Z_ISS, // issue |
|
3893 |
Z_RF, // resource fetch |
|
3894 |
Z_EX1, // execute (all units) |
|
3895 |
Z_EX2, // execute (FP, LDST) |
|
3896 |
Z_EX3, // execute (FP, LDST) |
|
3897 |
Z_EX4, // execute (FP) |
|
3898 |
Z_EX5, // execute (FP) |
|
3899 |
Z_EX6, // execute (FP) |
|
3900 |
Z_WB, // write back |
|
3901 |
Z_Xfer2, |
|
3902 |
Z_CP |
|
3903 |
); |
|
3904 |
||
3905 |
//----------PIPELINE CLASSES--------------------------------------------------- |
|
3906 |
// Pipeline Classes describe the stages in which input and output are |
|
3907 |
// referenced by the hardware pipeline. |
|
3908 |
||
3909 |
// Providing the `ins_pipe' declarations in the instruction |
|
3910 |
// specifications seems to be of little use. So we use |
|
3911 |
// `pipe_class_dummy' for all our instructions at present. |
|
3912 |
pipe_class pipe_class_dummy() %{
|
|
3913 |
single_instruction; |
|
3914 |
fixed_latency(4); |
|
3915 |
%} |
|
3916 |
||
3917 |
// SIGTRAP based implicit range checks in compiled code. |
|
3918 |
// Currently, no pipe classes are used on z/Architecture. |
|
3919 |
pipe_class pipe_class_trap() %{
|
|
3920 |
single_instruction; |
|
3921 |
%} |
|
3922 |
||
3923 |
pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
|
|
3924 |
single_instruction; |
|
3925 |
dst : Z_EX1(write); |
|
3926 |
src1 : Z_RF(read); |
|
3927 |
src2 : Z_RF(read); |
|
3928 |
Z_FX : Z_RF; |
|
3929 |
%} |
|
3930 |
||
3931 |
pipe_class pipe_class_ldst(iRegP dst, memory mem) %{
|
|
3932 |
single_instruction; |
|
3933 |
mem : Z_RF(read); |
|
3934 |
dst : Z_WB(write); |
|
3935 |
Z_LDST : Z_RF; |
|
3936 |
%} |
|
3937 |
||
3938 |
define %{
|
|
3939 |
MachNop = pipe_class_dummy; |
|
3940 |
%} |
|
3941 |
||
3942 |
%} |
|
3943 |
||
3944 |
//----------INSTRUCTIONS------------------------------------------------------- |
|
3945 |
||
3946 |
//---------- Chain stack slots between similar types -------- |
|
3947 |
||
3948 |
// Load integer from stack slot. |
|
3949 |
instruct stkI_to_regI(iRegI dst, stackSlotI src) %{
|
|
3950 |
match(Set dst src); |
|
3951 |
ins_cost(MEMORY_REF_COST); |
|
3952 |
// TODO: s390 port size(FIXED_SIZE); |
|
3953 |
format %{ "L $dst,$src\t # stk reload int" %}
|
|
3954 |
opcode(L_ZOPC); |
|
3955 |
ins_encode(z_form_rt_mem(dst, src)); |
|
3956 |
ins_pipe(pipe_class_dummy); |
|
3957 |
%} |
|
3958 |
||
3959 |
// Store integer to stack slot. |
|
3960 |
instruct regI_to_stkI(stackSlotI dst, iRegI src) %{
|
|
3961 |
match(Set dst src); |
|
3962 |
ins_cost(MEMORY_REF_COST); |
|
3963 |
// TODO: s390 port size(FIXED_SIZE); |
|
3964 |
format %{ "ST $src,$dst\t # stk spill int" %}
|
|
3965 |
opcode(ST_ZOPC); |
|
3966 |
ins_encode(z_form_rt_mem(src, dst)); // rs=rt |
|
3967 |
ins_pipe(pipe_class_dummy); |
|
3968 |
%} |
|
3969 |
||
3970 |
// Load long from stack slot. |
|
3971 |
instruct stkL_to_regL(iRegL dst, stackSlotL src) %{
|
|
3972 |
match(Set dst src); |
|
3973 |
ins_cost(MEMORY_REF_COST); |
|
3974 |
// TODO: s390 port size(FIXED_SIZE); |
|
3975 |
format %{ "LG $dst,$src\t # stk reload long" %}
|
|
3976 |
opcode(LG_ZOPC); |
|
3977 |
ins_encode(z_form_rt_mem(dst, src)); |
|
3978 |
ins_pipe(pipe_class_dummy); |
|
3979 |
%} |
|
3980 |
||
3981 |
// Store long to stack slot. |
|
3982 |
instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
|
|
3983 |
match(Set dst src); |
|
3984 |
ins_cost(MEMORY_REF_COST); |
|
3985 |
size(6); |
|
3986 |
format %{ "STG $src,$dst\t # stk spill long" %}
|
|
3987 |
opcode(STG_ZOPC); |
|
3988 |
ins_encode(z_form_rt_mem(src, dst)); // rs=rt |
|
3989 |
ins_pipe(pipe_class_dummy); |
|
3990 |
%} |
|
3991 |
||
3992 |
// Load pointer from stack slot, 64-bit encoding. |
|
3993 |
instruct stkP_to_regP(iRegP dst, stackSlotP src) %{
|
|
3994 |
match(Set dst src); |
|
3995 |
ins_cost(MEMORY_REF_COST); |
|
3996 |
// TODO: s390 port size(FIXED_SIZE); |
|
3997 |
format %{ "LG $dst,$src\t # stk reload ptr" %}
|
|
3998 |
opcode(LG_ZOPC); |
|
3999 |
ins_encode(z_form_rt_mem(dst, src)); |
|
4000 |
ins_pipe(pipe_class_dummy); |
|
4001 |
%} |
|
4002 |
||
4003 |
// Store pointer to stack slot. |
|
4004 |
instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
|
|
4005 |
match(Set dst src); |
|
4006 |
ins_cost(MEMORY_REF_COST); |
|
4007 |
// TODO: s390 port size(FIXED_SIZE); |
|
4008 |
format %{ "STG $src,$dst\t # stk spill ptr" %}
|
|
4009 |
opcode(STG_ZOPC); |
|
4010 |
ins_encode(z_form_rt_mem(src, dst)); // rs=rt |
|
4011 |
ins_pipe(pipe_class_dummy); |
|
4012 |
%} |
|
4013 |
||
4014 |
// Float types |
|
4015 |
||
4016 |
// Load float value from stack slot. |
|
4017 |
instruct stkF_to_regF(regF dst, stackSlotF src) %{
|
|
4018 |
match(Set dst src); |
|
4019 |
ins_cost(MEMORY_REF_COST); |
|
4020 |
size(4); |
|
4021 |
format %{ "LE(Y) $dst,$src\t # stk reload float" %}
|
|
4022 |
opcode(LE_ZOPC); |
|
4023 |
ins_encode(z_form_rt_mem(dst, src)); |
|
4024 |
ins_pipe(pipe_class_dummy); |
|
4025 |
%} |
|
4026 |
||
4027 |
// Store float value to stack slot. |
|
4028 |
instruct regF_to_stkF(stackSlotF dst, regF src) %{
|
|
4029 |
match(Set dst src); |
|
4030 |
ins_cost(MEMORY_REF_COST); |
|
4031 |
size(4); |
|
4032 |
format %{ "STE(Y) $src,$dst\t # stk spill float" %}
|
|
4033 |
opcode(STE_ZOPC); |
|
4034 |
ins_encode(z_form_rt_mem(src, dst)); |
|
4035 |
ins_pipe(pipe_class_dummy); |
|
4036 |
%} |
|
4037 |
||
4038 |
// Load double value from stack slot. |
|
4039 |
instruct stkD_to_regD(regD dst, stackSlotD src) %{
|
|
4040 |
match(Set dst src); |
|
4041 |
ins_cost(MEMORY_REF_COST); |
|
4042 |
// TODO: s390 port size(FIXED_SIZE); |
|
4043 |
format %{ "LD(Y) $dst,$src\t # stk reload double" %}
|
|
4044 |
opcode(LD_ZOPC); |
|
4045 |
ins_encode(z_form_rt_mem(dst, src)); |
|
4046 |
ins_pipe(pipe_class_dummy); |
|
4047 |
%} |
|
4048 |
||
4049 |
// Store double value to stack slot. |
|
4050 |
instruct regD_to_stkD(stackSlotD dst, regD src) %{
|
|
4051 |
match(Set dst src); |
|
4052 |
ins_cost(MEMORY_REF_COST); |
|
4053 |
size(4); |
|
4054 |
format %{ "STD(Y) $src,$dst\t # stk spill double" %}
|
|
4055 |
opcode(STD_ZOPC); |
|
4056 |
ins_encode(z_form_rt_mem(src, dst)); |
|
4057 |
ins_pipe(pipe_class_dummy); |
|
4058 |
%} |
|
4059 |
||
4060 |
//----------Load/Store/Move Instructions--------------------------------------- |
|
4061 |
||
4062 |
//----------Load Instructions-------------------------------------------------- |
|
4063 |
||
4064 |
//------------------ |
|
4065 |
// MEMORY |
|
4066 |
//------------------ |
|
4067 |
||
4068 |
// BYTE |
|
4069 |
// Load Byte (8bit signed) |
|
4070 |
instruct loadB(iRegI dst, memory mem) %{
|
|
4071 |
match(Set dst (LoadB mem)); |
|
4072 |
ins_cost(MEMORY_REF_COST); |
|
4073 |
size(Z_DISP3_SIZE); |
|
4074 |
format %{ "LB $dst, $mem\t # sign-extend byte to int" %}
|
|
4075 |
opcode(LB_ZOPC, LB_ZOPC); |
|
4076 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4077 |
ins_pipe(pipe_class_dummy); |
|
4078 |
%} |
|
4079 |
||
4080 |
// Load Byte (8bit signed) |
|
4081 |
instruct loadB2L(iRegL dst, memory mem) %{
|
|
4082 |
match(Set dst (ConvI2L (LoadB mem))); |
|
4083 |
ins_cost(MEMORY_REF_COST); |
|
4084 |
size(Z_DISP3_SIZE); |
|
4085 |
format %{ "LGB $dst, $mem\t # sign-extend byte to long" %}
|
|
4086 |
opcode(LGB_ZOPC, LGB_ZOPC); |
|
4087 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4088 |
ins_pipe(pipe_class_dummy); |
|
4089 |
%} |
|
4090 |
||
4091 |
// Load Unsigned Byte (8bit UNsigned) into an int reg. |
|
4092 |
instruct loadUB(iRegI dst, memory mem) %{
|
|
4093 |
match(Set dst (LoadUB mem)); |
|
4094 |
ins_cost(MEMORY_REF_COST); |
|
4095 |
size(Z_DISP3_SIZE); |
|
4096 |
format %{ "LLGC $dst,$mem\t # zero-extend byte to int" %}
|
|
4097 |
opcode(LLGC_ZOPC, LLGC_ZOPC); |
|
4098 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4099 |
ins_pipe(pipe_class_dummy); |
|
4100 |
%} |
|
4101 |
||
4102 |
// Load Unsigned Byte (8bit UNsigned) into a Long Register. |
|
4103 |
instruct loadUB2L(iRegL dst, memory mem) %{
|
|
4104 |
match(Set dst (ConvI2L (LoadUB mem))); |
|
4105 |
ins_cost(MEMORY_REF_COST); |
|
4106 |
size(Z_DISP3_SIZE); |
|
4107 |
format %{ "LLGC $dst,$mem\t # zero-extend byte to long" %}
|
|
4108 |
opcode(LLGC_ZOPC, LLGC_ZOPC); |
|
4109 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4110 |
ins_pipe(pipe_class_dummy); |
|
4111 |
%} |
|
4112 |
||
4113 |
// CHAR/SHORT |
|
4114 |
||
4115 |
// Load Short (16bit signed) |
|
4116 |
instruct loadS(iRegI dst, memory mem) %{
|
|
4117 |
match(Set dst (LoadS mem)); |
|
4118 |
ins_cost(MEMORY_REF_COST); |
|
4119 |
size(Z_DISP_SIZE); |
|
4120 |
format %{ "LH(Y) $dst,$mem\t # sign-extend short to int" %}
|
|
4121 |
opcode(LHY_ZOPC, LH_ZOPC); |
|
4122 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4123 |
ins_pipe(pipe_class_dummy); |
|
4124 |
%} |
|
4125 |
||
4126 |
// Load Short (16bit signed) |
|
4127 |
instruct loadS2L(iRegL dst, memory mem) %{
|
|
4128 |
match(Set dst (ConvI2L (LoadS mem))); |
|
4129 |
ins_cost(MEMORY_REF_COST); |
|
4130 |
size(Z_DISP3_SIZE); |
|
4131 |
format %{ "LGH $dst,$mem\t # sign-extend short to long" %}
|
|
4132 |
opcode(LGH_ZOPC, LGH_ZOPC); |
|
4133 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4134 |
ins_pipe(pipe_class_dummy); |
|
4135 |
%} |
|
4136 |
||
4137 |
// Load Char (16bit Unsigned) |
|
4138 |
instruct loadUS(iRegI dst, memory mem) %{
|
|
4139 |
match(Set dst (LoadUS mem)); |
|
4140 |
ins_cost(MEMORY_REF_COST); |
|
4141 |
size(Z_DISP3_SIZE); |
|
4142 |
format %{ "LLGH $dst,$mem\t # zero-extend short to int" %}
|
|
4143 |
opcode(LLGH_ZOPC, LLGH_ZOPC); |
|
4144 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4145 |
ins_pipe(pipe_class_dummy); |
|
4146 |
%} |
|
4147 |
||
4148 |
// Load Unsigned Short/Char (16bit UNsigned) into a Long Register. |
|
4149 |
instruct loadUS2L(iRegL dst, memory mem) %{
|
|
4150 |
match(Set dst (ConvI2L (LoadUS mem))); |
|
4151 |
ins_cost(MEMORY_REF_COST); |
|
4152 |
size(Z_DISP3_SIZE); |
|
4153 |
format %{ "LLGH $dst,$mem\t # zero-extend short to long" %}
|
|
4154 |
opcode(LLGH_ZOPC, LLGH_ZOPC); |
|
4155 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4156 |
ins_pipe(pipe_class_dummy); |
|
4157 |
%} |
|
4158 |
||
4159 |
// INT |
|
4160 |
||
4161 |
// Load Integer |
|
4162 |
instruct loadI(iRegI dst, memory mem) %{
|
|
4163 |
match(Set dst (LoadI mem)); |
|
4164 |
ins_cost(MEMORY_REF_COST); |
|
4165 |
size(Z_DISP_SIZE); |
|
4166 |
format %{ "L(Y) $dst,$mem\t #" %}
|
|
4167 |
opcode(LY_ZOPC, L_ZOPC); |
|
4168 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4169 |
ins_pipe(pipe_class_dummy); |
|
4170 |
%} |
|
4171 |
||
4172 |
// Load and convert to long. |
|
4173 |
instruct loadI2L(iRegL dst, memory mem) %{
|
|
4174 |
match(Set dst (ConvI2L (LoadI mem))); |
|
4175 |
ins_cost(MEMORY_REF_COST); |
|
4176 |
size(Z_DISP3_SIZE); |
|
4177 |
format %{ "LGF $dst,$mem\t #" %}
|
|
4178 |
opcode(LGF_ZOPC, LGF_ZOPC); |
|
4179 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4180 |
ins_pipe(pipe_class_dummy); |
|
4181 |
%} |
|
4182 |
||
4183 |
// Load Unsigned Integer into a Long Register |
|
4184 |
instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{
|
|
4185 |
match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); |
|
4186 |
ins_cost(MEMORY_REF_COST); |
|
4187 |
size(Z_DISP3_SIZE); |
|
4188 |
format %{ "LLGF $dst,$mem\t # zero-extend int to long" %}
|
|
4189 |
opcode(LLGF_ZOPC, LLGF_ZOPC); |
|
4190 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4191 |
ins_pipe(pipe_class_dummy); |
|
4192 |
%} |
|
4193 |
||
4194 |
// range = array length (=jint) |
|
4195 |
// Load Range |
|
4196 |
instruct loadRange(iRegI dst, memory mem) %{
|
|
4197 |
match(Set dst (LoadRange mem)); |
|
4198 |
ins_cost(MEMORY_REF_COST); |
|
4199 |
size(Z_DISP_SIZE); |
|
4200 |
format %{ "L(Y) $dst,$mem\t # range" %}
|
|
4201 |
opcode(LY_ZOPC, L_ZOPC); |
|
4202 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4203 |
ins_pipe(pipe_class_dummy); |
|
4204 |
%} |
|
4205 |
||
4206 |
// LONG |
|
4207 |
||
4208 |
// Load Long - aligned |
|
4209 |
instruct loadL(iRegL dst, memory mem) %{
|
|
4210 |
match(Set dst (LoadL mem)); |
|
4211 |
ins_cost(MEMORY_REF_COST); |
|
4212 |
size(Z_DISP3_SIZE); |
|
4213 |
format %{ "LG $dst,$mem\t # long" %}
|
|
4214 |
opcode(LG_ZOPC, LG_ZOPC); |
|
4215 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4216 |
ins_pipe(pipe_class_dummy); |
|
4217 |
%} |
|
4218 |
||
4219 |
// Load Long - UNaligned |
|
4220 |
instruct loadL_unaligned(iRegL dst, memory mem) %{
|
|
4221 |
match(Set dst (LoadL_unaligned mem)); |
|
4222 |
ins_cost(MEMORY_REF_COST); |
|
4223 |
size(Z_DISP3_SIZE); |
|
4224 |
format %{ "LG $dst,$mem\t # unaligned long" %}
|
|
4225 |
opcode(LG_ZOPC, LG_ZOPC); |
|
4226 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4227 |
ins_pipe(pipe_class_dummy); |
|
4228 |
%} |
|
4229 |
||
4230 |
||
4231 |
// PTR |
|
4232 |
||
4233 |
// Load Pointer |
|
4234 |
instruct loadP(iRegP dst, memory mem) %{
|
|
4235 |
match(Set dst (LoadP mem)); |
|
4236 |
ins_cost(MEMORY_REF_COST); |
|
4237 |
size(Z_DISP3_SIZE); |
|
4238 |
format %{ "LG $dst,$mem\t # ptr" %}
|
|
4239 |
opcode(LG_ZOPC, LG_ZOPC); |
|
4240 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4241 |
ins_pipe(pipe_class_dummy); |
|
4242 |
%} |
|
4243 |
||
4244 |
// LoadP + CastP2L |
|
4245 |
instruct castP2X_loadP(iRegL dst, memory mem) %{
|
|
4246 |
match(Set dst (CastP2X (LoadP mem))); |
|
4247 |
ins_cost(MEMORY_REF_COST); |
|
4248 |
size(Z_DISP3_SIZE); |
|
4249 |
format %{ "LG $dst,$mem\t # ptr + p2x" %}
|
|
4250 |
opcode(LG_ZOPC, LG_ZOPC); |
|
4251 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4252 |
ins_pipe(pipe_class_dummy); |
|
4253 |
%} |
|
4254 |
||
4255 |
// Load Klass Pointer |
|
4256 |
instruct loadKlass(iRegP dst, memory mem) %{
|
|
4257 |
match(Set dst (LoadKlass mem)); |
|
4258 |
ins_cost(MEMORY_REF_COST); |
|
4259 |
size(Z_DISP3_SIZE); |
|
4260 |
format %{ "LG $dst,$mem\t # klass ptr" %}
|
|
4261 |
opcode(LG_ZOPC, LG_ZOPC); |
|
4262 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4263 |
ins_pipe(pipe_class_dummy); |
|
4264 |
%} |
|
4265 |
||
4266 |
instruct loadTOC(iRegL dst) %{
|
|
4267 |
effect(DEF dst); |
|
4268 |
ins_cost(DEFAULT_COST); |
|
4269 |
// TODO: s390 port size(FIXED_SIZE); |
|
4270 |
// TODO: check why this attribute causes many unnecessary rematerializations. |
|
4271 |
// |
|
4272 |
// The graphs I saw just had high register pressure. Further the |
|
4273 |
// register TOC is loaded to is overwritten by the constant short |
|
4274 |
// after. Here something as round robin register allocation might |
|
4275 |
// help. But rematerializing seems not to hurt, jack even seems to |
|
4276 |
// improve slightly. |
|
4277 |
// |
|
4278 |
// Without this flag we get spill-split recycle sanity check |
|
4279 |
// failures in |
|
4280 |
// spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in |
|
4281 |
// a block with three loadConP_dynTOC nodes and a tlsLoadP. The |
|
4282 |
// tlsLoadP has a huge amount of outs and forces the TOC down to the |
|
4283 |
// stack. Later tlsLoadP is rematerialized, leaving the register |
|
4284 |
// allocator with TOC on the stack and a badly placed reload. |
|
4285 |
ins_should_rematerialize(true); |
|
4286 |
format %{ "LARL $dst, &constant_pool\t; load dynTOC" %}
|
|
4287 |
ins_encode %{ __ load_toc($dst$$Register); %}
|
|
4288 |
ins_pipe(pipe_class_dummy); |
|
4289 |
%} |
|
4290 |
||
4291 |
// FLOAT |
|
4292 |
||
4293 |
// Load Float |
|
4294 |
instruct loadF(regF dst, memory mem) %{
|
|
4295 |
match(Set dst (LoadF mem)); |
|
4296 |
ins_cost(MEMORY_REF_COST); |
|
4297 |
size(Z_DISP_SIZE); |
|
4298 |
format %{ "LE(Y) $dst,$mem" %}
|
|
4299 |
opcode(LEY_ZOPC, LE_ZOPC); |
|
4300 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4301 |
ins_pipe(pipe_class_dummy); |
|
4302 |
%} |
|
4303 |
||
4304 |
// DOUBLE |
|
4305 |
||
4306 |
// Load Double |
|
4307 |
instruct loadD(regD dst, memory mem) %{
|
|
4308 |
match(Set dst (LoadD mem)); |
|
4309 |
ins_cost(MEMORY_REF_COST); |
|
4310 |
size(Z_DISP_SIZE); |
|
4311 |
format %{ "LD(Y) $dst,$mem" %}
|
|
4312 |
opcode(LDY_ZOPC, LD_ZOPC); |
|
4313 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4314 |
ins_pipe(pipe_class_dummy); |
|
4315 |
%} |
|
4316 |
||
4317 |
// Load Double - UNaligned |
|
4318 |
instruct loadD_unaligned(regD dst, memory mem) %{
|
|
4319 |
match(Set dst (LoadD_unaligned mem)); |
|
4320 |
ins_cost(MEMORY_REF_COST); |
|
4321 |
size(Z_DISP_SIZE); |
|
4322 |
format %{ "LD(Y) $dst,$mem" %}
|
|
4323 |
opcode(LDY_ZOPC, LD_ZOPC); |
|
4324 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4325 |
ins_pipe(pipe_class_dummy); |
|
4326 |
%} |
|
4327 |
||
4328 |
||
4329 |
//---------------------- |
|
4330 |
// IMMEDIATES |
|
4331 |
//---------------------- |
|
4332 |
||
4333 |
instruct loadConI(iRegI dst, immI src) %{
|
|
4334 |
match(Set dst src); |
|
4335 |
ins_cost(DEFAULT_COST); |
|
4336 |
size(6); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4337 |
format %{ "LGFI $dst,$src\t # (int)" %}
|
| 42065 | 4338 |
ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
|
4339 |
ins_pipe(pipe_class_dummy); |
|
4340 |
%} |
|
4341 |
||
4342 |
instruct loadConI16(iRegI dst, immI16 src) %{
|
|
4343 |
match(Set dst src); |
|
4344 |
ins_cost(DEFAULT_COST_LOW); |
|
4345 |
size(4); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4346 |
format %{ "LGHI $dst,$src\t # (int)" %}
|
| 42065 | 4347 |
ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
|
4348 |
ins_pipe(pipe_class_dummy); |
|
4349 |
%} |
|
4350 |
||
4351 |
instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
|
|
4352 |
match(Set dst src); |
|
4353 |
effect(KILL cr); |
|
4354 |
ins_cost(DEFAULT_COST_LOW); |
|
4355 |
size(4); |
|
4356 |
format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %}
|
|
4357 |
opcode(XGR_ZOPC); |
|
4358 |
ins_encode(z_rreform(dst, dst)); |
|
4359 |
ins_pipe(pipe_class_dummy); |
|
4360 |
%} |
|
4361 |
||
4362 |
instruct loadConUI16(iRegI dst, uimmI16 src) %{
|
|
4363 |
match(Set dst src); |
|
4364 |
// TODO: s390 port size(FIXED_SIZE); |
|
4365 |
format %{ "LLILL $dst,$src" %}
|
|
4366 |
opcode(LLILL_ZOPC); |
|
4367 |
ins_encode(z_riform_unsigned(dst, src) ); |
|
4368 |
ins_pipe(pipe_class_dummy); |
|
4369 |
%} |
|
4370 |
||
4371 |
// Load long constant from TOC with pcrelative address. |
|
4372 |
instruct loadConL_pcrelTOC(iRegL dst, immL src) %{
|
|
4373 |
match(Set dst src); |
|
4374 |
ins_cost(MEMORY_REF_COST_LO); |
|
4375 |
size(6); |
|
4376 |
format %{ "LGRL $dst,[pcrelTOC]\t # load long $src from table" %}
|
|
4377 |
ins_encode %{
|
|
4378 |
address long_address = __ long_constant($src$$constant); |
|
4379 |
if (long_address == NULL) {
|
|
4380 |
Compile::current()->env()->record_out_of_memory_failure(); |
|
4381 |
return; |
|
4382 |
} |
|
4383 |
__ load_long_pcrelative($dst$$Register, long_address); |
|
4384 |
%} |
|
4385 |
ins_pipe(pipe_class_dummy); |
|
4386 |
%} |
|
4387 |
||
4388 |
instruct loadConL32(iRegL dst, immL32 src) %{
|
|
4389 |
match(Set dst src); |
|
4390 |
ins_cost(DEFAULT_COST); |
|
4391 |
size(6); |
|
4392 |
format %{ "LGFI $dst,$src\t # (long)" %}
|
|
4393 |
ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
|
|
4394 |
ins_pipe(pipe_class_dummy); |
|
4395 |
%} |
|
4396 |
||
4397 |
instruct loadConL16(iRegL dst, immL16 src) %{
|
|
4398 |
match(Set dst src); |
|
4399 |
ins_cost(DEFAULT_COST_LOW); |
|
4400 |
size(4); |
|
4401 |
format %{ "LGHI $dst,$src\t # (long)" %}
|
|
4402 |
ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
|
|
4403 |
ins_pipe(pipe_class_dummy); |
|
4404 |
%} |
|
4405 |
||
4406 |
instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{
|
|
4407 |
match(Set dst src); |
|
4408 |
effect(KILL cr); |
|
4409 |
ins_cost(DEFAULT_COST_LOW); |
|
4410 |
format %{ "LoadConL $dst,$src\t # (long) XGR because ZERO is loaded" %}
|
|
4411 |
opcode(XGR_ZOPC); |
|
4412 |
ins_encode(z_rreform(dst, dst)); |
|
4413 |
ins_pipe(pipe_class_dummy); |
|
4414 |
%} |
|
4415 |
||
4416 |
// Load ptr constant from TOC with pc relative address. |
|
4417 |
// Special handling for oop constants required. |
|
4418 |
instruct loadConP_pcrelTOC(iRegP dst, immP src) %{
|
|
4419 |
match(Set dst src); |
|
4420 |
ins_cost(MEMORY_REF_COST_LO); |
|
4421 |
size(6); |
|
4422 |
format %{ "LGRL $dst,[pcrelTOC]\t # load ptr $src from table" %}
|
|
4423 |
ins_encode %{
|
|
4424 |
relocInfo::relocType constant_reloc = $src->constant_reloc(); |
|
4425 |
if (constant_reloc == relocInfo::oop_type) {
|
|
4426 |
AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant); |
|
4427 |
bool success = __ load_oop_from_toc($dst$$Register, a); |
|
4428 |
if (!success) {
|
|
4429 |
Compile::current()->env()->record_out_of_memory_failure(); |
|
4430 |
return; |
|
4431 |
} |
|
4432 |
} else if (constant_reloc == relocInfo::metadata_type) {
|
|
4433 |
AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant); |
|
4434 |
address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); |
|
4435 |
if (const_toc_addr == NULL) {
|
|
4436 |
Compile::current()->env()->record_out_of_memory_failure(); |
|
4437 |
return; |
|
4438 |
} |
|
4439 |
__ load_long_pcrelative($dst$$Register, const_toc_addr); |
|
4440 |
} else { // Non-oop pointers, e.g. card mark base, heap top.
|
|
4441 |
address long_address = __ long_constant((jlong)$src$$constant); |
|
4442 |
if (long_address == NULL) {
|
|
4443 |
Compile::current()->env()->record_out_of_memory_failure(); |
|
4444 |
return; |
|
4445 |
} |
|
4446 |
__ load_long_pcrelative($dst$$Register, long_address); |
|
4447 |
} |
|
4448 |
%} |
|
4449 |
ins_pipe(pipe_class_dummy); |
|
4450 |
%} |
|
4451 |
||
4452 |
// We don't use immP16 to avoid problems with oops. |
|
4453 |
instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{
|
|
4454 |
match(Set dst src); |
|
4455 |
effect(KILL cr); |
|
4456 |
size(4); |
|
4457 |
format %{ "XGR $dst,$dst\t # NULL ptr" %}
|
|
4458 |
opcode(XGR_ZOPC); |
|
4459 |
ins_encode(z_rreform(dst, dst)); |
|
4460 |
ins_pipe(pipe_class_dummy); |
|
4461 |
%} |
|
4462 |
||
4463 |
//----------Load Float Constant Instructions------------------------------------------------- |
|
4464 |
||
4465 |
// We may not specify this instruction via an `expand' rule. If we do, |
|
4466 |
// code selection will forget that this instruction needs a floating |
|
4467 |
// point constant inserted into the code buffer. So `Shorten_branches' |
|
4468 |
// will fail. |
|
4469 |
instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{
|
|
4470 |
match(Set dst src); |
|
4471 |
effect(KILL cr); |
|
4472 |
ins_cost(MEMORY_REF_COST); |
|
4473 |
size(6); |
|
4474 |
// If this instruction rematerializes, it prolongs the live range |
|
4475 |
// of the toc node, causing illegal graphs. |
|
4476 |
ins_cannot_rematerialize(true); |
|
4477 |
format %{ "LE(Y) $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %}
|
|
4478 |
ins_encode %{
|
|
4479 |
__ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch); |
|
4480 |
%} |
|
4481 |
ins_pipe(pipe_class_dummy); |
|
4482 |
%} |
|
4483 |
||
4484 |
// E may not specify this instruction via an `expand' rule. If we do, |
|
4485 |
// code selection will forget that this instruction needs a floating |
|
4486 |
// point constant inserted into the code buffer. So `Shorten_branches' |
|
4487 |
// will fail. |
|
4488 |
instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{
|
|
4489 |
match(Set dst src); |
|
4490 |
effect(KILL cr); |
|
4491 |
ins_cost(MEMORY_REF_COST); |
|
4492 |
size(6); |
|
4493 |
// If this instruction rematerializes, it prolongs the live range |
|
4494 |
// of the toc node, causing illegal graphs. |
|
4495 |
ins_cannot_rematerialize(true); |
|
4496 |
format %{ "LD(Y) $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %}
|
|
4497 |
ins_encode %{
|
|
4498 |
__ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch); |
|
4499 |
%} |
|
4500 |
ins_pipe(pipe_class_dummy); |
|
4501 |
%} |
|
4502 |
||
4503 |
// Special case: Load Const 0.0F |
|
4504 |
||
4505 |
// There's a special instr to clear a FP register. |
|
4506 |
instruct loadConF0(regF dst, immFp0 src) %{
|
|
4507 |
match(Set dst src); |
|
4508 |
ins_cost(DEFAULT_COST_LOW); |
|
4509 |
size(4); |
|
4510 |
format %{ "LZER $dst,$src\t # clear to zero" %}
|
|
4511 |
opcode(LZER_ZOPC); |
|
4512 |
ins_encode(z_rreform(dst, Z_F0)); |
|
4513 |
ins_pipe(pipe_class_dummy); |
|
4514 |
%} |
|
4515 |
||
4516 |
// There's a special instr to clear a FP register. |
|
4517 |
instruct loadConD0(regD dst, immDp0 src) %{
|
|
4518 |
match(Set dst src); |
|
4519 |
ins_cost(DEFAULT_COST_LOW); |
|
4520 |
size(4); |
|
4521 |
format %{ "LZDR $dst,$src\t # clear to zero" %}
|
|
4522 |
opcode(LZDR_ZOPC); |
|
4523 |
ins_encode(z_rreform(dst, Z_F0)); |
|
4524 |
ins_pipe(pipe_class_dummy); |
|
4525 |
%} |
|
4526 |
||
4527 |
||
4528 |
//----------Store Instructions------------------------------------------------- |
|
4529 |
||
4530 |
// BYTE |
|
4531 |
||
4532 |
// Store Byte |
|
4533 |
instruct storeB(memory mem, iRegI src) %{
|
|
4534 |
match(Set mem (StoreB mem src)); |
|
4535 |
ins_cost(MEMORY_REF_COST); |
|
4536 |
size(Z_DISP_SIZE); |
|
4537 |
format %{ "STC(Y) $src,$mem\t # byte" %}
|
|
4538 |
opcode(STCY_ZOPC, STC_ZOPC); |
|
4539 |
ins_encode(z_form_rt_mem_opt(src, mem)); |
|
4540 |
ins_pipe(pipe_class_dummy); |
|
4541 |
%} |
|
4542 |
||
4543 |
instruct storeCM(memory mem, immI_0 src) %{
|
|
4544 |
match(Set mem (StoreCM mem src)); |
|
4545 |
ins_cost(MEMORY_REF_COST); |
|
4546 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
4547 |
format %{ "STC(Y) $src,$mem\t # CMS card-mark byte (must be 0!)" %}
|
|
4548 |
ins_encode %{
|
|
4549 |
guarantee($mem$$index$$Register != Z_R0, "content will not be used."); |
|
4550 |
if ($mem$$index$$Register != noreg) {
|
|
4551 |
// Can't use clear_mem --> load const zero and store character. |
|
4552 |
__ load_const_optimized(Z_R0_scratch, (long)0); |
|
4553 |
if (Immediate::is_uimm12($mem$$disp)) {
|
|
4554 |
__ z_stc(Z_R0_scratch, $mem$$Address); |
|
4555 |
} else {
|
|
4556 |
__ z_stcy(Z_R0_scratch, $mem$$Address); |
|
4557 |
} |
|
4558 |
} else {
|
|
4559 |
__ clear_mem(Address($mem$$Address), 1); |
|
4560 |
} |
|
4561 |
%} |
|
4562 |
ins_pipe(pipe_class_dummy); |
|
4563 |
%} |
|
4564 |
||
4565 |
// CHAR/SHORT |
|
4566 |
||
4567 |
// Store Char/Short |
|
4568 |
instruct storeC(memory mem, iRegI src) %{
|
|
4569 |
match(Set mem (StoreC mem src)); |
|
4570 |
ins_cost(MEMORY_REF_COST); |
|
4571 |
size(Z_DISP_SIZE); |
|
4572 |
format %{ "STH(Y) $src,$mem\t # short" %}
|
|
4573 |
opcode(STHY_ZOPC, STH_ZOPC); |
|
4574 |
ins_encode(z_form_rt_mem_opt(src, mem)); |
|
4575 |
ins_pipe(pipe_class_dummy); |
|
4576 |
%} |
|
4577 |
||
4578 |
// INT |
|
4579 |
||
4580 |
// Store Integer |
|
4581 |
instruct storeI(memory mem, iRegI src) %{
|
|
4582 |
match(Set mem (StoreI mem src)); |
|
4583 |
ins_cost(MEMORY_REF_COST); |
|
4584 |
size(Z_DISP_SIZE); |
|
4585 |
format %{ "ST(Y) $src,$mem\t # int" %}
|
|
4586 |
opcode(STY_ZOPC, ST_ZOPC); |
|
4587 |
ins_encode(z_form_rt_mem_opt(src, mem)); |
|
4588 |
ins_pipe(pipe_class_dummy); |
|
4589 |
%} |
|
4590 |
||
4591 |
// LONG |
|
4592 |
||
4593 |
// Store Long |
|
4594 |
instruct storeL(memory mem, iRegL src) %{
|
|
4595 |
match(Set mem (StoreL mem src)); |
|
4596 |
ins_cost(MEMORY_REF_COST); |
|
4597 |
size(Z_DISP3_SIZE); |
|
4598 |
format %{ "STG $src,$mem\t # long" %}
|
|
4599 |
opcode(STG_ZOPC, STG_ZOPC); |
|
4600 |
ins_encode(z_form_rt_mem_opt(src, mem)); |
|
4601 |
ins_pipe(pipe_class_dummy); |
|
4602 |
%} |
|
4603 |
||
4604 |
// PTR |
|
4605 |
||
4606 |
// Store Pointer |
|
4607 |
instruct storeP(memory dst, memoryRegP src) %{
|
|
4608 |
match(Set dst (StoreP dst src)); |
|
4609 |
ins_cost(MEMORY_REF_COST); |
|
4610 |
size(Z_DISP3_SIZE); |
|
4611 |
format %{ "STG $src,$dst\t # ptr" %}
|
|
4612 |
opcode(STG_ZOPC, STG_ZOPC); |
|
4613 |
ins_encode(z_form_rt_mem_opt(src, dst)); |
|
4614 |
ins_pipe(pipe_class_dummy); |
|
4615 |
%} |
|
4616 |
||
4617 |
// FLOAT |
|
4618 |
||
4619 |
// Store Float |
|
4620 |
instruct storeF(memory mem, regF src) %{
|
|
4621 |
match(Set mem (StoreF mem src)); |
|
4622 |
ins_cost(MEMORY_REF_COST); |
|
4623 |
size(Z_DISP_SIZE); |
|
4624 |
format %{ "STE(Y) $src,$mem\t # float" %}
|
|
4625 |
opcode(STEY_ZOPC, STE_ZOPC); |
|
4626 |
ins_encode(z_form_rt_mem_opt(src, mem)); |
|
4627 |
ins_pipe(pipe_class_dummy); |
|
4628 |
%} |
|
4629 |
||
4630 |
// DOUBLE |
|
4631 |
||
4632 |
// Store Double |
|
4633 |
instruct storeD(memory mem, regD src) %{
|
|
4634 |
match(Set mem (StoreD mem src)); |
|
4635 |
ins_cost(MEMORY_REF_COST); |
|
4636 |
size(Z_DISP_SIZE); |
|
4637 |
format %{ "STD(Y) $src,$mem\t # double" %}
|
|
4638 |
opcode(STDY_ZOPC, STD_ZOPC); |
|
4639 |
ins_encode(z_form_rt_mem_opt(src, mem)); |
|
4640 |
ins_pipe(pipe_class_dummy); |
|
4641 |
%} |
|
4642 |
||
4643 |
// Prefetch instructions. Must be safe to execute with invalid address (cannot fault). |
|
4644 |
||
4645 |
// Should support match rule for PrefetchAllocation. |
|
4646 |
// Still needed after 8068977 for PrefetchAllocate. |
|
4647 |
instruct prefetchAlloc(memory mem) %{
|
|
4648 |
match(PrefetchAllocation mem); |
|
4649 |
predicate(VM_Version::has_Prefetch()); |
|
4650 |
ins_cost(DEFAULT_COST); |
|
4651 |
format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %}
|
|
4652 |
ins_encode %{ __ z_pfd(0x02, $mem$$Address); %}
|
|
4653 |
ins_pipe(pipe_class_dummy); |
|
4654 |
%} |
|
4655 |
||
4656 |
//----------Memory init instructions------------------------------------------ |
|
4657 |
||
4658 |
// Move Immediate to 1-byte memory. |
|
4659 |
instruct memInitB(memoryRSY mem, immI8 src) %{
|
|
4660 |
match(Set mem (StoreB mem src)); |
|
4661 |
ins_cost(MEMORY_REF_COST); |
|
4662 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
4663 |
format %{ "MVI $mem,$src\t # direct mem init 1" %}
|
|
4664 |
ins_encode %{
|
|
4665 |
if (Immediate::is_uimm12((long)$mem$$disp)) {
|
|
4666 |
__ z_mvi($mem$$Address, $src$$constant); |
|
4667 |
} else {
|
|
4668 |
__ z_mviy($mem$$Address, $src$$constant); |
|
4669 |
} |
|
4670 |
%} |
|
4671 |
ins_pipe(pipe_class_dummy); |
|
4672 |
%} |
|
4673 |
||
4674 |
// Move Immediate to 2-byte memory. |
|
4675 |
instruct memInitC(memoryRS mem, immI16 src) %{
|
|
4676 |
match(Set mem (StoreC mem src)); |
|
4677 |
ins_cost(MEMORY_REF_COST); |
|
4678 |
size(6); |
|
4679 |
format %{ "MVHHI $mem,$src\t # direct mem init 2" %}
|
|
4680 |
opcode(MVHHI_ZOPC); |
|
4681 |
ins_encode(z_silform(mem, src)); |
|
4682 |
ins_pipe(pipe_class_dummy); |
|
4683 |
%} |
|
4684 |
||
4685 |
// Move Immediate to 4-byte memory. |
|
4686 |
instruct memInitI(memoryRS mem, immI16 src) %{
|
|
4687 |
match(Set mem (StoreI mem src)); |
|
4688 |
ins_cost(MEMORY_REF_COST); |
|
4689 |
size(6); |
|
4690 |
format %{ "MVHI $mem,$src\t # direct mem init 4" %}
|
|
4691 |
opcode(MVHI_ZOPC); |
|
4692 |
ins_encode(z_silform(mem, src)); |
|
4693 |
ins_pipe(pipe_class_dummy); |
|
4694 |
%} |
|
4695 |
||
4696 |
||
4697 |
// Move Immediate to 8-byte memory. |
|
4698 |
instruct memInitL(memoryRS mem, immL16 src) %{
|
|
4699 |
match(Set mem (StoreL mem src)); |
|
4700 |
ins_cost(MEMORY_REF_COST); |
|
4701 |
size(6); |
|
4702 |
format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
|
|
4703 |
opcode(MVGHI_ZOPC); |
|
4704 |
ins_encode(z_silform(mem, src)); |
|
4705 |
ins_pipe(pipe_class_dummy); |
|
4706 |
%} |
|
4707 |
||
4708 |
// Move Immediate to 8-byte memory. |
|
4709 |
instruct memInitP(memoryRS mem, immP16 src) %{
|
|
4710 |
match(Set mem (StoreP mem src)); |
|
4711 |
ins_cost(MEMORY_REF_COST); |
|
4712 |
size(6); |
|
4713 |
format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
|
|
4714 |
opcode(MVGHI_ZOPC); |
|
4715 |
ins_encode(z_silform(mem, src)); |
|
4716 |
ins_pipe(pipe_class_dummy); |
|
4717 |
%} |
|
4718 |
||
4719 |
||
4720 |
//----------Instructions for compressed pointers (cOop and NKlass)------------- |
|
4721 |
||
4722 |
// See cOop encoding classes for elaborate comment. |
|
4723 |
||
4724 |
// Moved here because it is needed in expand rules for encode. |
|
4725 |
// Long negation. |
|
4726 |
instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{
|
|
4727 |
match(Set dst (SubL zero src)); |
|
4728 |
effect(KILL cr); |
|
4729 |
size(4); |
|
4730 |
format %{ "NEG $dst, $src\t # long" %}
|
|
4731 |
ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %}
|
|
4732 |
ins_pipe(pipe_class_dummy); |
|
4733 |
%} |
|
4734 |
||
4735 |
// Load Compressed Pointer |
|
4736 |
||
4737 |
// Load narrow oop |
|
4738 |
instruct loadN(iRegN dst, memory mem) %{
|
|
4739 |
match(Set dst (LoadN mem)); |
|
4740 |
ins_cost(MEMORY_REF_COST); |
|
4741 |
size(Z_DISP3_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4742 |
format %{ "LoadN $dst,$mem\t # (cOop)" %}
|
| 42065 | 4743 |
opcode(LLGF_ZOPC, LLGF_ZOPC); |
4744 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4745 |
ins_pipe(pipe_class_dummy); |
|
4746 |
%} |
|
4747 |
||
4748 |
// Load narrow Klass Pointer |
|
4749 |
instruct loadNKlass(iRegN dst, memory mem) %{
|
|
4750 |
match(Set dst (LoadNKlass mem)); |
|
4751 |
ins_cost(MEMORY_REF_COST); |
|
4752 |
size(Z_DISP3_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4753 |
format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %}
|
| 42065 | 4754 |
opcode(LLGF_ZOPC, LLGF_ZOPC); |
4755 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4756 |
ins_pipe(pipe_class_dummy); |
|
4757 |
%} |
|
4758 |
||
4759 |
// Load constant Compressed Pointer |
|
4760 |
||
4761 |
instruct loadConN(iRegN dst, immN src) %{
|
|
4762 |
match(Set dst src); |
|
4763 |
ins_cost(DEFAULT_COST); |
|
4764 |
size(6); |
|
4765 |
format %{ "loadConN $dst,$src\t # (cOop)" %}
|
|
4766 |
ins_encode %{
|
|
4767 |
AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant); |
|
4768 |
__ relocate(cOop.rspec(), 1); |
|
4769 |
__ load_narrow_oop($dst$$Register, (narrowOop)cOop.value()); |
|
4770 |
%} |
|
4771 |
ins_pipe(pipe_class_dummy); |
|
4772 |
%} |
|
4773 |
||
4774 |
instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{
|
|
4775 |
match(Set dst src); |
|
4776 |
effect(KILL cr); |
|
4777 |
ins_cost(DEFAULT_COST_LOW); |
|
4778 |
size(4); |
|
4779 |
format %{ "loadConN $dst,$src\t # (cOop) XGR because ZERO is loaded" %}
|
|
4780 |
opcode(XGR_ZOPC); |
|
4781 |
ins_encode(z_rreform(dst, dst)); |
|
4782 |
ins_pipe(pipe_class_dummy); |
|
4783 |
%} |
|
4784 |
||
4785 |
instruct loadConNKlass(iRegN dst, immNKlass src) %{
|
|
4786 |
match(Set dst src); |
|
4787 |
ins_cost(DEFAULT_COST); |
|
4788 |
size(6); |
|
4789 |
format %{ "loadConNKlass $dst,$src\t # (cKlass)" %}
|
|
4790 |
ins_encode %{
|
|
4791 |
AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant); |
|
4792 |
__ relocate(NKlass.rspec(), 1); |
|
4793 |
__ load_narrow_klass($dst$$Register, (Klass*)NKlass.value()); |
|
4794 |
%} |
|
4795 |
ins_pipe(pipe_class_dummy); |
|
4796 |
%} |
|
4797 |
||
4798 |
// Load and Decode Compressed Pointer |
|
4799 |
// optimized variants for Unscaled cOops |
|
4800 |
||
4801 |
instruct decodeLoadN(iRegP dst, memory mem) %{
|
|
4802 |
match(Set dst (DecodeN (LoadN mem))); |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4803 |
predicate(false && (CompressedOops::base()==NULL)&&(CompressedOops::shift()==0)); |
| 42065 | 4804 |
ins_cost(MEMORY_REF_COST); |
4805 |
size(Z_DISP3_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4806 |
format %{ "DecodeLoadN $dst,$mem\t # (cOop Load+Decode)" %}
|
| 42065 | 4807 |
opcode(LLGF_ZOPC, LLGF_ZOPC); |
4808 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4809 |
ins_pipe(pipe_class_dummy); |
|
4810 |
%} |
|
4811 |
||
4812 |
instruct decodeLoadNKlass(iRegP dst, memory mem) %{
|
|
4813 |
match(Set dst (DecodeNKlass (LoadNKlass mem))); |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4814 |
predicate(false && (CompressedKlassPointers::base()==NULL)&&(CompressedKlassPointers::shift()==0)); |
| 42065 | 4815 |
ins_cost(MEMORY_REF_COST); |
4816 |
size(Z_DISP3_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4817 |
format %{ "DecodeLoadNKlass $dst,$mem\t # (load/decode NKlass)" %}
|
| 42065 | 4818 |
opcode(LLGF_ZOPC, LLGF_ZOPC); |
4819 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
4820 |
ins_pipe(pipe_class_dummy); |
|
4821 |
%} |
|
4822 |
||
4823 |
instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{
|
|
4824 |
match(Set dst (DecodeNKlass src)); |
|
4825 |
ins_cost(3 * DEFAULT_COST); |
|
4826 |
size(12); |
|
4827 |
format %{ "DecodeLoadConNKlass $dst,$src\t # decode(cKlass)" %}
|
|
4828 |
ins_encode %{
|
|
4829 |
AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant); |
|
4830 |
__ relocate(NKlass.rspec(), 1); |
|
4831 |
__ load_const($dst$$Register, (Klass*)NKlass.value()); |
|
4832 |
%} |
|
4833 |
ins_pipe(pipe_class_dummy); |
|
4834 |
%} |
|
4835 |
||
4836 |
// Decode Compressed Pointer |
|
4837 |
||
4838 |
// General decoder |
|
4839 |
instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{
|
|
4840 |
match(Set dst (DecodeN src)); |
|
4841 |
effect(KILL cr); |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4842 |
predicate(CompressedOops::base() == NULL || !ExpandLoadingBaseDecode); |
| 42065 | 4843 |
ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); |
4844 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4845 |
format %{ "decodeN $dst,$src\t # (decode cOop)" %}
|
| 42065 | 4846 |
ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %}
|
4847 |
ins_pipe(pipe_class_dummy); |
|
4848 |
%} |
|
4849 |
||
4850 |
// General Klass decoder |
|
4851 |
instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{
|
|
4852 |
match(Set dst (DecodeNKlass src)); |
|
4853 |
effect(KILL cr); |
|
4854 |
ins_cost(3 * DEFAULT_COST); |
|
4855 |
format %{ "decode_klass $dst,$src" %}
|
|
4856 |
ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %}
|
|
4857 |
ins_pipe(pipe_class_dummy); |
|
4858 |
%} |
|
4859 |
||
4860 |
// General decoder |
|
4861 |
instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{
|
|
4862 |
match(Set dst (DecodeN src)); |
|
4863 |
effect(KILL cr); |
|
4864 |
predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || |
|
4865 |
n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4866 |
(CompressedOops::base()== NULL || !ExpandLoadingBaseDecode_NN)); |
| 42065 | 4867 |
ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); |
4868 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4869 |
format %{ "decodeN $dst,$src\t # (decode cOop NN)" %}
|
| 42065 | 4870 |
ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
|
4871 |
ins_pipe(pipe_class_dummy); |
|
4872 |
%} |
|
4873 |
||
4874 |
instruct loadBase(iRegL dst, immL baseImm) %{
|
|
4875 |
effect(DEF dst, USE baseImm); |
|
4876 |
predicate(false); |
|
4877 |
format %{ "llihl $dst=$baseImm \t// load heap base" %}
|
|
4878 |
ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %}
|
|
4879 |
ins_pipe(pipe_class_dummy); |
|
4880 |
%} |
|
4881 |
||
4882 |
// Decoder for heapbased mode peeling off loading the base. |
|
4883 |
instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
|
|
4884 |
match(Set dst (DecodeN src base)); |
|
4885 |
// Note: Effect TEMP dst was used with the intention to get |
|
4886 |
// different regs for dst and base, but this has caused ADLC to |
|
4887 |
// generate wrong code. Oop_decoder generates additional lgr when |
|
4888 |
// dst==base. |
|
4889 |
effect(KILL cr); |
|
4890 |
predicate(false); |
|
4891 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4892 |
format %{ "decodeN $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
|
| 42065 | 4893 |
ins_encode %{
|
4894 |
__ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register, |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4895 |
(jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base())); |
| 42065 | 4896 |
%} |
4897 |
ins_pipe(pipe_class_dummy); |
|
4898 |
%} |
|
4899 |
||
4900 |
// Decoder for heapbased mode peeling off loading the base. |
|
4901 |
instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
|
|
4902 |
match(Set dst (DecodeN src base)); |
|
4903 |
effect(KILL cr); |
|
4904 |
predicate(false); |
|
4905 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4906 |
format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
|
| 42065 | 4907 |
ins_encode %{
|
4908 |
__ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register, |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4909 |
(jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base())); |
| 42065 | 4910 |
%} |
4911 |
ins_pipe(pipe_class_dummy); |
|
4912 |
%} |
|
4913 |
||
4914 |
// Decoder for heapbased mode peeling off loading the base. |
|
4915 |
instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
|
|
4916 |
match(Set dst (DecodeN src)); |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4917 |
predicate(CompressedOops::base() != NULL && ExpandLoadingBaseDecode); |
| 42065 | 4918 |
ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); |
4919 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
4920 |
expand %{
|
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4921 |
immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
|
| 42065 | 4922 |
iRegL base; |
4923 |
loadBase(base, baseImm); |
|
4924 |
decodeN_base(dst, src, base, cr); |
|
4925 |
%} |
|
4926 |
%} |
|
4927 |
||
4928 |
// Decoder for heapbased mode peeling off loading the base. |
|
4929 |
instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
|
|
4930 |
match(Set dst (DecodeN src)); |
|
4931 |
predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || |
|
4932 |
n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4933 |
CompressedOops::base() != NULL && ExpandLoadingBaseDecode_NN); |
| 42065 | 4934 |
ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); |
4935 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
4936 |
expand %{
|
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4937 |
immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
|
| 42065 | 4938 |
iRegL base; |
4939 |
loadBase(base, baseImm); |
|
4940 |
decodeN_NN_base(dst, src, base, cr); |
|
4941 |
%} |
|
4942 |
%} |
|
4943 |
||
4944 |
// Encode Compressed Pointer |
|
4945 |
||
4946 |
// General encoder |
|
4947 |
instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{
|
|
4948 |
match(Set dst (EncodeP src)); |
|
4949 |
effect(KILL cr); |
|
4950 |
predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4951 |
(CompressedOops::base() == 0 || |
|
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4952 |
CompressedOops::base_disjoint() || |
| 42065 | 4953 |
!ExpandLoadingBaseEncode)); |
4954 |
ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); |
|
4955 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4956 |
format %{ "encodeP $dst,$src\t # (encode cOop)" %}
|
| 42065 | 4957 |
ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
|
4958 |
ins_pipe(pipe_class_dummy); |
|
4959 |
%} |
|
4960 |
||
4961 |
// General class encoder |
|
4962 |
instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{
|
|
4963 |
match(Set dst (EncodePKlass src)); |
|
4964 |
effect(KILL cr); |
|
4965 |
format %{ "encode_klass $dst,$src" %}
|
|
4966 |
ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %}
|
|
4967 |
ins_pipe(pipe_class_dummy); |
|
4968 |
%} |
|
4969 |
||
4970 |
instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{
|
|
4971 |
match(Set dst (EncodeP src)); |
|
4972 |
effect(KILL cr); |
|
4973 |
predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4974 |
(CompressedOops::base() == 0 || |
|
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4975 |
CompressedOops::base_disjoint() || |
| 42065 | 4976 |
!ExpandLoadingBaseEncode_NN)); |
4977 |
ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); |
|
4978 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4979 |
format %{ "encodeP $dst,$src\t # (encode cOop)" %}
|
| 42065 | 4980 |
ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
|
4981 |
ins_pipe(pipe_class_dummy); |
|
4982 |
%} |
|
4983 |
||
4984 |
// Encoder for heapbased mode peeling off loading the base. |
|
4985 |
instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{
|
|
4986 |
match(Set dst (EncodeP src (Binary base dst))); |
|
4987 |
effect(TEMP_DEF dst); |
|
4988 |
predicate(false); |
|
4989 |
ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); |
|
4990 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
4991 |
format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %}
|
| 42065 | 4992 |
ins_encode %{
|
4993 |
jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
4994 |
(((uint64_t)(intptr_t)CompressedOops::base()) >> CompressedOops::shift()); |
| 42065 | 4995 |
__ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset); |
4996 |
%} |
|
4997 |
ins_pipe(pipe_class_dummy); |
|
4998 |
%} |
|
4999 |
||
5000 |
// Encoder for heapbased mode peeling off loading the base. |
|
5001 |
instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{
|
|
5002 |
match(Set dst (EncodeP src base)); |
|
5003 |
effect(USE pow2_offset); |
|
5004 |
predicate(false); |
|
5005 |
ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); |
|
5006 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
5007 |
format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %}
|
| 42065 | 5008 |
ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
|
5009 |
ins_pipe(pipe_class_dummy); |
|
5010 |
%} |
|
5011 |
||
5012 |
// Encoder for heapbased mode peeling off loading the base. |
|
5013 |
instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{
|
|
5014 |
match(Set dst (EncodeP src)); |
|
5015 |
effect(KILL cr); |
|
5016 |
predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
5017 |
(CompressedOops::base_overlaps() && ExpandLoadingBaseEncode)); |
| 42065 | 5018 |
ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); |
5019 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5020 |
expand %{
|
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
5021 |
immL baseImm %{ ((jlong)(intptr_t)CompressedOops::base()) >> CompressedOops::shift() %}
|
| 42065 | 5022 |
immL_0 zero %{ (0) %}
|
5023 |
flagsReg ccr; |
|
5024 |
iRegL base; |
|
5025 |
iRegL negBase; |
|
5026 |
loadBase(base, baseImm); |
|
5027 |
negL_reg_reg(negBase, zero, base, ccr); |
|
5028 |
encodeP_base(dst, src, negBase); |
|
5029 |
%} |
|
5030 |
%} |
|
5031 |
||
5032 |
// Encoder for heapbased mode peeling off loading the base. |
|
5033 |
instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{
|
|
5034 |
match(Set dst (EncodeP src)); |
|
5035 |
effect(KILL cr); |
|
5036 |
predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
5037 |
(CompressedOops::base_overlaps() && ExpandLoadingBaseEncode_NN)); |
| 42065 | 5038 |
ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); |
5039 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5040 |
expand %{
|
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
5041 |
immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
|
|
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
5042 |
immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)CompressedOops::base())) %}
|
| 42065 | 5043 |
immL_0 zero %{ 0 %}
|
5044 |
flagsReg ccr; |
|
5045 |
iRegL base; |
|
5046 |
iRegL negBase; |
|
5047 |
loadBase(base, baseImm); |
|
5048 |
negL_reg_reg(negBase, zero, base, ccr); |
|
5049 |
encodeP_NN_base(dst, src, negBase, pow2_offset); |
|
5050 |
%} |
|
5051 |
%} |
|
5052 |
||
5053 |
// Store Compressed Pointer |
|
5054 |
||
5055 |
// Store Compressed Pointer |
|
5056 |
instruct storeN(memory mem, iRegN_P2N src) %{
|
|
5057 |
match(Set mem (StoreN mem src)); |
|
5058 |
ins_cost(MEMORY_REF_COST); |
|
5059 |
size(Z_DISP_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
5060 |
format %{ "ST $src,$mem\t # (cOop)" %}
|
| 42065 | 5061 |
opcode(STY_ZOPC, ST_ZOPC); |
5062 |
ins_encode(z_form_rt_mem_opt(src, mem)); |
|
5063 |
ins_pipe(pipe_class_dummy); |
|
5064 |
%} |
|
5065 |
||
5066 |
// Store Compressed Klass pointer |
|
5067 |
instruct storeNKlass(memory mem, iRegN src) %{
|
|
5068 |
match(Set mem (StoreNKlass mem src)); |
|
5069 |
ins_cost(MEMORY_REF_COST); |
|
5070 |
size(Z_DISP_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
5071 |
format %{ "ST $src,$mem\t # (cKlass)" %}
|
| 42065 | 5072 |
opcode(STY_ZOPC, ST_ZOPC); |
5073 |
ins_encode(z_form_rt_mem_opt(src, mem)); |
|
5074 |
ins_pipe(pipe_class_dummy); |
|
5075 |
%} |
|
5076 |
||
5077 |
// Compare Compressed Pointers |
|
5078 |
||
5079 |
instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
|
|
5080 |
match(Set cr (CmpN src1 src2)); |
|
5081 |
ins_cost(DEFAULT_COST); |
|
5082 |
size(2); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
5083 |
format %{ "CLR $src1,$src2\t # (cOop)" %}
|
| 42065 | 5084 |
opcode(CLR_ZOPC); |
5085 |
ins_encode(z_rrform(src1, src2)); |
|
5086 |
ins_pipe(pipe_class_dummy); |
|
5087 |
%} |
|
5088 |
||
5089 |
instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
|
|
5090 |
match(Set cr (CmpN src1 src2)); |
|
5091 |
ins_cost(DEFAULT_COST); |
|
5092 |
size(6); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
5093 |
format %{ "CLFI $src1,$src2\t # (cOop) compare immediate narrow" %}
|
| 42065 | 5094 |
ins_encode %{
|
5095 |
AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant); |
|
5096 |
__ relocate(cOop.rspec(), 1); |
|
5097 |
__ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value()); |
|
5098 |
%} |
|
5099 |
ins_pipe(pipe_class_dummy); |
|
5100 |
%} |
|
5101 |
||
5102 |
instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
|
|
5103 |
match(Set cr (CmpN src1 src2)); |
|
5104 |
ins_cost(DEFAULT_COST); |
|
5105 |
size(6); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
5106 |
format %{ "CLFI $src1,$src2\t # (NKlass) compare immediate narrow" %}
|
| 42065 | 5107 |
ins_encode %{
|
5108 |
AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant); |
|
5109 |
__ relocate(NKlass.rspec(), 1); |
|
5110 |
__ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value()); |
|
5111 |
%} |
|
5112 |
ins_pipe(pipe_class_dummy); |
|
5113 |
%} |
|
5114 |
||
5115 |
instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
|
|
5116 |
match(Set cr (CmpN src1 src2)); |
|
5117 |
ins_cost(DEFAULT_COST); |
|
5118 |
size(2); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
5119 |
format %{ "LTR $src1,$src2\t # (cOop) LTR because comparing against zero" %}
|
| 42065 | 5120 |
opcode(LTR_ZOPC); |
5121 |
ins_encode(z_rrform(src1, src1)); |
|
5122 |
ins_pipe(pipe_class_dummy); |
|
5123 |
%} |
|
5124 |
||
5125 |
||
5126 |
//----------MemBar Instructions----------------------------------------------- |
|
5127 |
||
5128 |
// Memory barrier flavors |
|
5129 |
||
5130 |
instruct membar_acquire() %{
|
|
5131 |
match(MemBarAcquire); |
|
5132 |
match(LoadFence); |
|
5133 |
ins_cost(4*MEMORY_REF_COST); |
|
5134 |
size(0); |
|
5135 |
format %{ "MEMBAR-acquire" %}
|
|
5136 |
ins_encode %{ __ z_acquire(); %}
|
|
5137 |
ins_pipe(pipe_class_dummy); |
|
5138 |
%} |
|
5139 |
||
5140 |
instruct membar_acquire_lock() %{
|
|
5141 |
match(MemBarAcquireLock); |
|
5142 |
ins_cost(0); |
|
5143 |
size(0); |
|
5144 |
format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
|
|
5145 |
ins_encode(/*empty*/); |
|
5146 |
ins_pipe(pipe_class_dummy); |
|
5147 |
%} |
|
5148 |
||
5149 |
instruct membar_release() %{
|
|
5150 |
match(MemBarRelease); |
|
5151 |
match(StoreFence); |
|
5152 |
ins_cost(4 * MEMORY_REF_COST); |
|
5153 |
size(0); |
|
5154 |
format %{ "MEMBAR-release" %}
|
|
5155 |
ins_encode %{ __ z_release(); %}
|
|
5156 |
ins_pipe(pipe_class_dummy); |
|
5157 |
%} |
|
5158 |
||
5159 |
instruct membar_release_lock() %{
|
|
5160 |
match(MemBarReleaseLock); |
|
5161 |
ins_cost(0); |
|
5162 |
size(0); |
|
5163 |
format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
|
|
5164 |
ins_encode(/*empty*/); |
|
5165 |
ins_pipe(pipe_class_dummy); |
|
5166 |
%} |
|
5167 |
||
5168 |
instruct membar_volatile() %{
|
|
5169 |
match(MemBarVolatile); |
|
5170 |
ins_cost(4 * MEMORY_REF_COST); |
|
5171 |
size(2); |
|
5172 |
format %{ "MEMBAR-volatile" %}
|
|
5173 |
ins_encode %{ __ z_fence(); %}
|
|
5174 |
ins_pipe(pipe_class_dummy); |
|
5175 |
%} |
|
5176 |
||
5177 |
instruct unnecessary_membar_volatile() %{
|
|
5178 |
match(MemBarVolatile); |
|
5179 |
predicate(Matcher::post_store_load_barrier(n)); |
|
5180 |
ins_cost(0); |
|
5181 |
size(0); |
|
5182 |
format %{ "# MEMBAR-volatile (empty)" %}
|
|
5183 |
ins_encode(/*empty*/); |
|
5184 |
ins_pipe(pipe_class_dummy); |
|
5185 |
%} |
|
5186 |
||
5187 |
instruct membar_CPUOrder() %{
|
|
5188 |
match(MemBarCPUOrder); |
|
5189 |
ins_cost(0); |
|
5190 |
// TODO: s390 port size(FIXED_SIZE); |
|
5191 |
format %{ "MEMBAR-CPUOrder (empty)" %}
|
|
5192 |
ins_encode(/*empty*/); |
|
5193 |
ins_pipe(pipe_class_dummy); |
|
5194 |
%} |
|
5195 |
||
5196 |
instruct membar_storestore() %{
|
|
5197 |
match(MemBarStoreStore); |
|
5198 |
ins_cost(0); |
|
5199 |
size(0); |
|
5200 |
format %{ "MEMBAR-storestore (empty)" %}
|
|
5201 |
ins_encode(); |
|
5202 |
ins_pipe(pipe_class_dummy); |
|
5203 |
%} |
|
5204 |
||
5205 |
||
5206 |
//----------Register Move Instructions----------------------------------------- |
|
5207 |
instruct roundDouble_nop(regD dst) %{
|
|
5208 |
match(Set dst (RoundDouble dst)); |
|
5209 |
ins_cost(0); |
|
5210 |
// TODO: s390 port size(FIXED_SIZE); |
|
5211 |
// z/Architecture results are already "rounded" (i.e., normal-format IEEE). |
|
5212 |
ins_encode(); |
|
5213 |
ins_pipe(pipe_class_dummy); |
|
5214 |
%} |
|
5215 |
||
5216 |
instruct roundFloat_nop(regF dst) %{
|
|
5217 |
match(Set dst (RoundFloat dst)); |
|
5218 |
ins_cost(0); |
|
5219 |
// TODO: s390 port size(FIXED_SIZE); |
|
5220 |
// z/Architecture results are already "rounded" (i.e., normal-format IEEE). |
|
5221 |
ins_encode(); |
|
5222 |
ins_pipe(pipe_class_dummy); |
|
5223 |
%} |
|
5224 |
||
5225 |
// Cast Long to Pointer for unsafe natives. |
|
5226 |
instruct castX2P(iRegP dst, iRegL src) %{
|
|
5227 |
match(Set dst (CastX2P src)); |
|
5228 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5229 |
format %{ "LGR $dst,$src\t # CastX2P" %}
|
|
5230 |
ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
|
|
5231 |
ins_pipe(pipe_class_dummy); |
|
5232 |
%} |
|
5233 |
||
5234 |
// Cast Pointer to Long for unsafe natives. |
|
5235 |
instruct castP2X(iRegL dst, iRegP_N2P src) %{
|
|
5236 |
match(Set dst (CastP2X src)); |
|
5237 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5238 |
format %{ "LGR $dst,$src\t # CastP2X" %}
|
|
5239 |
ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
|
|
5240 |
ins_pipe(pipe_class_dummy); |
|
5241 |
%} |
|
5242 |
||
5243 |
instruct stfSSD(stackSlotD stkSlot, regD src) %{
|
|
5244 |
// %%%% TODO: Tell the coalescer that this kind of node is a copy! |
|
5245 |
match(Set stkSlot src); // chain rule |
|
5246 |
ins_cost(MEMORY_REF_COST); |
|
5247 |
// TODO: s390 port size(FIXED_SIZE); |
|
5248 |
format %{ " STD $src,$stkSlot\t # stk" %}
|
|
5249 |
opcode(STD_ZOPC); |
|
5250 |
ins_encode(z_form_rt_mem(src, stkSlot)); |
|
5251 |
ins_pipe(pipe_class_dummy); |
|
5252 |
%} |
|
5253 |
||
5254 |
instruct stfSSF(stackSlotF stkSlot, regF src) %{
|
|
5255 |
// %%%% TODO: Tell the coalescer that this kind of node is a copy! |
|
5256 |
match(Set stkSlot src); // chain rule |
|
5257 |
ins_cost(MEMORY_REF_COST); |
|
5258 |
// TODO: s390 port size(FIXED_SIZE); |
|
5259 |
format %{ "STE $src,$stkSlot\t # stk" %}
|
|
5260 |
opcode(STE_ZOPC); |
|
5261 |
ins_encode(z_form_rt_mem(src, stkSlot)); |
|
5262 |
ins_pipe(pipe_class_dummy); |
|
5263 |
%} |
|
5264 |
||
5265 |
//----------Conditional Move--------------------------------------------------- |
|
5266 |
||
5267 |
instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{
|
|
5268 |
match(Set dst (CMoveN (Binary cmp cr) (Binary dst src))); |
|
5269 |
ins_cost(DEFAULT_COST + BRANCH_COST); |
|
5270 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5271 |
format %{ "CMoveN,$cmp $dst,$src" %}
|
|
5272 |
ins_encode(z_enc_cmov_reg(cmp,dst,src)); |
|
5273 |
ins_pipe(pipe_class_dummy); |
|
5274 |
%} |
|
5275 |
||
5276 |
instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{
|
|
5277 |
match(Set dst (CMoveN (Binary cmp cr) (Binary dst src))); |
|
5278 |
ins_cost(DEFAULT_COST + BRANCH_COST); |
|
5279 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5280 |
format %{ "CMoveN,$cmp $dst,$src" %}
|
|
5281 |
ins_encode(z_enc_cmov_imm(cmp,dst,src)); |
|
5282 |
ins_pipe(pipe_class_dummy); |
|
5283 |
%} |
|
5284 |
||
5285 |
instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{
|
|
5286 |
match(Set dst (CMoveI (Binary cmp cr) (Binary dst src))); |
|
5287 |
ins_cost(DEFAULT_COST + BRANCH_COST); |
|
5288 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5289 |
format %{ "CMoveI,$cmp $dst,$src" %}
|
|
5290 |
ins_encode(z_enc_cmov_reg(cmp,dst,src)); |
|
5291 |
ins_pipe(pipe_class_dummy); |
|
5292 |
%} |
|
5293 |
||
5294 |
instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{
|
|
5295 |
match(Set dst (CMoveI (Binary cmp cr) (Binary dst src))); |
|
5296 |
ins_cost(DEFAULT_COST + BRANCH_COST); |
|
5297 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5298 |
format %{ "CMoveI,$cmp $dst,$src" %}
|
|
5299 |
ins_encode(z_enc_cmov_imm(cmp,dst,src)); |
|
5300 |
ins_pipe(pipe_class_dummy); |
|
5301 |
%} |
|
5302 |
||
5303 |
instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{
|
|
5304 |
match(Set dst (CMoveP (Binary cmp cr) (Binary dst src))); |
|
5305 |
ins_cost(DEFAULT_COST + BRANCH_COST); |
|
5306 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5307 |
format %{ "CMoveP,$cmp $dst,$src" %}
|
|
5308 |
ins_encode(z_enc_cmov_reg(cmp,dst,src)); |
|
5309 |
ins_pipe(pipe_class_dummy); |
|
5310 |
%} |
|
5311 |
||
5312 |
instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{
|
|
5313 |
match(Set dst (CMoveP (Binary cmp cr) (Binary dst src))); |
|
5314 |
ins_cost(DEFAULT_COST + BRANCH_COST); |
|
5315 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5316 |
format %{ "CMoveP,$cmp $dst,$src" %}
|
|
5317 |
ins_encode(z_enc_cmov_imm(cmp,dst,src)); |
|
5318 |
ins_pipe(pipe_class_dummy); |
|
5319 |
%} |
|
5320 |
||
5321 |
instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{
|
|
5322 |
match(Set dst (CMoveF (Binary cmp cr) (Binary dst src))); |
|
5323 |
ins_cost(DEFAULT_COST + BRANCH_COST); |
|
5324 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5325 |
format %{ "CMoveF,$cmp $dst,$src" %}
|
|
5326 |
ins_encode %{
|
|
5327 |
// Don't emit code if operands are identical (same register). |
|
5328 |
if ($dst$$FloatRegister != $src$$FloatRegister) {
|
|
5329 |
Label done; |
|
5330 |
__ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done); |
|
5331 |
__ z_ler($dst$$FloatRegister, $src$$FloatRegister); |
|
5332 |
__ bind(done); |
|
5333 |
} |
|
5334 |
%} |
|
5335 |
ins_pipe(pipe_class_dummy); |
|
5336 |
%} |
|
5337 |
||
5338 |
instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{
|
|
5339 |
match(Set dst (CMoveD (Binary cmp cr) (Binary dst src))); |
|
5340 |
ins_cost(DEFAULT_COST + BRANCH_COST); |
|
5341 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5342 |
format %{ "CMoveD,$cmp $dst,$src" %}
|
|
5343 |
ins_encode %{
|
|
5344 |
// Don't emit code if operands are identical (same register). |
|
5345 |
if ($dst$$FloatRegister != $src$$FloatRegister) {
|
|
5346 |
Label done; |
|
5347 |
__ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done); |
|
5348 |
__ z_ldr($dst$$FloatRegister, $src$$FloatRegister); |
|
5349 |
__ bind(done); |
|
5350 |
} |
|
5351 |
%} |
|
5352 |
ins_pipe(pipe_class_dummy); |
|
5353 |
%} |
|
5354 |
||
5355 |
instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{
|
|
5356 |
match(Set dst (CMoveL (Binary cmp cr) (Binary dst src))); |
|
5357 |
ins_cost(DEFAULT_COST + BRANCH_COST); |
|
5358 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5359 |
format %{ "CMoveL,$cmp $dst,$src" %}
|
|
5360 |
ins_encode(z_enc_cmov_reg(cmp,dst,src)); |
|
5361 |
ins_pipe(pipe_class_dummy); |
|
5362 |
%} |
|
5363 |
||
5364 |
instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{
|
|
5365 |
match(Set dst (CMoveL (Binary cmp cr) (Binary dst src))); |
|
5366 |
ins_cost(DEFAULT_COST + BRANCH_COST); |
|
5367 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5368 |
format %{ "CMoveL,$cmp $dst,$src" %}
|
|
5369 |
ins_encode(z_enc_cmov_imm(cmp,dst,src)); |
|
5370 |
ins_pipe(pipe_class_dummy); |
|
5371 |
%} |
|
5372 |
||
5373 |
//----------OS and Locking Instructions---------------------------------------- |
|
5374 |
||
5375 |
// This name is KNOWN by the ADLC and cannot be changed. |
|
5376 |
// The ADLC forces a 'TypeRawPtr::BOTTOM' output type |
|
5377 |
// for this guy. |
|
5378 |
instruct tlsLoadP(threadRegP dst) %{
|
|
5379 |
match(Set dst (ThreadLocal)); |
|
5380 |
ins_cost(0); |
|
5381 |
size(0); |
|
5382 |
ins_should_rematerialize(true); |
|
5383 |
format %{ "# $dst=ThreadLocal" %}
|
|
5384 |
ins_encode(/* empty */); |
|
5385 |
ins_pipe(pipe_class_dummy); |
|
5386 |
%} |
|
5387 |
||
5388 |
instruct checkCastPP(iRegP dst) %{
|
|
5389 |
match(Set dst (CheckCastPP dst)); |
|
5390 |
size(0); |
|
5391 |
format %{ "# checkcastPP of $dst" %}
|
|
5392 |
ins_encode(/*empty*/); |
|
5393 |
ins_pipe(pipe_class_dummy); |
|
5394 |
%} |
|
5395 |
||
5396 |
instruct castPP(iRegP dst) %{
|
|
5397 |
match(Set dst (CastPP dst)); |
|
5398 |
size(0); |
|
5399 |
format %{ "# castPP of $dst" %}
|
|
5400 |
ins_encode(/*empty*/); |
|
5401 |
ins_pipe(pipe_class_dummy); |
|
5402 |
%} |
|
5403 |
||
5404 |
instruct castII(iRegI dst) %{
|
|
5405 |
match(Set dst (CastII dst)); |
|
5406 |
size(0); |
|
5407 |
format %{ "# castII of $dst" %}
|
|
5408 |
ins_encode(/*empty*/); |
|
5409 |
ins_pipe(pipe_class_dummy); |
|
5410 |
%} |
|
5411 |
||
|
58019
86b95fc6ca32
8229496: SIGFPE (division by zero) in C2 OSR compiled method
thartmann
parents:
55343
diff
changeset
|
5412 |
instruct castLL(iRegL dst) %{
|
|
86b95fc6ca32
8229496: SIGFPE (division by zero) in C2 OSR compiled method
thartmann
parents:
55343
diff
changeset
|
5413 |
match(Set dst (CastLL dst)); |
|
86b95fc6ca32
8229496: SIGFPE (division by zero) in C2 OSR compiled method
thartmann
parents:
55343
diff
changeset
|
5414 |
size(0); |
|
86b95fc6ca32
8229496: SIGFPE (division by zero) in C2 OSR compiled method
thartmann
parents:
55343
diff
changeset
|
5415 |
format %{ "# castLL of $dst" %}
|
|
86b95fc6ca32
8229496: SIGFPE (division by zero) in C2 OSR compiled method
thartmann
parents:
55343
diff
changeset
|
5416 |
ins_encode(/*empty*/); |
|
86b95fc6ca32
8229496: SIGFPE (division by zero) in C2 OSR compiled method
thartmann
parents:
55343
diff
changeset
|
5417 |
ins_pipe(pipe_class_dummy); |
|
86b95fc6ca32
8229496: SIGFPE (division by zero) in C2 OSR compiled method
thartmann
parents:
55343
diff
changeset
|
5418 |
%} |
|
86b95fc6ca32
8229496: SIGFPE (division by zero) in C2 OSR compiled method
thartmann
parents:
55343
diff
changeset
|
5419 |
|
| 42065 | 5420 |
|
5421 |
//----------Conditional_store-------------------------------------------------- |
|
5422 |
// Conditional-store of the updated heap-top. |
|
5423 |
// Used during allocation of the shared heap. |
|
5424 |
// Sets flags (EQ) on success. |
|
5425 |
||
5426 |
// Implement LoadPLocked. Must be ordered against changes of the memory location |
|
5427 |
// by storePConditional. |
|
5428 |
// Don't know whether this is ever used. |
|
5429 |
instruct loadPLocked(iRegP dst, memory mem) %{
|
|
5430 |
match(Set dst (LoadPLocked mem)); |
|
5431 |
ins_cost(MEMORY_REF_COST); |
|
5432 |
size(Z_DISP3_SIZE); |
|
5433 |
format %{ "LG $dst,$mem\t # LoadPLocked" %}
|
|
5434 |
opcode(LG_ZOPC, LG_ZOPC); |
|
5435 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
5436 |
ins_pipe(pipe_class_dummy); |
|
5437 |
%} |
|
5438 |
||
5439 |
// As compareAndSwapP, but return flag register instead of boolean value in |
|
5440 |
// int register. |
|
5441 |
// This instruction is matched if UseTLAB is off. Needed to pass |
|
5442 |
// option tests. Mem_ptr must be a memory operand, else this node |
|
5443 |
// does not get Flag_needs_anti_dependence_check set by adlc. If this |
|
5444 |
// is not set this node can be rematerialized which leads to errors. |
|
5445 |
instruct storePConditional(indirect mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{
|
|
5446 |
match(Set cr (StorePConditional mem_ptr (Binary oldval newval))); |
|
5447 |
effect(KILL oldval); |
|
5448 |
// TODO: s390 port size(FIXED_SIZE); |
|
5449 |
format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
|
|
5450 |
ins_encode(z_enc_casL(oldval, newval, mem_ptr)); |
|
5451 |
ins_pipe(pipe_class_dummy); |
|
5452 |
%} |
|
5453 |
||
5454 |
// As compareAndSwapL, but return flag register instead of boolean value in |
|
5455 |
// int register. |
|
5456 |
// Used by sun/misc/AtomicLongCSImpl.java. Mem_ptr must be a memory |
|
5457 |
// operand, else this node does not get |
|
5458 |
// Flag_needs_anti_dependence_check set by adlc. If this is not set |
|
5459 |
// this node can be rematerialized which leads to errors. |
|
5460 |
instruct storeLConditional(indirect mem_ptr, rarg5RegL oldval, iRegL newval, flagsReg cr) %{
|
|
5461 |
match(Set cr (StoreLConditional mem_ptr (Binary oldval newval))); |
|
5462 |
effect(KILL oldval); |
|
5463 |
// TODO: s390 port size(FIXED_SIZE); |
|
5464 |
format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
|
|
5465 |
ins_encode(z_enc_casL(oldval, newval, mem_ptr)); |
|
5466 |
ins_pipe(pipe_class_dummy); |
|
5467 |
%} |
|
5468 |
||
5469 |
// No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them.
|
|
5470 |
||
5471 |
instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{
|
|
5472 |
match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); |
|
5473 |
effect(USE mem_ptr, USE_KILL oldval, KILL cr); |
|
5474 |
size(16); |
|
5475 |
format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %}
|
|
5476 |
ins_encode(z_enc_casI(oldval, newval, mem_ptr), |
|
5477 |
z_enc_cctobool(res)); |
|
5478 |
ins_pipe(pipe_class_dummy); |
|
5479 |
%} |
|
5480 |
||
5481 |
instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{
|
|
5482 |
match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
|
5483 |
effect(USE mem_ptr, USE_KILL oldval, KILL cr); |
|
5484 |
size(18); |
|
5485 |
format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %}
|
|
5486 |
ins_encode(z_enc_casL(oldval, newval, mem_ptr), |
|
5487 |
z_enc_cctobool(res)); |
|
5488 |
ins_pipe(pipe_class_dummy); |
|
5489 |
%} |
|
5490 |
||
5491 |
instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{
|
|
5492 |
match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
|
5493 |
effect(USE mem_ptr, USE_KILL oldval, KILL cr); |
|
5494 |
size(18); |
|
5495 |
format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %}
|
|
5496 |
ins_encode(z_enc_casL(oldval, newval, mem_ptr), |
|
5497 |
z_enc_cctobool(res)); |
|
5498 |
ins_pipe(pipe_class_dummy); |
|
5499 |
%} |
|
5500 |
||
5501 |
instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{
|
|
5502 |
match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
5503 |
effect(USE mem_ptr, USE_KILL oldval, KILL cr); |
|
5504 |
size(16); |
|
5505 |
format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %}
|
|
5506 |
ins_encode(z_enc_casI(oldval, newval, mem_ptr), |
|
5507 |
z_enc_cctobool(res)); |
|
5508 |
ins_pipe(pipe_class_dummy); |
|
5509 |
%} |
|
5510 |
||
5511 |
//----------Atomic operations on memory (GetAndSet*, GetAndAdd*)--------------- |
|
5512 |
||
5513 |
// Exploit: direct memory arithmetic |
|
5514 |
// Prereqs: - instructions available |
|
5515 |
// - instructions guarantee atomicity |
|
5516 |
// - immediate operand to be added |
|
5517 |
// - immediate operand is small enough (8-bit signed). |
|
5518 |
// - result of instruction is not used |
|
5519 |
instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{
|
|
5520 |
match(Set dummy (GetAndAddI mem src)); |
|
5521 |
effect(KILL cr); |
|
5522 |
predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used()); |
|
5523 |
ins_cost(MEMORY_REF_COST); |
|
5524 |
size(6); |
|
5525 |
format %{ "ASI [$mem],$src\t # GetAndAddI (atomic)" %}
|
|
5526 |
opcode(ASI_ZOPC); |
|
5527 |
ins_encode(z_siyform(mem, src)); |
|
5528 |
ins_pipe(pipe_class_dummy); |
|
5529 |
%} |
|
5530 |
||
5531 |
// Fallback: direct memory arithmetic not available |
|
5532 |
// Disadvantages: - CS-Loop required, very expensive. |
|
5533 |
// - more code generated (26 to xx bytes vs. 6 bytes) |
|
5534 |
instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{
|
|
5535 |
match(Set dst (GetAndAddI mem src)); |
|
5536 |
effect(KILL cr, TEMP_DEF dst, TEMP tmp); |
|
5537 |
ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); |
|
5538 |
format %{ "BEGIN ATOMIC {\n\t"
|
|
5539 |
" LGF $dst,[$mem]\n\t" |
|
5540 |
" AHIK $tmp,$dst,$src\n\t" |
|
5541 |
" CSY $dst,$tmp,$mem\n\t" |
|
5542 |
" retry if failed\n\t" |
|
5543 |
"} END ATOMIC" |
|
5544 |
%} |
|
5545 |
ins_encode %{
|
|
5546 |
Register Rdst = $dst$$Register; |
|
5547 |
Register Rtmp = $tmp$$Register; |
|
5548 |
int Isrc = $src$$constant; |
|
5549 |
Label retry; |
|
5550 |
||
5551 |
// Iterate until update with incremented value succeeds. |
|
5552 |
__ z_lgf(Rdst, $mem$$Address); // current contents |
|
5553 |
__ bind(retry); |
|
5554 |
// Calculate incremented value. |
|
5555 |
if (VM_Version::has_DistinctOpnds()) {
|
|
5556 |
__ z_ahik(Rtmp, Rdst, Isrc); |
|
5557 |
} else {
|
|
5558 |
__ z_lr(Rtmp, Rdst); |
|
5559 |
__ z_ahi(Rtmp, Isrc); |
|
5560 |
} |
|
5561 |
// Swap into memory location. |
|
5562 |
__ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. |
|
5563 |
__ z_brne(retry); // Yikes, concurrent update, need to retry. |
|
5564 |
%} |
|
5565 |
ins_pipe(pipe_class_dummy); |
|
5566 |
%} |
|
5567 |
||
5568 |
instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{
|
|
5569 |
match(Set dst (GetAndAddI mem src)); |
|
5570 |
effect(KILL cr, TEMP_DEF dst, TEMP tmp); |
|
5571 |
ins_cost(MEMORY_REF_COST+200*DEFAULT_COST); |
|
5572 |
format %{ "BEGIN ATOMIC {\n\t"
|
|
5573 |
" LGF $dst,[$mem]\n\t" |
|
5574 |
" LGR $tmp,$dst\n\t" |
|
5575 |
" AFI $tmp,$src\n\t" |
|
5576 |
" CSY $dst,$tmp,$mem\n\t" |
|
5577 |
" retry if failed\n\t" |
|
5578 |
"} END ATOMIC" |
|
5579 |
%} |
|
5580 |
ins_encode %{
|
|
5581 |
Register Rdst = $dst$$Register; |
|
5582 |
Register Rtmp = $tmp$$Register; |
|
5583 |
int Isrc = $src$$constant; |
|
5584 |
Label retry; |
|
5585 |
||
5586 |
// Iterate until update with incremented value succeeds. |
|
5587 |
__ z_lgf(Rdst, $mem$$Address); // current contents |
|
5588 |
__ bind(retry); |
|
5589 |
// Calculate incremented value. |
|
5590 |
__ z_lr(Rtmp, Rdst); |
|
5591 |
__ z_afi(Rtmp, Isrc); |
|
5592 |
// Swap into memory location. |
|
5593 |
__ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. |
|
5594 |
__ z_brne(retry); // Yikes, concurrent update, need to retry. |
|
5595 |
%} |
|
5596 |
ins_pipe(pipe_class_dummy); |
|
5597 |
%} |
|
5598 |
||
5599 |
instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
|
|
5600 |
match(Set dst (GetAndAddI mem src)); |
|
5601 |
effect(KILL cr, TEMP_DEF dst, TEMP tmp); |
|
5602 |
ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); |
|
5603 |
format %{ "BEGIN ATOMIC {\n\t"
|
|
5604 |
" LGF $dst,[$mem]\n\t" |
|
5605 |
" ARK $tmp,$dst,$src\n\t" |
|
5606 |
" CSY $dst,$tmp,$mem\n\t" |
|
5607 |
" retry if failed\n\t" |
|
5608 |
"} END ATOMIC" |
|
5609 |
%} |
|
5610 |
ins_encode %{
|
|
5611 |
Register Rsrc = $src$$Register; |
|
5612 |
Register Rdst = $dst$$Register; |
|
5613 |
Register Rtmp = $tmp$$Register; |
|
5614 |
Label retry; |
|
5615 |
||
5616 |
// Iterate until update with incremented value succeeds. |
|
5617 |
__ z_lgf(Rdst, $mem$$Address); // current contents |
|
5618 |
__ bind(retry); |
|
5619 |
// Calculate incremented value. |
|
5620 |
if (VM_Version::has_DistinctOpnds()) {
|
|
5621 |
__ z_ark(Rtmp, Rdst, Rsrc); |
|
5622 |
} else {
|
|
5623 |
__ z_lr(Rtmp, Rdst); |
|
5624 |
__ z_ar(Rtmp, Rsrc); |
|
5625 |
} |
|
5626 |
__ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. |
|
5627 |
__ z_brne(retry); // Yikes, concurrent update, need to retry. |
|
5628 |
%} |
|
5629 |
ins_pipe(pipe_class_dummy); |
|
5630 |
%} |
|
5631 |
||
5632 |
||
5633 |
// Exploit: direct memory arithmetic |
|
5634 |
// Prereqs: - instructions available |
|
5635 |
// - instructions guarantee atomicity |
|
5636 |
// - immediate operand to be added |
|
5637 |
// - immediate operand is small enough (8-bit signed). |
|
5638 |
// - result of instruction is not used |
|
5639 |
instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{
|
|
5640 |
match(Set dummy (GetAndAddL mem src)); |
|
5641 |
effect(KILL cr); |
|
5642 |
predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used()); |
|
5643 |
ins_cost(MEMORY_REF_COST); |
|
5644 |
size(6); |
|
5645 |
format %{ "AGSI [$mem],$src\t # GetAndAddL (atomic)" %}
|
|
5646 |
opcode(AGSI_ZOPC); |
|
5647 |
ins_encode(z_siyform(mem, src)); |
|
5648 |
ins_pipe(pipe_class_dummy); |
|
5649 |
%} |
|
5650 |
||
5651 |
// Fallback: direct memory arithmetic not available |
|
5652 |
// Disadvantages: - CS-Loop required, very expensive. |
|
5653 |
// - more code generated (26 to xx bytes vs. 6 bytes) |
|
5654 |
instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{
|
|
5655 |
match(Set dst (GetAndAddL mem src)); |
|
5656 |
effect(KILL cr, TEMP_DEF dst, TEMP tmp); |
|
5657 |
ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); |
|
5658 |
format %{ "BEGIN ATOMIC {\n\t"
|
|
5659 |
" LG $dst,[$mem]\n\t" |
|
5660 |
" AGHIK $tmp,$dst,$src\n\t" |
|
5661 |
" CSG $dst,$tmp,$mem\n\t" |
|
5662 |
" retry if failed\n\t" |
|
5663 |
"} END ATOMIC" |
|
5664 |
%} |
|
5665 |
ins_encode %{
|
|
5666 |
Register Rdst = $dst$$Register; |
|
5667 |
Register Rtmp = $tmp$$Register; |
|
5668 |
int Isrc = $src$$constant; |
|
5669 |
Label retry; |
|
5670 |
||
5671 |
// Iterate until update with incremented value succeeds. |
|
5672 |
__ z_lg(Rdst, $mem$$Address); // current contents |
|
5673 |
__ bind(retry); |
|
5674 |
// Calculate incremented value. |
|
5675 |
if (VM_Version::has_DistinctOpnds()) {
|
|
5676 |
__ z_aghik(Rtmp, Rdst, Isrc); |
|
5677 |
} else {
|
|
5678 |
__ z_lgr(Rtmp, Rdst); |
|
5679 |
__ z_aghi(Rtmp, Isrc); |
|
5680 |
} |
|
5681 |
__ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. |
|
5682 |
__ z_brne(retry); // Yikes, concurrent update, need to retry. |
|
5683 |
%} |
|
5684 |
ins_pipe(pipe_class_dummy); |
|
5685 |
%} |
|
5686 |
||
5687 |
instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{
|
|
5688 |
match(Set dst (GetAndAddL mem src)); |
|
5689 |
effect(KILL cr, TEMP_DEF dst, TEMP tmp); |
|
5690 |
ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); |
|
5691 |
format %{ "BEGIN ATOMIC {\n\t"
|
|
5692 |
" LG $dst,[$mem]\n\t" |
|
5693 |
" LGR $tmp,$dst\n\t" |
|
5694 |
" AGFI $tmp,$src\n\t" |
|
5695 |
" CSG $dst,$tmp,$mem\n\t" |
|
5696 |
" retry if failed\n\t" |
|
5697 |
"} END ATOMIC" |
|
5698 |
%} |
|
5699 |
ins_encode %{
|
|
5700 |
Register Rdst = $dst$$Register; |
|
5701 |
Register Rtmp = $tmp$$Register; |
|
5702 |
int Isrc = $src$$constant; |
|
5703 |
Label retry; |
|
5704 |
||
5705 |
// Iterate until update with incremented value succeeds. |
|
5706 |
__ z_lg(Rdst, $mem$$Address); // current contents |
|
5707 |
__ bind(retry); |
|
5708 |
// Calculate incremented value. |
|
5709 |
__ z_lgr(Rtmp, Rdst); |
|
5710 |
__ z_agfi(Rtmp, Isrc); |
|
5711 |
__ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. |
|
5712 |
__ z_brne(retry); // Yikes, concurrent update, need to retry. |
|
5713 |
%} |
|
5714 |
ins_pipe(pipe_class_dummy); |
|
5715 |
%} |
|
5716 |
||
5717 |
instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{
|
|
5718 |
match(Set dst (GetAndAddL mem src)); |
|
5719 |
effect(KILL cr, TEMP_DEF dst, TEMP tmp); |
|
5720 |
ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); |
|
5721 |
format %{ "BEGIN ATOMIC {\n\t"
|
|
5722 |
" LG $dst,[$mem]\n\t" |
|
5723 |
" AGRK $tmp,$dst,$src\n\t" |
|
5724 |
" CSG $dst,$tmp,$mem\n\t" |
|
5725 |
" retry if failed\n\t" |
|
5726 |
"} END ATOMIC" |
|
5727 |
%} |
|
5728 |
ins_encode %{
|
|
5729 |
Register Rsrc = $src$$Register; |
|
5730 |
Register Rdst = $dst$$Register; |
|
5731 |
Register Rtmp = $tmp$$Register; |
|
5732 |
Label retry; |
|
5733 |
||
5734 |
// Iterate until update with incremented value succeeds. |
|
5735 |
__ z_lg(Rdst, $mem$$Address); // current contents |
|
5736 |
__ bind(retry); |
|
5737 |
// Calculate incremented value. |
|
5738 |
if (VM_Version::has_DistinctOpnds()) {
|
|
5739 |
__ z_agrk(Rtmp, Rdst, Rsrc); |
|
5740 |
} else {
|
|
5741 |
__ z_lgr(Rtmp, Rdst); |
|
5742 |
__ z_agr(Rtmp, Rsrc); |
|
5743 |
} |
|
5744 |
__ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. |
|
5745 |
__ z_brne(retry); // Yikes, concurrent update, need to retry. |
|
5746 |
%} |
|
5747 |
ins_pipe(pipe_class_dummy); |
|
5748 |
%} |
|
5749 |
||
5750 |
// Increment value in memory, save old value in dst. |
|
5751 |
instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{
|
|
5752 |
match(Set dst (GetAndAddI mem src)); |
|
5753 |
predicate(VM_Version::has_LoadAndALUAtomicV1()); |
|
5754 |
ins_cost(MEMORY_REF_COST + DEFAULT_COST); |
|
5755 |
size(6); |
|
5756 |
format %{ "LAA $dst,$src,[$mem]" %}
|
|
5757 |
ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %}
|
|
5758 |
ins_pipe(pipe_class_dummy); |
|
5759 |
%} |
|
5760 |
||
5761 |
// Increment value in memory, save old value in dst. |
|
5762 |
instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{
|
|
5763 |
match(Set dst (GetAndAddL mem src)); |
|
5764 |
predicate(VM_Version::has_LoadAndALUAtomicV1()); |
|
5765 |
ins_cost(MEMORY_REF_COST + DEFAULT_COST); |
|
5766 |
size(6); |
|
5767 |
format %{ "LAAG $dst,$src,[$mem]" %}
|
|
5768 |
ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %}
|
|
5769 |
ins_pipe(pipe_class_dummy); |
|
5770 |
%} |
|
5771 |
||
5772 |
||
5773 |
instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{
|
|
5774 |
match(Set dst (GetAndSetI mem dst)); |
|
5775 |
effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. |
|
5776 |
format %{ "XCHGI $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %}
|
|
5777 |
ins_encode(z_enc_SwapI(mem, dst, tmp)); |
|
5778 |
ins_pipe(pipe_class_dummy); |
|
5779 |
%} |
|
5780 |
||
5781 |
instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{
|
|
5782 |
match(Set dst (GetAndSetL mem dst)); |
|
5783 |
effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. |
|
5784 |
format %{ "XCHGL $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %}
|
|
5785 |
ins_encode(z_enc_SwapL(mem, dst, tmp)); |
|
5786 |
ins_pipe(pipe_class_dummy); |
|
5787 |
%} |
|
5788 |
||
5789 |
instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{
|
|
5790 |
match(Set dst (GetAndSetN mem dst)); |
|
5791 |
effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. |
|
5792 |
format %{ "XCHGN $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %}
|
|
5793 |
ins_encode(z_enc_SwapI(mem, dst, tmp)); |
|
5794 |
ins_pipe(pipe_class_dummy); |
|
5795 |
%} |
|
5796 |
||
5797 |
instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{
|
|
5798 |
match(Set dst (GetAndSetP mem dst)); |
|
5799 |
effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. |
|
5800 |
format %{ "XCHGP $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %}
|
|
5801 |
ins_encode(z_enc_SwapL(mem, dst, tmp)); |
|
5802 |
ins_pipe(pipe_class_dummy); |
|
5803 |
%} |
|
5804 |
||
5805 |
||
5806 |
//----------Arithmetic Instructions-------------------------------------------- |
|
5807 |
||
5808 |
// The rules are sorted by right operand type and operand length. Please keep |
|
5809 |
// it that way. |
|
5810 |
// Left operand type is always reg. Left operand len is I, L, P |
|
5811 |
// Right operand type is reg, imm, mem. Right operand len is S, I, L, P |
|
5812 |
// Special instruction formats, e.g. multi-operand, are inserted at the end. |
|
5813 |
||
5814 |
// ADD |
|
5815 |
||
5816 |
// REG = REG + REG |
|
5817 |
||
5818 |
// Register Addition |
|
5819 |
instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
|
|
5820 |
match(Set dst (AddI dst src)); |
|
5821 |
effect(KILL cr); |
|
5822 |
// TODO: s390 port size(FIXED_SIZE); |
|
5823 |
format %{ "AR $dst,$src\t # int CISC ALU" %}
|
|
5824 |
opcode(AR_ZOPC); |
|
5825 |
ins_encode(z_rrform(dst, src)); |
|
5826 |
ins_pipe(pipe_class_dummy); |
|
5827 |
%} |
|
5828 |
||
5829 |
// Avoid use of LA(Y) for general ALU operation. |
|
5830 |
instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
|
|
5831 |
match(Set dst (AddI src1 src2)); |
|
5832 |
effect(KILL cr); |
|
5833 |
predicate(VM_Version::has_DistinctOpnds()); |
|
5834 |
ins_cost(DEFAULT_COST); |
|
5835 |
size(4); |
|
5836 |
format %{ "ARK $dst,$src1,$src2\t # int RISC ALU" %}
|
|
5837 |
opcode(ARK_ZOPC); |
|
5838 |
ins_encode(z_rrfform(dst, src1, src2)); |
|
5839 |
ins_pipe(pipe_class_dummy); |
|
5840 |
%} |
|
5841 |
||
5842 |
// REG = REG + IMM |
|
5843 |
||
5844 |
// Avoid use of LA(Y) for general ALU operation. |
|
5845 |
// Immediate Addition |
|
5846 |
instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{
|
|
5847 |
match(Set dst (AddI dst con)); |
|
5848 |
effect(KILL cr); |
|
5849 |
ins_cost(DEFAULT_COST); |
|
5850 |
// TODO: s390 port size(FIXED_SIZE); |
|
5851 |
format %{ "AHI $dst,$con\t # int CISC ALU" %}
|
|
5852 |
opcode(AHI_ZOPC); |
|
5853 |
ins_encode(z_riform_signed(dst, con)); |
|
5854 |
ins_pipe(pipe_class_dummy); |
|
5855 |
%} |
|
5856 |
||
5857 |
// Avoid use of LA(Y) for general ALU operation. |
|
5858 |
// Immediate Addition |
|
5859 |
instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{
|
|
5860 |
match(Set dst (AddI src con)); |
|
5861 |
effect(KILL cr); |
|
5862 |
predicate( VM_Version::has_DistinctOpnds()); |
|
5863 |
ins_cost(DEFAULT_COST); |
|
5864 |
// TODO: s390 port size(FIXED_SIZE); |
|
5865 |
format %{ "AHIK $dst,$src,$con\t # int RISC ALU" %}
|
|
5866 |
opcode(AHIK_ZOPC); |
|
5867 |
ins_encode(z_rieform_d(dst, src, con)); |
|
5868 |
ins_pipe(pipe_class_dummy); |
|
5869 |
%} |
|
5870 |
||
5871 |
// Immediate Addition |
|
5872 |
instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{
|
|
5873 |
match(Set dst (AddI dst src)); |
|
5874 |
effect(KILL cr); |
|
5875 |
ins_cost(DEFAULT_COST_HIGH); |
|
5876 |
size(6); |
|
5877 |
format %{ "AFI $dst,$src" %}
|
|
5878 |
opcode(AFI_ZOPC); |
|
5879 |
ins_encode(z_rilform_signed(dst, src)); |
|
5880 |
ins_pipe(pipe_class_dummy); |
|
5881 |
%} |
|
5882 |
||
5883 |
// Immediate Addition |
|
5884 |
instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{
|
|
5885 |
match(Set dst (AddI src con)); |
|
5886 |
predicate(PreferLAoverADD); |
|
5887 |
ins_cost(DEFAULT_COST_LOW); |
|
5888 |
size(4); |
|
5889 |
format %{ "LA $dst,$con(,$src)\t # int d12(,b)" %}
|
|
5890 |
opcode(LA_ZOPC); |
|
5891 |
ins_encode(z_rxform_imm_reg(dst, con, src)); |
|
5892 |
ins_pipe(pipe_class_dummy); |
|
5893 |
%} |
|
5894 |
||
5895 |
// Immediate Addition |
|
5896 |
instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{
|
|
5897 |
match(Set dst (AddI src con)); |
|
5898 |
predicate(PreferLAoverADD); |
|
5899 |
ins_cost(DEFAULT_COST); |
|
5900 |
size(6); |
|
5901 |
format %{ "LAY $dst,$con(,$src)\t # int d20(,b)" %}
|
|
5902 |
opcode(LAY_ZOPC); |
|
5903 |
ins_encode(z_rxyform_imm_reg(dst, con, src)); |
|
5904 |
ins_pipe(pipe_class_dummy); |
|
5905 |
%} |
|
5906 |
||
5907 |
instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{
|
|
5908 |
match(Set dst (AddI (AddI src1 src2) con)); |
|
5909 |
predicate( PreferLAoverADD); |
|
5910 |
ins_cost(DEFAULT_COST_LOW); |
|
5911 |
size(4); |
|
5912 |
format %{ "LA $dst,$con($src1,$src2)\t # int d12(x,b)" %}
|
|
5913 |
opcode(LA_ZOPC); |
|
5914 |
ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); |
|
5915 |
ins_pipe(pipe_class_dummy); |
|
5916 |
%} |
|
5917 |
||
5918 |
instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{
|
|
5919 |
match(Set dst (AddI (AddI src1 src2) con)); |
|
5920 |
predicate(PreferLAoverADD); |
|
5921 |
ins_cost(DEFAULT_COST); |
|
5922 |
size(6); |
|
5923 |
format %{ "LAY $dst,$con($src1,$src2)\t # int d20(x,b)" %}
|
|
5924 |
opcode(LAY_ZOPC); |
|
5925 |
ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); |
|
5926 |
ins_pipe(pipe_class_dummy); |
|
5927 |
%} |
|
5928 |
||
5929 |
// REG = REG + MEM |
|
5930 |
||
5931 |
instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
|
|
5932 |
match(Set dst (AddI dst (LoadI src))); |
|
5933 |
effect(KILL cr); |
|
5934 |
ins_cost(MEMORY_REF_COST); |
|
5935 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
5936 |
format %{ "A(Y) $dst, $src\t # int" %}
|
|
5937 |
opcode(AY_ZOPC, A_ZOPC); |
|
5938 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
5939 |
ins_pipe(pipe_class_dummy); |
|
5940 |
%} |
|
5941 |
||
5942 |
// MEM = MEM + IMM |
|
5943 |
||
5944 |
// Add Immediate to 4-byte memory operand and result |
|
5945 |
instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{
|
|
5946 |
match(Set mem (StoreI mem (AddI (LoadI mem) src))); |
|
5947 |
effect(KILL cr); |
|
5948 |
predicate(VM_Version::has_MemWithImmALUOps()); |
|
5949 |
ins_cost(MEMORY_REF_COST); |
|
5950 |
size(6); |
|
5951 |
format %{ "ASI $mem,$src\t # direct mem add 4" %}
|
|
5952 |
opcode(ASI_ZOPC); |
|
5953 |
ins_encode(z_siyform(mem, src)); |
|
5954 |
ins_pipe(pipe_class_dummy); |
|
5955 |
%} |
|
5956 |
||
5957 |
||
5958 |
// |
|
5959 |
||
5960 |
// REG = REG + REG |
|
5961 |
||
5962 |
instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{
|
|
5963 |
match(Set dst (AddL dst (ConvI2L src))); |
|
5964 |
effect(KILL cr); |
|
5965 |
size(4); |
|
5966 |
format %{ "AGFR $dst,$src\t # long<-int CISC ALU" %}
|
|
5967 |
opcode(AGFR_ZOPC); |
|
5968 |
ins_encode(z_rreform(dst, src)); |
|
5969 |
ins_pipe(pipe_class_dummy); |
|
5970 |
%} |
|
5971 |
||
5972 |
instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
|
|
5973 |
match(Set dst (AddL dst src)); |
|
5974 |
effect(KILL cr); |
|
5975 |
// TODO: s390 port size(FIXED_SIZE); |
|
5976 |
format %{ "AGR $dst, $src\t # long CISC ALU" %}
|
|
5977 |
opcode(AGR_ZOPC); |
|
5978 |
ins_encode(z_rreform(dst, src)); |
|
5979 |
ins_pipe(pipe_class_dummy); |
|
5980 |
%} |
|
5981 |
||
5982 |
// Avoid use of LA(Y) for general ALU operation. |
|
5983 |
instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
|
|
5984 |
match(Set dst (AddL src1 src2)); |
|
5985 |
effect(KILL cr); |
|
5986 |
predicate(VM_Version::has_DistinctOpnds()); |
|
5987 |
ins_cost(DEFAULT_COST); |
|
5988 |
size(4); |
|
5989 |
format %{ "AGRK $dst,$src1,$src2\t # long RISC ALU" %}
|
|
5990 |
opcode(AGRK_ZOPC); |
|
5991 |
ins_encode(z_rrfform(dst, src1, src2)); |
|
5992 |
ins_pipe(pipe_class_dummy); |
|
5993 |
%} |
|
5994 |
||
5995 |
// REG = REG + IMM |
|
5996 |
||
5997 |
instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{
|
|
5998 |
match(Set dst (AddL src con)); |
|
5999 |
predicate( PreferLAoverADD); |
|
6000 |
ins_cost(DEFAULT_COST_LOW); |
|
6001 |
size(4); |
|
6002 |
format %{ "LA $dst,$con(,$src)\t # long d12(,b)" %}
|
|
6003 |
opcode(LA_ZOPC); |
|
6004 |
ins_encode(z_rxform_imm_reg(dst, con, src)); |
|
6005 |
ins_pipe(pipe_class_dummy); |
|
6006 |
%} |
|
6007 |
||
6008 |
instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{
|
|
6009 |
match(Set dst (AddL src con)); |
|
6010 |
predicate(PreferLAoverADD); |
|
6011 |
ins_cost(DEFAULT_COST); |
|
6012 |
size(6); |
|
6013 |
format %{ "LAY $dst,$con(,$src)\t # long d20(,b)" %}
|
|
6014 |
opcode(LAY_ZOPC); |
|
6015 |
ins_encode(z_rxyform_imm_reg(dst, con, src)); |
|
6016 |
ins_pipe(pipe_class_dummy); |
|
6017 |
%} |
|
6018 |
||
6019 |
instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{
|
|
6020 |
match(Set dst (AddL dst con)); |
|
6021 |
effect(KILL cr); |
|
6022 |
ins_cost(DEFAULT_COST_HIGH); |
|
6023 |
size(6); |
|
6024 |
format %{ "AGFI $dst,$con\t # long CISC ALU" %}
|
|
6025 |
opcode(AGFI_ZOPC); |
|
6026 |
ins_encode(z_rilform_signed(dst, con)); |
|
6027 |
ins_pipe(pipe_class_dummy); |
|
6028 |
%} |
|
6029 |
||
6030 |
// Avoid use of LA(Y) for general ALU operation. |
|
6031 |
instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{
|
|
6032 |
match(Set dst (AddL dst con)); |
|
6033 |
effect(KILL cr); |
|
6034 |
ins_cost(DEFAULT_COST); |
|
6035 |
// TODO: s390 port size(FIXED_SIZE); |
|
6036 |
format %{ "AGHI $dst,$con\t # long CISC ALU" %}
|
|
6037 |
opcode(AGHI_ZOPC); |
|
6038 |
ins_encode(z_riform_signed(dst, con)); |
|
6039 |
ins_pipe(pipe_class_dummy); |
|
6040 |
%} |
|
6041 |
||
6042 |
// Avoid use of LA(Y) for general ALU operation. |
|
6043 |
instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{
|
|
6044 |
match(Set dst (AddL src con)); |
|
6045 |
effect(KILL cr); |
|
6046 |
predicate( VM_Version::has_DistinctOpnds()); |
|
6047 |
ins_cost(DEFAULT_COST); |
|
6048 |
size(6); |
|
6049 |
format %{ "AGHIK $dst,$src,$con\t # long RISC ALU" %}
|
|
6050 |
opcode(AGHIK_ZOPC); |
|
6051 |
ins_encode(z_rieform_d(dst, src, con)); |
|
6052 |
ins_pipe(pipe_class_dummy); |
|
6053 |
%} |
|
6054 |
||
6055 |
// REG = REG + MEM |
|
6056 |
||
6057 |
instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
|
|
6058 |
match(Set dst (AddL dst (ConvI2L (LoadI src)))); |
|
6059 |
effect(KILL cr); |
|
6060 |
ins_cost(MEMORY_REF_COST); |
|
6061 |
size(Z_DISP3_SIZE); |
|
6062 |
format %{ "AGF $dst, $src\t # long/int" %}
|
|
6063 |
opcode(AGF_ZOPC, AGF_ZOPC); |
|
6064 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
6065 |
ins_pipe(pipe_class_dummy); |
|
6066 |
%} |
|
6067 |
||
6068 |
instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
|
|
6069 |
match(Set dst (AddL dst (LoadL src))); |
|
6070 |
effect(KILL cr); |
|
6071 |
ins_cost(MEMORY_REF_COST); |
|
6072 |
size(Z_DISP3_SIZE); |
|
6073 |
format %{ "AG $dst, $src\t # long" %}
|
|
6074 |
opcode(AG_ZOPC, AG_ZOPC); |
|
6075 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
6076 |
ins_pipe(pipe_class_dummy); |
|
6077 |
%} |
|
6078 |
||
6079 |
instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{
|
|
6080 |
match(Set dst (AddL (AddL src1 src2) con)); |
|
6081 |
predicate( PreferLAoverADD); |
|
6082 |
ins_cost(DEFAULT_COST_LOW); |
|
6083 |
size(4); |
|
6084 |
format %{ "LA $dst,$con($src1,$src2)\t # long d12(x,b)" %}
|
|
6085 |
opcode(LA_ZOPC); |
|
6086 |
ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); |
|
6087 |
ins_pipe(pipe_class_dummy); |
|
6088 |
%} |
|
6089 |
||
6090 |
instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{
|
|
6091 |
match(Set dst (AddL (AddL src1 src2) con)); |
|
6092 |
predicate(PreferLAoverADD); |
|
6093 |
ins_cost(DEFAULT_COST); |
|
6094 |
size(6); |
|
6095 |
format %{ "LAY $dst,$con($src1,$src2)\t # long d20(x,b)" %}
|
|
6096 |
opcode(LAY_ZOPC); |
|
6097 |
ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); |
|
6098 |
ins_pipe(pipe_class_dummy); |
|
6099 |
%} |
|
6100 |
||
6101 |
// MEM = MEM + IMM |
|
6102 |
||
6103 |
// Add Immediate to 8-byte memory operand and result. |
|
6104 |
instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
|
|
6105 |
match(Set mem (StoreL mem (AddL (LoadL mem) src))); |
|
6106 |
effect(KILL cr); |
|
6107 |
predicate(VM_Version::has_MemWithImmALUOps()); |
|
6108 |
ins_cost(MEMORY_REF_COST); |
|
6109 |
size(6); |
|
6110 |
format %{ "AGSI $mem,$src\t # direct mem add 8" %}
|
|
6111 |
opcode(AGSI_ZOPC); |
|
6112 |
ins_encode(z_siyform(mem, src)); |
|
6113 |
ins_pipe(pipe_class_dummy); |
|
6114 |
%} |
|
6115 |
||
6116 |
||
6117 |
// REG = REG + REG |
|
6118 |
||
6119 |
// Ptr Addition |
|
6120 |
instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{
|
|
6121 |
match(Set dst (AddP src1 src2)); |
|
6122 |
predicate( PreferLAoverADD); |
|
6123 |
ins_cost(DEFAULT_COST); |
|
6124 |
size(4); |
|
6125 |
format %{ "LA $dst,#0($src1,$src2)\t # ptr 0(x,b)" %}
|
|
6126 |
opcode(LA_ZOPC); |
|
6127 |
ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2)); |
|
6128 |
ins_pipe(pipe_class_dummy); |
|
6129 |
%} |
|
6130 |
||
6131 |
// Ptr Addition |
|
6132 |
// Avoid use of LA(Y) for general ALU operation. |
|
6133 |
instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{
|
|
6134 |
match(Set dst (AddP dst src)); |
|
6135 |
effect(KILL cr); |
|
6136 |
predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds()); |
|
6137 |
ins_cost(DEFAULT_COST); |
|
6138 |
// TODO: s390 port size(FIXED_SIZE); |
|
6139 |
format %{ "ALGR $dst,$src\t # ptr CICS ALU" %}
|
|
6140 |
opcode(ALGR_ZOPC); |
|
6141 |
ins_encode(z_rreform(dst, src)); |
|
6142 |
ins_pipe(pipe_class_dummy); |
|
6143 |
%} |
|
6144 |
||
6145 |
// Ptr Addition |
|
6146 |
// Avoid use of LA(Y) for general ALU operation. |
|
6147 |
instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{
|
|
6148 |
match(Set dst (AddP src1 src2)); |
|
6149 |
effect(KILL cr); |
|
6150 |
predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds()); |
|
6151 |
ins_cost(DEFAULT_COST); |
|
6152 |
// TODO: s390 port size(FIXED_SIZE); |
|
6153 |
format %{ "ALGRK $dst,$src1,$src2\t # ptr RISC ALU" %}
|
|
6154 |
opcode(ALGRK_ZOPC); |
|
6155 |
ins_encode(z_rrfform(dst, src1, src2)); |
|
6156 |
ins_pipe(pipe_class_dummy); |
|
6157 |
%} |
|
6158 |
||
6159 |
// REG = REG + IMM |
|
6160 |
||
6161 |
instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{
|
|
6162 |
match(Set dst (AddP src con)); |
|
6163 |
predicate( PreferLAoverADD); |
|
6164 |
ins_cost(DEFAULT_COST_LOW); |
|
6165 |
size(4); |
|
6166 |
format %{ "LA $dst,$con(,$src)\t # ptr d12(,b)" %}
|
|
6167 |
opcode(LA_ZOPC); |
|
6168 |
ins_encode(z_rxform_imm_reg(dst, con, src)); |
|
6169 |
ins_pipe(pipe_class_dummy); |
|
6170 |
%} |
|
6171 |
||
6172 |
// Avoid use of LA(Y) for general ALU operation. |
|
6173 |
instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{
|
|
6174 |
match(Set dst (AddP dst src)); |
|
6175 |
effect(KILL cr); |
|
6176 |
predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds()); |
|
6177 |
ins_cost(DEFAULT_COST); |
|
6178 |
// TODO: s390 port size(FIXED_SIZE); |
|
6179 |
format %{ "AGHI $dst,$src\t # ptr CISC ALU" %}
|
|
6180 |
opcode(AGHI_ZOPC); |
|
6181 |
ins_encode(z_riform_signed(dst, src)); |
|
6182 |
ins_pipe(pipe_class_dummy); |
|
6183 |
%} |
|
6184 |
||
6185 |
// Avoid use of LA(Y) for general ALU operation. |
|
6186 |
instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{
|
|
6187 |
match(Set dst (AddP src con)); |
|
6188 |
effect(KILL cr); |
|
6189 |
predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds()); |
|
6190 |
ins_cost(DEFAULT_COST); |
|
6191 |
// TODO: s390 port size(FIXED_SIZE); |
|
6192 |
format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %}
|
|
6193 |
opcode(ALGHSIK_ZOPC); |
|
6194 |
ins_encode(z_rieform_d(dst, src, con)); |
|
6195 |
ins_pipe(pipe_class_dummy); |
|
6196 |
%} |
|
6197 |
||
6198 |
instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{
|
|
6199 |
match(Set dst (AddP src con)); |
|
6200 |
predicate(PreferLAoverADD); |
|
6201 |
ins_cost(DEFAULT_COST); |
|
6202 |
size(6); |
|
6203 |
format %{ "LAY $dst,$con(,$src)\t # ptr d20(,b)" %}
|
|
6204 |
opcode(LAY_ZOPC); |
|
6205 |
ins_encode(z_rxyform_imm_reg(dst, con, src)); |
|
6206 |
ins_pipe(pipe_class_dummy); |
|
6207 |
%} |
|
6208 |
||
6209 |
// Pointer Immediate Addition |
|
6210 |
instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{
|
|
6211 |
match(Set dst (AddP dst src)); |
|
6212 |
effect(KILL cr); |
|
6213 |
ins_cost(DEFAULT_COST_HIGH); |
|
6214 |
// TODO: s390 port size(FIXED_SIZE); |
|
6215 |
format %{ "AGFI $dst,$src\t # ptr" %}
|
|
6216 |
opcode(AGFI_ZOPC); |
|
6217 |
ins_encode(z_rilform_signed(dst, src)); |
|
6218 |
ins_pipe(pipe_class_dummy); |
|
6219 |
%} |
|
6220 |
||
6221 |
// REG = REG1 + REG2 + IMM |
|
6222 |
||
6223 |
instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{
|
|
6224 |
match(Set dst (AddP (AddP src1 src2) con)); |
|
6225 |
predicate( PreferLAoverADD); |
|
6226 |
ins_cost(DEFAULT_COST_LOW); |
|
6227 |
size(4); |
|
6228 |
format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
|
|
6229 |
opcode(LA_ZOPC); |
|
6230 |
ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); |
|
6231 |
ins_pipe(pipe_class_dummy); |
|
6232 |
%} |
|
6233 |
||
6234 |
instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{
|
|
6235 |
match(Set dst (AddP (AddP src1 src2) con)); |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
6236 |
predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0); |
| 42065 | 6237 |
ins_cost(DEFAULT_COST_LOW); |
6238 |
size(4); |
|
6239 |
format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
|
|
6240 |
opcode(LA_ZOPC); |
|
6241 |
ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); |
|
6242 |
ins_pipe(pipe_class_dummy); |
|
6243 |
%} |
|
6244 |
||
6245 |
instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{
|
|
6246 |
match(Set dst (AddP (AddP src1 src2) con)); |
|
6247 |
predicate(PreferLAoverADD); |
|
6248 |
ins_cost(DEFAULT_COST); |
|
6249 |
// TODO: s390 port size(FIXED_SIZE); |
|
6250 |
format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
|
|
6251 |
opcode(LAY_ZOPC); |
|
6252 |
ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); |
|
6253 |
ins_pipe(pipe_class_dummy); |
|
6254 |
%} |
|
6255 |
||
6256 |
instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{
|
|
6257 |
match(Set dst (AddP (AddP src1 src2) con)); |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
6258 |
predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0); |
| 42065 | 6259 |
ins_cost(DEFAULT_COST); |
6260 |
// TODO: s390 port size(FIXED_SIZE); |
|
6261 |
format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
|
|
6262 |
opcode(LAY_ZOPC); |
|
6263 |
ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); |
|
6264 |
ins_pipe(pipe_class_dummy); |
|
6265 |
%} |
|
6266 |
||
6267 |
// MEM = MEM + IMM |
|
6268 |
||
6269 |
// Add Immediate to 8-byte memory operand and result |
|
6270 |
instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
|
|
6271 |
match(Set mem (StoreP mem (AddP (LoadP mem) src))); |
|
6272 |
effect(KILL cr); |
|
6273 |
predicate(VM_Version::has_MemWithImmALUOps()); |
|
6274 |
ins_cost(MEMORY_REF_COST); |
|
6275 |
size(6); |
|
6276 |
format %{ "AGSI $mem,$src\t # direct mem add 8 (ptr)" %}
|
|
6277 |
opcode(AGSI_ZOPC); |
|
6278 |
ins_encode(z_siyform(mem, src)); |
|
6279 |
ins_pipe(pipe_class_dummy); |
|
6280 |
%} |
|
6281 |
||
6282 |
// SUB |
|
6283 |
||
6284 |
// Register Subtraction |
|
6285 |
instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
|
|
6286 |
match(Set dst (SubI dst src)); |
|
6287 |
effect(KILL cr); |
|
6288 |
// TODO: s390 port size(FIXED_SIZE); |
|
6289 |
format %{ "SR $dst,$src\t # int CISC ALU" %}
|
|
6290 |
opcode(SR_ZOPC); |
|
6291 |
ins_encode(z_rrform(dst, src)); |
|
6292 |
ins_pipe(pipe_class_dummy); |
|
6293 |
%} |
|
6294 |
||
6295 |
instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
|
|
6296 |
match(Set dst (SubI src1 src2)); |
|
6297 |
effect(KILL cr); |
|
6298 |
predicate(VM_Version::has_DistinctOpnds()); |
|
6299 |
ins_cost(DEFAULT_COST); |
|
6300 |
size(4); |
|
6301 |
format %{ "SRK $dst,$src1,$src2\t # int RISC ALU" %}
|
|
6302 |
opcode(SRK_ZOPC); |
|
6303 |
ins_encode(z_rrfform(dst, src1, src2)); |
|
6304 |
ins_pipe(pipe_class_dummy); |
|
6305 |
%} |
|
6306 |
||
6307 |
instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
|
|
6308 |
match(Set dst (SubI dst (LoadI src))); |
|
6309 |
effect(KILL cr); |
|
6310 |
ins_cost(MEMORY_REF_COST); |
|
6311 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
6312 |
format %{ "S(Y) $dst, $src\t # int" %}
|
|
6313 |
opcode(SY_ZOPC, S_ZOPC); |
|
6314 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
6315 |
ins_pipe(pipe_class_dummy); |
|
6316 |
%} |
|
6317 |
||
6318 |
instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{
|
|
6319 |
match(Set dst (SubI zero src)); |
|
6320 |
effect(KILL cr); |
|
6321 |
size(2); |
|
6322 |
format %{ "NEG $dst, $src" %}
|
|
6323 |
ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %}
|
|
6324 |
ins_pipe(pipe_class_dummy); |
|
6325 |
%} |
|
6326 |
||
6327 |
// |
|
6328 |
||
6329 |
// Long subtraction |
|
6330 |
instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
|
|
6331 |
match(Set dst (SubL dst src)); |
|
6332 |
effect(KILL cr); |
|
6333 |
// TODO: s390 port size(FIXED_SIZE); |
|
6334 |
format %{ "SGR $dst,$src\t # int CISC ALU" %}
|
|
6335 |
opcode(SGR_ZOPC); |
|
6336 |
ins_encode(z_rreform(dst, src)); |
|
6337 |
ins_pipe(pipe_class_dummy); |
|
6338 |
%} |
|
6339 |
||
6340 |
// Avoid use of LA(Y) for general ALU operation. |
|
6341 |
instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
|
|
6342 |
match(Set dst (SubL src1 src2)); |
|
6343 |
effect(KILL cr); |
|
6344 |
predicate(VM_Version::has_DistinctOpnds()); |
|
6345 |
ins_cost(DEFAULT_COST); |
|
6346 |
size(4); |
|
6347 |
format %{ "SGRK $dst,$src1,$src2\t # int RISC ALU" %}
|
|
6348 |
opcode(SGRK_ZOPC); |
|
6349 |
ins_encode(z_rrfform(dst, src1, src2)); |
|
6350 |
ins_pipe(pipe_class_dummy); |
|
6351 |
%} |
|
6352 |
||
6353 |
instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{
|
|
6354 |
match(Set dst (SubL dst (ConvI2L src))); |
|
6355 |
effect(KILL cr); |
|
6356 |
size(4); |
|
6357 |
format %{ "SGFR $dst, $src\t # int CISC ALU" %}
|
|
6358 |
opcode(SGFR_ZOPC); |
|
6359 |
ins_encode(z_rreform(dst, src)); |
|
6360 |
ins_pipe(pipe_class_dummy); |
|
6361 |
%} |
|
6362 |
||
6363 |
instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
|
|
6364 |
match(Set dst (SubL dst (ConvI2L (LoadI src)))); |
|
6365 |
effect(KILL cr); |
|
6366 |
ins_cost(MEMORY_REF_COST); |
|
6367 |
size(Z_DISP3_SIZE); |
|
6368 |
format %{ "SGF $dst, $src\t # long/int" %}
|
|
6369 |
opcode(SGF_ZOPC, SGF_ZOPC); |
|
6370 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
6371 |
ins_pipe(pipe_class_dummy); |
|
6372 |
%} |
|
6373 |
||
6374 |
instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
|
|
6375 |
match(Set dst (SubL dst (LoadL src))); |
|
6376 |
effect(KILL cr); |
|
6377 |
ins_cost(MEMORY_REF_COST); |
|
6378 |
size(Z_DISP3_SIZE); |
|
6379 |
format %{ "SG $dst, $src\t # long" %}
|
|
6380 |
opcode(SG_ZOPC, SG_ZOPC); |
|
6381 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
6382 |
ins_pipe(pipe_class_dummy); |
|
6383 |
%} |
|
6384 |
||
6385 |
// Moved declaration of negL_reg_reg before encode nodes, where it is used. |
|
6386 |
||
6387 |
// MUL |
|
6388 |
||
6389 |
// Register Multiplication |
|
6390 |
instruct mulI_reg_reg(iRegI dst, iRegI src) %{
|
|
6391 |
match(Set dst (MulI dst src)); |
|
6392 |
ins_cost(DEFAULT_COST); |
|
6393 |
size(4); |
|
6394 |
format %{ "MSR $dst, $src" %}
|
|
6395 |
opcode(MSR_ZOPC); |
|
6396 |
ins_encode(z_rreform(dst, src)); |
|
6397 |
ins_pipe(pipe_class_dummy); |
|
6398 |
%} |
|
6399 |
||
6400 |
// Immediate Multiplication |
|
6401 |
instruct mulI_reg_imm16(iRegI dst, immI16 con) %{
|
|
6402 |
match(Set dst (MulI dst con)); |
|
6403 |
ins_cost(DEFAULT_COST); |
|
6404 |
// TODO: s390 port size(FIXED_SIZE); |
|
6405 |
format %{ "MHI $dst,$con" %}
|
|
6406 |
opcode(MHI_ZOPC); |
|
6407 |
ins_encode(z_riform_signed(dst,con)); |
|
6408 |
ins_pipe(pipe_class_dummy); |
|
6409 |
%} |
|
6410 |
||
6411 |
// Immediate (32bit) Multiplication |
|
6412 |
instruct mulI_reg_imm32(iRegI dst, immI con) %{
|
|
6413 |
match(Set dst (MulI dst con)); |
|
6414 |
ins_cost(DEFAULT_COST); |
|
6415 |
size(6); |
|
6416 |
format %{ "MSFI $dst,$con" %}
|
|
6417 |
opcode(MSFI_ZOPC); |
|
6418 |
ins_encode(z_rilform_signed(dst,con)); |
|
6419 |
ins_pipe(pipe_class_dummy); |
|
6420 |
%} |
|
6421 |
||
6422 |
instruct mulI_Reg_mem(iRegI dst, memory src)%{
|
|
6423 |
match(Set dst (MulI dst (LoadI src))); |
|
6424 |
ins_cost(MEMORY_REF_COST); |
|
6425 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
6426 |
format %{ "MS(Y) $dst, $src\t # int" %}
|
|
6427 |
opcode(MSY_ZOPC, MS_ZOPC); |
|
6428 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
6429 |
ins_pipe(pipe_class_dummy); |
|
6430 |
%} |
|
6431 |
||
6432 |
// |
|
6433 |
||
6434 |
instruct mulL_reg_regI(iRegL dst, iRegI src) %{
|
|
6435 |
match(Set dst (MulL dst (ConvI2L src))); |
|
6436 |
ins_cost(DEFAULT_COST); |
|
6437 |
// TODO: s390 port size(FIXED_SIZE); |
|
6438 |
format %{ "MSGFR $dst $src\t # long/int" %}
|
|
6439 |
opcode(MSGFR_ZOPC); |
|
6440 |
ins_encode(z_rreform(dst, src)); |
|
6441 |
ins_pipe(pipe_class_dummy); |
|
6442 |
%} |
|
6443 |
||
6444 |
instruct mulL_reg_reg(iRegL dst, iRegL src) %{
|
|
6445 |
match(Set dst (MulL dst src)); |
|
6446 |
ins_cost(DEFAULT_COST); |
|
6447 |
size(4); |
|
6448 |
format %{ "MSGR $dst $src\t # long" %}
|
|
6449 |
opcode(MSGR_ZOPC); |
|
6450 |
ins_encode(z_rreform(dst, src)); |
|
6451 |
ins_pipe(pipe_class_dummy); |
|
6452 |
%} |
|
6453 |
||
6454 |
// Immediate Multiplication |
|
6455 |
instruct mulL_reg_imm16(iRegL dst, immL16 src) %{
|
|
6456 |
match(Set dst (MulL dst src)); |
|
6457 |
ins_cost(DEFAULT_COST); |
|
6458 |
// TODO: s390 port size(FIXED_SIZE); |
|
6459 |
format %{ "MGHI $dst,$src\t # long" %}
|
|
6460 |
opcode(MGHI_ZOPC); |
|
6461 |
ins_encode(z_riform_signed(dst, src)); |
|
6462 |
ins_pipe(pipe_class_dummy); |
|
6463 |
%} |
|
6464 |
||
6465 |
// Immediate (32bit) Multiplication |
|
6466 |
instruct mulL_reg_imm32(iRegL dst, immL32 con) %{
|
|
6467 |
match(Set dst (MulL dst con)); |
|
6468 |
ins_cost(DEFAULT_COST); |
|
6469 |
size(6); |
|
6470 |
format %{ "MSGFI $dst,$con" %}
|
|
6471 |
opcode(MSGFI_ZOPC); |
|
6472 |
ins_encode(z_rilform_signed(dst,con)); |
|
6473 |
ins_pipe(pipe_class_dummy); |
|
6474 |
%} |
|
6475 |
||
6476 |
instruct mulL_Reg_memI(iRegL dst, memory src)%{
|
|
6477 |
match(Set dst (MulL dst (ConvI2L (LoadI src)))); |
|
6478 |
ins_cost(MEMORY_REF_COST); |
|
6479 |
size(Z_DISP3_SIZE); |
|
6480 |
format %{ "MSGF $dst, $src\t # long" %}
|
|
6481 |
opcode(MSGF_ZOPC, MSGF_ZOPC); |
|
6482 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
6483 |
ins_pipe(pipe_class_dummy); |
|
6484 |
%} |
|
6485 |
||
6486 |
instruct mulL_Reg_mem(iRegL dst, memory src)%{
|
|
6487 |
match(Set dst (MulL dst (LoadL src))); |
|
6488 |
ins_cost(MEMORY_REF_COST); |
|
6489 |
size(Z_DISP3_SIZE); |
|
6490 |
format %{ "MSG $dst, $src\t # long" %}
|
|
6491 |
opcode(MSG_ZOPC, MSG_ZOPC); |
|
6492 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
6493 |
ins_pipe(pipe_class_dummy); |
|
6494 |
%} |
|
6495 |
||
|
47606
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6496 |
instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{
|
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6497 |
match(Set Rdst (MulHiL Rsrc1 Rsrc2)); |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6498 |
effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr); |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6499 |
ins_cost(7*DEFAULT_COST); |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6500 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6501 |
format %{ "MulHiL $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %}
|
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6502 |
ins_encode%{
|
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6503 |
Register dst = $Rdst$$Register; |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6504 |
Register src1 = $Rsrc1$$Register; |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6505 |
Register src2 = $Rsrc2$$Register; |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6506 |
Register tmp1 = $Rtmp1$$Register; |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6507 |
Register tmp2 = $Rdst$$Register; |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6508 |
// z/Architecture has only unsigned multiply (64 * 64 -> 128). |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6509 |
// implementing mulhs(a,b) = mulhu(a,b) – (a & (b>>63)) – (b & (a>>63)) |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6510 |
__ z_srag(tmp2, src1, 63); // a>>63 |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6511 |
__ z_srag(tmp1, src2, 63); // b>>63 |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6512 |
__ z_ngr(tmp2, src2); // b & (a>>63) |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6513 |
__ z_ngr(tmp1, src1); // a & (b>>63) |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6514 |
__ z_agr(tmp1, tmp2); // ((a & (b>>63)) + (b & (a>>63))) |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6515 |
__ z_mlgr(dst, src2); // tricky: 128-bit product is written to even/odd pair (dst,src1), |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6516 |
// multiplicand is taken from oddReg (src1), multiplier in src2. |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6517 |
__ z_sgr(dst, tmp1); |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6518 |
%} |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6519 |
ins_pipe(pipe_class_dummy); |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6520 |
%} |
|
660175b829e8
8187964: [s390][ppc]: Intrinsify Math.multiplyHigh(long, long)
lucy
parents:
47216
diff
changeset
|
6521 |
|
| 42065 | 6522 |
// DIV |
6523 |
||
6524 |
// Integer DIVMOD with Register, both quotient and mod results |
|
6525 |
instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{
|
|
6526 |
match(DivModI dst1src1 src2); |
|
6527 |
effect(KILL cr); |
|
6528 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
|
52412
df84c02f4780
8213196: [ppc] [s390]: prepare code for gcc7.3.1 warning (int-in-bool-context)
lucy
parents:
51009
diff
changeset
|
6529 |
size((VM_Version::has_CompareBranch() ? 24 : 26)); |
| 42065 | 6530 |
format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
|
6531 |
ins_encode %{
|
|
6532 |
Register d1s1 = $dst1src1$$Register; |
|
6533 |
Register d2 = $dst2$$Register; |
|
6534 |
Register s2 = $src2$$Register; |
|
6535 |
||
6536 |
assert_different_registers(d1s1, s2); |
|
6537 |
||
6538 |
Label do_div, done_div; |
|
6539 |
if (VM_Version::has_CompareBranch()) {
|
|
6540 |
__ z_cij(s2, -1, Assembler::bcondNotEqual, do_div); |
|
6541 |
} else {
|
|
6542 |
__ z_chi(s2, -1); |
|
6543 |
__ z_brne(do_div); |
|
6544 |
} |
|
6545 |
__ z_lcr(d1s1, d1s1); |
|
6546 |
__ clear_reg(d2, false, false); |
|
6547 |
__ z_bru(done_div); |
|
6548 |
__ bind(do_div); |
|
6549 |
__ z_lgfr(d1s1, d1s1); |
|
6550 |
__ z_dsgfr(d2, s2); |
|
6551 |
__ bind(done_div); |
|
6552 |
%} |
|
6553 |
ins_pipe(pipe_class_dummy); |
|
6554 |
%} |
|
6555 |
||
6556 |
||
6557 |
// Register Division |
|
6558 |
instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
|
|
6559 |
match(Set dst (DivI src1 src2)); |
|
6560 |
effect(KILL tmp, KILL cr); |
|
6561 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
|
52412
df84c02f4780
8213196: [ppc] [s390]: prepare code for gcc7.3.1 warning (int-in-bool-context)
lucy
parents:
51009
diff
changeset
|
6562 |
size((VM_Version::has_CompareBranch() ? 20 : 22)); |
| 42065 | 6563 |
format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
|
6564 |
ins_encode %{
|
|
6565 |
Register a = $src1$$Register; |
|
6566 |
Register b = $src2$$Register; |
|
6567 |
Register t = $dst$$Register; |
|
6568 |
||
6569 |
assert_different_registers(t, b); |
|
6570 |
||
6571 |
Label do_div, done_div; |
|
6572 |
if (VM_Version::has_CompareBranch()) {
|
|
6573 |
__ z_cij(b, -1, Assembler::bcondNotEqual, do_div); |
|
6574 |
} else {
|
|
6575 |
__ z_chi(b, -1); |
|
6576 |
__ z_brne(do_div); |
|
6577 |
} |
|
6578 |
__ z_lcr(t, a); |
|
6579 |
__ z_bru(done_div); |
|
6580 |
__ bind(do_div); |
|
6581 |
__ z_lgfr(t, a); |
|
6582 |
__ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b); |
|
6583 |
__ bind(done_div); |
|
6584 |
%} |
|
6585 |
ins_pipe(pipe_class_dummy); |
|
6586 |
%} |
|
6587 |
||
6588 |
// Immediate Division |
|
6589 |
instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{
|
|
6590 |
match(Set dst (DivI src1 src2)); |
|
6591 |
effect(KILL tmp, KILL cr); // R0 is killed, too. |
|
6592 |
ins_cost(2 * DEFAULT_COST); |
|
6593 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
6594 |
format %{ "DIV_const $dst,$src1,$src2" %}
|
|
6595 |
ins_encode %{
|
|
6596 |
// No sign extension of Rdividend needed here. |
|
6597 |
if ($src2$$constant != -1) {
|
|
6598 |
__ z_lghi(Z_R0_scratch, $src2$$constant); |
|
6599 |
__ z_lgfr($dst$$Register, $src1$$Register); |
|
6600 |
__ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch); |
|
6601 |
} else {
|
|
6602 |
__ z_lcr($dst$$Register, $src1$$Register); |
|
6603 |
} |
|
6604 |
%} |
|
6605 |
ins_pipe(pipe_class_dummy); |
|
6606 |
%} |
|
6607 |
||
6608 |
// Long DIVMOD with Register, both quotient and mod results |
|
6609 |
instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
|
|
6610 |
match(DivModL dst1src1 src2); |
|
6611 |
effect(KILL cr); |
|
6612 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
|
52412
df84c02f4780
8213196: [ppc] [s390]: prepare code for gcc7.3.1 warning (int-in-bool-context)
lucy
parents:
51009
diff
changeset
|
6613 |
size((VM_Version::has_CompareBranch() ? 22 : 24)); |
| 42065 | 6614 |
format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
|
6615 |
ins_encode %{
|
|
6616 |
Register d1s1 = $dst1src1$$Register; |
|
6617 |
Register d2 = $dst2$$Register; |
|
6618 |
Register s2 = $src2$$Register; |
|
6619 |
||
6620 |
Label do_div, done_div; |
|
6621 |
if (VM_Version::has_CompareBranch()) {
|
|
6622 |
__ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div); |
|
6623 |
} else {
|
|
6624 |
__ z_cghi(s2, -1); |
|
6625 |
__ z_brne(do_div); |
|
6626 |
} |
|
6627 |
__ z_lcgr(d1s1, d1s1); |
|
6628 |
// indicate unused result |
|
6629 |
(void) __ clear_reg(d2, true, false); |
|
6630 |
__ z_bru(done_div); |
|
6631 |
__ bind(do_div); |
|
6632 |
__ z_dsgr(d2, s2); |
|
6633 |
__ bind(done_div); |
|
6634 |
%} |
|
6635 |
ins_pipe(pipe_class_dummy); |
|
6636 |
%} |
|
6637 |
||
6638 |
// Register Long Division |
|
6639 |
instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
|
|
6640 |
match(Set dst (DivL dst src)); |
|
6641 |
effect(KILL tmp, KILL cr); |
|
6642 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
|
52412
df84c02f4780
8213196: [ppc] [s390]: prepare code for gcc7.3.1 warning (int-in-bool-context)
lucy
parents:
51009
diff
changeset
|
6643 |
size((VM_Version::has_CompareBranch() ? 18 : 20)); |
| 42065 | 6644 |
format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %}
|
6645 |
ins_encode %{
|
|
6646 |
Register b = $src$$Register; |
|
6647 |
Register t = $dst$$Register; |
|
6648 |
||
6649 |
Label done_div; |
|
6650 |
__ z_lcgr(t, t); // Does no harm. divisor is in other register. |
|
6651 |
if (VM_Version::has_CompareBranch()) {
|
|
6652 |
__ z_cgij(b, -1, Assembler::bcondEqual, done_div); |
|
6653 |
} else {
|
|
6654 |
__ z_cghi(b, -1); |
|
6655 |
__ z_bre(done_div); |
|
6656 |
} |
|
6657 |
__ z_lcgr(t, t); // Restore sign. |
|
6658 |
__ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b); |
|
6659 |
__ bind(done_div); |
|
6660 |
%} |
|
6661 |
ins_pipe(pipe_class_dummy); |
|
6662 |
%} |
|
6663 |
||
6664 |
// Immediate Long Division |
|
6665 |
instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
|
|
6666 |
match(Set dst (DivL src1 src2)); |
|
6667 |
effect(KILL tmp, KILL cr); // R0 is killed, too. |
|
6668 |
ins_cost(2 * DEFAULT_COST); |
|
6669 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
6670 |
format %{ "DIVG_const $dst,$src1,$src2\t # long" %}
|
|
6671 |
ins_encode %{
|
|
6672 |
if ($src2$$constant != -1) {
|
|
6673 |
__ z_lghi(Z_R0_scratch, $src2$$constant); |
|
6674 |
__ lgr_if_needed($dst$$Register, $src1$$Register); |
|
6675 |
__ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch); |
|
6676 |
} else {
|
|
6677 |
__ z_lcgr($dst$$Register, $src1$$Register); |
|
6678 |
} |
|
6679 |
%} |
|
6680 |
ins_pipe(pipe_class_dummy); |
|
6681 |
%} |
|
6682 |
||
6683 |
// REM |
|
6684 |
||
6685 |
// Integer Remainder |
|
6686 |
// Register Remainder |
|
6687 |
instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{
|
|
6688 |
match(Set dst (ModI src1 src2)); |
|
6689 |
effect(KILL tmp, KILL cr); |
|
6690 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
6691 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
6692 |
format %{ "MOD_checked $dst,$src1,$src2" %}
|
|
6693 |
ins_encode %{
|
|
6694 |
Register a = $src1$$Register; |
|
6695 |
Register b = $src2$$Register; |
|
6696 |
Register t = $dst$$Register; |
|
6697 |
assert_different_registers(t->successor(), b); |
|
6698 |
||
6699 |
Label do_div, done_div; |
|
6700 |
||
6701 |
if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) {
|
|
6702 |
(void) __ clear_reg(t, true, false); // Does no harm. Operands are in other regs. |
|
6703 |
if (VM_Version::has_CompareBranch()) {
|
|
6704 |
__ z_cij(b, -1, Assembler::bcondEqual, done_div); |
|
6705 |
} else {
|
|
6706 |
__ z_chi(b, -1); |
|
6707 |
__ z_bre(done_div); |
|
6708 |
} |
|
6709 |
__ z_lgfr(t->successor(), a); |
|
6710 |
__ z_dsgfr(t/* t is even part of a register pair. */, b); |
|
6711 |
} else {
|
|
6712 |
if (VM_Version::has_CompareBranch()) {
|
|
6713 |
__ z_cij(b, -1, Assembler::bcondNotEqual, do_div); |
|
6714 |
} else {
|
|
6715 |
__ z_chi(b, -1); |
|
6716 |
__ z_brne(do_div); |
|
6717 |
} |
|
6718 |
__ clear_reg(t, true, false); |
|
6719 |
__ z_bru(done_div); |
|
6720 |
__ bind(do_div); |
|
6721 |
__ z_lgfr(t->successor(), a); |
|
6722 |
__ z_dsgfr(t/* t is even part of a register pair. */, b); |
|
6723 |
} |
|
6724 |
__ bind(done_div); |
|
6725 |
%} |
|
6726 |
ins_pipe(pipe_class_dummy); |
|
6727 |
%} |
|
6728 |
||
6729 |
// Immediate Remainder |
|
6730 |
instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
|
|
6731 |
match(Set dst (ModI src1 src2)); |
|
6732 |
effect(KILL tmp, KILL cr); // R0 is killed, too. |
|
6733 |
ins_cost(3 * DEFAULT_COST); |
|
6734 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
6735 |
format %{ "MOD_const $dst,src1,$src2" %}
|
|
6736 |
ins_encode %{
|
|
6737 |
assert_different_registers($dst$$Register, $src1$$Register); |
|
6738 |
assert_different_registers($dst$$Register->successor(), $src1$$Register); |
|
6739 |
int divisor = $src2$$constant; |
|
6740 |
||
6741 |
if (divisor != -1) {
|
|
6742 |
__ z_lghi(Z_R0_scratch, divisor); |
|
6743 |
__ z_lgfr($dst$$Register->successor(), $src1$$Register); |
|
6744 |
__ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp. |
|
6745 |
} else {
|
|
6746 |
__ clear_reg($dst$$Register, true, false); |
|
6747 |
} |
|
6748 |
%} |
|
6749 |
ins_pipe(pipe_class_dummy); |
|
6750 |
%} |
|
6751 |
||
6752 |
// Register Long Remainder |
|
6753 |
instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
|
|
6754 |
match(Set dst (ModL src1 src2)); |
|
6755 |
effect(KILL src1, KILL cr); // R0 is killed, too. |
|
6756 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
6757 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
6758 |
format %{ "MODG_checked $dst,$src1,$src2" %}
|
|
6759 |
ins_encode %{
|
|
6760 |
Register a = $src1$$Register; |
|
6761 |
Register b = $src2$$Register; |
|
6762 |
Register t = $dst$$Register; |
|
6763 |
assert(t->successor() == a, "(t,a) is an even-odd pair" ); |
|
6764 |
||
6765 |
Label do_div, done_div; |
|
6766 |
if (t->encoding() != b->encoding()) {
|
|
6767 |
(void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor. |
|
6768 |
if (VM_Version::has_CompareBranch()) {
|
|
6769 |
__ z_cgij(b, -1, Assembler::bcondEqual, done_div); |
|
6770 |
} else {
|
|
6771 |
__ z_cghi(b, -1); |
|
6772 |
__ z_bre(done_div); |
|
6773 |
} |
|
6774 |
__ z_dsgr(t, b); |
|
6775 |
} else {
|
|
6776 |
if (VM_Version::has_CompareBranch()) {
|
|
6777 |
__ z_cgij(b, -1, Assembler::bcondNotEqual, do_div); |
|
6778 |
} else {
|
|
6779 |
__ z_cghi(b, -1); |
|
6780 |
__ z_brne(do_div); |
|
6781 |
} |
|
6782 |
__ clear_reg(t, true, false); |
|
6783 |
__ z_bru(done_div); |
|
6784 |
__ bind(do_div); |
|
6785 |
__ z_dsgr(t, b); |
|
6786 |
} |
|
6787 |
__ bind(done_div); |
|
6788 |
%} |
|
6789 |
ins_pipe(pipe_class_dummy); |
|
6790 |
%} |
|
6791 |
||
6792 |
// Register Long Remainder |
|
6793 |
instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
|
|
6794 |
match(Set dst (ModL src1 src2)); |
|
6795 |
effect(KILL tmp, KILL cr); // R0 is killed, too. |
|
6796 |
ins_cost(3 * DEFAULT_COST); |
|
6797 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
6798 |
format %{ "MODG_const $dst,src1,$src2\t # long" %}
|
|
6799 |
ins_encode %{
|
|
6800 |
int divisor = $src2$$constant; |
|
6801 |
if (divisor != -1) {
|
|
6802 |
__ z_lghi(Z_R0_scratch, divisor); |
|
6803 |
__ z_lgr($dst$$Register->successor(), $src1$$Register); |
|
6804 |
__ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp. |
|
6805 |
} else {
|
|
6806 |
__ clear_reg($dst$$Register, true, false); |
|
6807 |
} |
|
6808 |
%} |
|
6809 |
ins_pipe(pipe_class_dummy); |
|
6810 |
%} |
|
6811 |
||
6812 |
// SHIFT |
|
6813 |
||
6814 |
// Shift left logical |
|
6815 |
||
6816 |
// Register Shift Left variable |
|
6817 |
instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
|
|
6818 |
match(Set dst (LShiftI src nbits)); |
|
6819 |
effect(KILL cr); // R1 is killed, too. |
|
6820 |
ins_cost(3 * DEFAULT_COST); |
|
6821 |
size(14); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
6822 |
format %{ "SLL $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %}
|
| 42065 | 6823 |
ins_encode %{
|
6824 |
__ z_lgr(Z_R1_scratch, $nbits$$Register); |
|
6825 |
__ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); |
|
6826 |
__ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch); |
|
6827 |
%} |
|
6828 |
ins_pipe(pipe_class_dummy); |
|
6829 |
%} |
|
6830 |
||
6831 |
// Register Shift Left Immediate |
|
6832 |
// Constant shift count is masked in ideal graph already. |
|
6833 |
instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
|
|
6834 |
match(Set dst (LShiftI src nbits)); |
|
6835 |
size(6); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
6836 |
format %{ "SLL $dst,$src,$nbits\t # use RISC-like SLLG also for int" %}
|
| 42065 | 6837 |
ins_encode %{
|
6838 |
int Nbit = $nbits$$constant; |
|
| 46277 | 6839 |
assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); |
| 42065 | 6840 |
__ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); |
6841 |
%} |
|
6842 |
ins_pipe(pipe_class_dummy); |
|
6843 |
%} |
|
6844 |
||
6845 |
// Register Shift Left Immediate by 1bit |
|
6846 |
instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
|
|
6847 |
match(Set dst (LShiftI src nbits)); |
|
6848 |
predicate(PreferLAoverADD); |
|
6849 |
ins_cost(DEFAULT_COST_LOW); |
|
6850 |
size(4); |
|
6851 |
format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %}
|
|
6852 |
ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
|
|
6853 |
ins_pipe(pipe_class_dummy); |
|
6854 |
%} |
|
6855 |
||
6856 |
// Register Shift Left Long |
|
6857 |
instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
|
|
6858 |
match(Set dst (LShiftL src1 nbits)); |
|
6859 |
size(6); |
|
6860 |
format %{ "SLLG $dst,$src1,[$nbits]" %}
|
|
6861 |
opcode(SLLG_ZOPC); |
|
6862 |
ins_encode(z_rsyform_reg_reg(dst, src1, nbits)); |
|
6863 |
ins_pipe(pipe_class_dummy); |
|
6864 |
%} |
|
6865 |
||
6866 |
// Register Shift Left Long Immediate |
|
6867 |
instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{
|
|
6868 |
match(Set dst (LShiftL src1 nbits)); |
|
6869 |
size(6); |
|
6870 |
format %{ "SLLG $dst,$src1,$nbits" %}
|
|
6871 |
opcode(SLLG_ZOPC); |
|
6872 |
ins_encode(z_rsyform_const(dst, src1, nbits)); |
|
6873 |
ins_pipe(pipe_class_dummy); |
|
6874 |
%} |
|
6875 |
||
6876 |
// Register Shift Left Long Immediate by 1bit |
|
6877 |
instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{
|
|
6878 |
match(Set dst (LShiftL src1 nbits)); |
|
6879 |
predicate(PreferLAoverADD); |
|
6880 |
ins_cost(DEFAULT_COST_LOW); |
|
6881 |
size(4); |
|
6882 |
format %{ "LA $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %}
|
|
6883 |
ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %}
|
|
6884 |
ins_pipe(pipe_class_dummy); |
|
6885 |
%} |
|
6886 |
||
6887 |
// Shift right arithmetic |
|
6888 |
||
6889 |
// Register Arithmetic Shift Right |
|
6890 |
instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
|
|
6891 |
match(Set dst (RShiftI dst src)); |
|
6892 |
effect(KILL cr); // R1 is killed, too. |
|
6893 |
ins_cost(3 * DEFAULT_COST); |
|
6894 |
size(12); |
|
6895 |
format %{ "SRA $dst,[$src] & 31" %}
|
|
6896 |
ins_encode %{
|
|
6897 |
__ z_lgr(Z_R1_scratch, $src$$Register); |
|
6898 |
__ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); |
|
6899 |
__ z_sra($dst$$Register, 0, Z_R1_scratch); |
|
6900 |
%} |
|
6901 |
ins_pipe(pipe_class_dummy); |
|
6902 |
%} |
|
6903 |
||
6904 |
// Register Arithmetic Shift Right Immediate |
|
6905 |
// Constant shift count is masked in ideal graph already. |
|
6906 |
instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
|
|
6907 |
match(Set dst (RShiftI dst src)); |
|
6908 |
effect(KILL cr); |
|
6909 |
size(4); |
|
6910 |
format %{ "SRA $dst,$src" %}
|
|
6911 |
ins_encode %{
|
|
6912 |
int Nbit = $src$$constant; |
|
| 46277 | 6913 |
assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); |
| 42065 | 6914 |
__ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); |
6915 |
%} |
|
6916 |
ins_pipe(pipe_class_dummy); |
|
6917 |
%} |
|
6918 |
||
6919 |
// Register Arithmetic Shift Right Long |
|
6920 |
instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
|
|
6921 |
match(Set dst (RShiftL src1 src2)); |
|
6922 |
effect(KILL cr); |
|
6923 |
size(6); |
|
6924 |
format %{ "SRAG $dst,$src1,[$src2]" %}
|
|
6925 |
opcode(SRAG_ZOPC); |
|
6926 |
ins_encode(z_rsyform_reg_reg(dst, src1, src2)); |
|
6927 |
ins_pipe(pipe_class_dummy); |
|
6928 |
%} |
|
6929 |
||
6930 |
// Register Arithmetic Shift Right Long Immediate |
|
6931 |
instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
|
|
6932 |
match(Set dst (RShiftL src1 src2)); |
|
6933 |
effect(KILL cr); |
|
6934 |
size(6); |
|
6935 |
format %{ "SRAG $dst,$src1,$src2" %}
|
|
6936 |
opcode(SRAG_ZOPC); |
|
6937 |
ins_encode(z_rsyform_const(dst, src1, src2)); |
|
6938 |
ins_pipe(pipe_class_dummy); |
|
6939 |
%} |
|
6940 |
||
6941 |
// Shift right logical |
|
6942 |
||
6943 |
// Register Shift Right |
|
6944 |
instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
|
|
6945 |
match(Set dst (URShiftI dst src)); |
|
6946 |
effect(KILL cr); // R1 is killed, too. |
|
6947 |
ins_cost(3 * DEFAULT_COST); |
|
6948 |
size(12); |
|
6949 |
format %{ "SRL $dst,[$src] & 31" %}
|
|
6950 |
ins_encode %{
|
|
6951 |
__ z_lgr(Z_R1_scratch, $src$$Register); |
|
6952 |
__ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); |
|
6953 |
__ z_srl($dst$$Register, 0, Z_R1_scratch); |
|
6954 |
%} |
|
6955 |
ins_pipe(pipe_class_dummy); |
|
6956 |
%} |
|
6957 |
||
6958 |
// Register Shift Right Immediate |
|
6959 |
// Constant shift count is masked in ideal graph already. |
|
6960 |
instruct srlI_reg_imm(iRegI dst, immI src) %{
|
|
6961 |
match(Set dst (URShiftI dst src)); |
|
6962 |
size(4); |
|
6963 |
format %{ "SRL $dst,$src" %}
|
|
6964 |
ins_encode %{
|
|
6965 |
int Nbit = $src$$constant; |
|
| 46277 | 6966 |
assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); |
| 42065 | 6967 |
__ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); |
6968 |
%} |
|
6969 |
ins_pipe(pipe_class_dummy); |
|
6970 |
%} |
|
6971 |
||
6972 |
// Register Shift Right Long |
|
6973 |
instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
|
|
6974 |
match(Set dst (URShiftL src1 src2)); |
|
6975 |
size(6); |
|
6976 |
format %{ "SRLG $dst,$src1,[$src2]" %}
|
|
6977 |
opcode(SRLG_ZOPC); |
|
6978 |
ins_encode(z_rsyform_reg_reg(dst, src1, src2)); |
|
6979 |
ins_pipe(pipe_class_dummy); |
|
6980 |
%} |
|
6981 |
||
6982 |
// Register Shift Right Long Immediate |
|
6983 |
instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
|
|
6984 |
match(Set dst (URShiftL src1 src2)); |
|
6985 |
size(6); |
|
6986 |
format %{ "SRLG $dst,$src1,$src2" %}
|
|
6987 |
opcode(SRLG_ZOPC); |
|
6988 |
ins_encode(z_rsyform_const(dst, src1, src2)); |
|
6989 |
ins_pipe(pipe_class_dummy); |
|
6990 |
%} |
|
6991 |
||
6992 |
// Register Shift Right Immediate with a CastP2X |
|
6993 |
instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{
|
|
6994 |
match(Set dst (URShiftL (CastP2X src1) src2)); |
|
6995 |
size(6); |
|
6996 |
format %{ "SRLG $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %}
|
|
6997 |
opcode(SRLG_ZOPC); |
|
6998 |
ins_encode(z_rsyform_const(dst, src1, src2)); |
|
6999 |
ins_pipe(pipe_class_dummy); |
|
7000 |
%} |
|
7001 |
||
7002 |
//----------Rotate Instructions------------------------------------------------ |
|
7003 |
||
7004 |
// Rotate left 32bit. |
|
7005 |
instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{
|
|
7006 |
match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); |
|
7007 |
predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
|
7008 |
size(6); |
|
7009 |
format %{ "RLL $dst,$src,$lshift\t # ROTL32" %}
|
|
7010 |
opcode(RLL_ZOPC); |
|
7011 |
ins_encode(z_rsyform_const(dst, src, lshift)); |
|
7012 |
ins_pipe(pipe_class_dummy); |
|
7013 |
%} |
|
7014 |
||
7015 |
// Rotate left 64bit. |
|
7016 |
instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{
|
|
7017 |
match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift))); |
|
7018 |
predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); |
|
7019 |
size(6); |
|
7020 |
format %{ "RLLG $dst,$src,$lshift\t # ROTL64" %}
|
|
7021 |
opcode(RLLG_ZOPC); |
|
7022 |
ins_encode(z_rsyform_const(dst, src, lshift)); |
|
7023 |
ins_pipe(pipe_class_dummy); |
|
7024 |
%} |
|
7025 |
||
7026 |
// Rotate right 32bit. |
|
7027 |
instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{
|
|
7028 |
match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); |
|
7029 |
predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
|
7030 |
// TODO: s390 port size(FIXED_SIZE); |
|
7031 |
format %{ "RLL $dst,$src,$rshift\t # ROTR32" %}
|
|
7032 |
opcode(RLL_ZOPC); |
|
7033 |
ins_encode(z_rsyform_const(dst, src, rshift)); |
|
7034 |
ins_pipe(pipe_class_dummy); |
|
7035 |
%} |
|
7036 |
||
7037 |
// Rotate right 64bit. |
|
7038 |
instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{
|
|
7039 |
match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift))); |
|
7040 |
predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); |
|
7041 |
// TODO: s390 port size(FIXED_SIZE); |
|
7042 |
format %{ "RLLG $dst,$src,$rshift\t # ROTR64" %}
|
|
7043 |
opcode(RLLG_ZOPC); |
|
7044 |
ins_encode(z_rsyform_const(dst, src, rshift)); |
|
7045 |
ins_pipe(pipe_class_dummy); |
|
7046 |
%} |
|
7047 |
||
7048 |
||
7049 |
//----------Overflow Math Instructions----------------------------------------- |
|
7050 |
||
7051 |
instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
|
|
7052 |
match(Set cr (OverflowAddI op1 op2)); |
|
7053 |
effect(DEF cr, USE op1, USE op2); |
|
7054 |
// TODO: s390 port size(FIXED_SIZE); |
|
7055 |
format %{ "AR $op1,$op2\t # overflow check int" %}
|
|
7056 |
ins_encode %{
|
|
7057 |
__ z_lr(Z_R0_scratch, $op1$$Register); |
|
7058 |
__ z_ar(Z_R0_scratch, $op2$$Register); |
|
7059 |
%} |
|
7060 |
ins_pipe(pipe_class_dummy); |
|
7061 |
%} |
|
7062 |
||
7063 |
instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
|
|
7064 |
match(Set cr (OverflowAddI op1 op2)); |
|
7065 |
effect(DEF cr, USE op1, USE op2); |
|
7066 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
7067 |
format %{ "AR $op1,$op2\t # overflow check int" %}
|
|
7068 |
ins_encode %{
|
|
7069 |
__ load_const_optimized(Z_R0_scratch, $op2$$constant); |
|
7070 |
__ z_ar(Z_R0_scratch, $op1$$Register); |
|
7071 |
%} |
|
7072 |
ins_pipe(pipe_class_dummy); |
|
7073 |
%} |
|
7074 |
||
7075 |
instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
|
|
7076 |
match(Set cr (OverflowAddL op1 op2)); |
|
7077 |
effect(DEF cr, USE op1, USE op2); |
|
7078 |
// TODO: s390 port size(FIXED_SIZE); |
|
7079 |
format %{ "AGR $op1,$op2\t # overflow check long" %}
|
|
7080 |
ins_encode %{
|
|
7081 |
__ z_lgr(Z_R0_scratch, $op1$$Register); |
|
7082 |
__ z_agr(Z_R0_scratch, $op2$$Register); |
|
7083 |
%} |
|
7084 |
ins_pipe(pipe_class_dummy); |
|
7085 |
%} |
|
7086 |
||
7087 |
instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
|
|
7088 |
match(Set cr (OverflowAddL op1 op2)); |
|
7089 |
effect(DEF cr, USE op1, USE op2); |
|
7090 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
7091 |
format %{ "AGR $op1,$op2\t # overflow check long" %}
|
|
7092 |
ins_encode %{
|
|
7093 |
__ load_const_optimized(Z_R0_scratch, $op2$$constant); |
|
7094 |
__ z_agr(Z_R0_scratch, $op1$$Register); |
|
7095 |
%} |
|
7096 |
ins_pipe(pipe_class_dummy); |
|
7097 |
%} |
|
7098 |
||
7099 |
instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
|
|
7100 |
match(Set cr (OverflowSubI op1 op2)); |
|
7101 |
effect(DEF cr, USE op1, USE op2); |
|
7102 |
// TODO: s390 port size(FIXED_SIZE); |
|
7103 |
format %{ "SR $op1,$op2\t # overflow check int" %}
|
|
7104 |
ins_encode %{
|
|
7105 |
__ z_lr(Z_R0_scratch, $op1$$Register); |
|
7106 |
__ z_sr(Z_R0_scratch, $op2$$Register); |
|
7107 |
%} |
|
7108 |
ins_pipe(pipe_class_dummy); |
|
7109 |
%} |
|
7110 |
||
7111 |
instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
|
|
7112 |
match(Set cr (OverflowSubI op1 op2)); |
|
7113 |
effect(DEF cr, USE op1, USE op2); |
|
7114 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
7115 |
format %{ "SR $op1,$op2\t # overflow check int" %}
|
|
7116 |
ins_encode %{
|
|
7117 |
__ load_const_optimized(Z_R1_scratch, $op2$$constant); |
|
7118 |
__ z_lr(Z_R0_scratch, $op1$$Register); |
|
7119 |
__ z_sr(Z_R0_scratch, Z_R1_scratch); |
|
7120 |
%} |
|
7121 |
ins_pipe(pipe_class_dummy); |
|
7122 |
%} |
|
7123 |
||
7124 |
instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
|
|
7125 |
match(Set cr (OverflowSubL op1 op2)); |
|
7126 |
effect(DEF cr, USE op1, USE op2); |
|
7127 |
// TODO: s390 port size(FIXED_SIZE); |
|
7128 |
format %{ "SGR $op1,$op2\t # overflow check long" %}
|
|
7129 |
ins_encode %{
|
|
7130 |
__ z_lgr(Z_R0_scratch, $op1$$Register); |
|
7131 |
__ z_sgr(Z_R0_scratch, $op2$$Register); |
|
7132 |
%} |
|
7133 |
ins_pipe(pipe_class_dummy); |
|
7134 |
%} |
|
7135 |
||
7136 |
instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
|
|
7137 |
match(Set cr (OverflowSubL op1 op2)); |
|
7138 |
effect(DEF cr, USE op1, USE op2); |
|
7139 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
7140 |
format %{ "SGR $op1,$op2\t # overflow check long" %}
|
|
7141 |
ins_encode %{
|
|
7142 |
__ load_const_optimized(Z_R1_scratch, $op2$$constant); |
|
7143 |
__ z_lgr(Z_R0_scratch, $op1$$Register); |
|
7144 |
__ z_sgr(Z_R0_scratch, Z_R1_scratch); |
|
7145 |
%} |
|
7146 |
ins_pipe(pipe_class_dummy); |
|
7147 |
%} |
|
7148 |
||
7149 |
instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
|
|
7150 |
match(Set cr (OverflowSubI zero op2)); |
|
7151 |
effect(DEF cr, USE op2); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
7152 |
format %{ "NEG $op2\t # overflow check int" %}
|
| 42065 | 7153 |
ins_encode %{
|
7154 |
__ clear_reg(Z_R0_scratch, false, false); |
|
7155 |
__ z_sr(Z_R0_scratch, $op2$$Register); |
|
7156 |
%} |
|
7157 |
ins_pipe(pipe_class_dummy); |
|
7158 |
%} |
|
7159 |
||
7160 |
instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
|
|
7161 |
match(Set cr (OverflowSubL zero op2)); |
|
7162 |
effect(DEF cr, USE op2); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
7163 |
format %{ "NEGG $op2\t # overflow check long" %}
|
| 42065 | 7164 |
ins_encode %{
|
7165 |
__ clear_reg(Z_R0_scratch, true, false); |
|
7166 |
__ z_sgr(Z_R0_scratch, $op2$$Register); |
|
7167 |
%} |
|
7168 |
ins_pipe(pipe_class_dummy); |
|
7169 |
%} |
|
7170 |
||
7171 |
// No intrinsics for multiplication, since there is no easy way |
|
7172 |
// to check for overflow. |
|
7173 |
||
7174 |
||
7175 |
//----------Floating Point Arithmetic Instructions----------------------------- |
|
7176 |
||
7177 |
// ADD |
|
7178 |
||
7179 |
// Add float single precision |
|
7180 |
instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{
|
|
7181 |
match(Set dst (AddF dst src)); |
|
7182 |
effect(KILL cr); |
|
7183 |
ins_cost(ALU_REG_COST); |
|
7184 |
size(4); |
|
7185 |
format %{ "AEBR $dst,$src" %}
|
|
7186 |
opcode(AEBR_ZOPC); |
|
7187 |
ins_encode(z_rreform(dst, src)); |
|
7188 |
ins_pipe(pipe_class_dummy); |
|
7189 |
%} |
|
7190 |
||
7191 |
instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
|
|
7192 |
match(Set dst (AddF dst (LoadF src))); |
|
7193 |
effect(KILL cr); |
|
7194 |
ins_cost(ALU_MEMORY_COST); |
|
7195 |
size(6); |
|
7196 |
format %{ "AEB $dst,$src\t # floatMemory" %}
|
|
7197 |
opcode(AEB_ZOPC); |
|
7198 |
ins_encode(z_form_rt_memFP(dst, src)); |
|
7199 |
ins_pipe(pipe_class_dummy); |
|
7200 |
%} |
|
7201 |
||
7202 |
// Add float double precision |
|
7203 |
instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{
|
|
7204 |
match(Set dst (AddD dst src)); |
|
7205 |
effect(KILL cr); |
|
7206 |
ins_cost(ALU_REG_COST); |
|
7207 |
size(4); |
|
7208 |
format %{ "ADBR $dst,$src" %}
|
|
7209 |
opcode(ADBR_ZOPC); |
|
7210 |
ins_encode(z_rreform(dst, src)); |
|
7211 |
ins_pipe(pipe_class_dummy); |
|
7212 |
%} |
|
7213 |
||
7214 |
instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
|
|
7215 |
match(Set dst (AddD dst (LoadD src))); |
|
7216 |
effect(KILL cr); |
|
7217 |
ins_cost(ALU_MEMORY_COST); |
|
7218 |
size(6); |
|
7219 |
format %{ "ADB $dst,$src\t # doubleMemory" %}
|
|
7220 |
opcode(ADB_ZOPC); |
|
7221 |
ins_encode(z_form_rt_memFP(dst, src)); |
|
7222 |
ins_pipe(pipe_class_dummy); |
|
7223 |
%} |
|
7224 |
||
7225 |
// SUB |
|
7226 |
||
7227 |
// Sub float single precision |
|
7228 |
instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{
|
|
7229 |
match(Set dst (SubF dst src)); |
|
7230 |
effect(KILL cr); |
|
7231 |
ins_cost(ALU_REG_COST); |
|
7232 |
size(4); |
|
7233 |
format %{ "SEBR $dst,$src" %}
|
|
7234 |
opcode(SEBR_ZOPC); |
|
7235 |
ins_encode(z_rreform(dst, src)); |
|
7236 |
ins_pipe(pipe_class_dummy); |
|
7237 |
%} |
|
7238 |
||
7239 |
instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
|
|
7240 |
match(Set dst (SubF dst (LoadF src))); |
|
7241 |
effect(KILL cr); |
|
7242 |
ins_cost(ALU_MEMORY_COST); |
|
7243 |
size(6); |
|
7244 |
format %{ "SEB $dst,$src\t # floatMemory" %}
|
|
7245 |
opcode(SEB_ZOPC); |
|
7246 |
ins_encode(z_form_rt_memFP(dst, src)); |
|
7247 |
ins_pipe(pipe_class_dummy); |
|
7248 |
%} |
|
7249 |
||
7250 |
// Sub float double precision |
|
7251 |
instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{
|
|
7252 |
match(Set dst (SubD dst src)); |
|
7253 |
effect(KILL cr); |
|
7254 |
ins_cost(ALU_REG_COST); |
|
7255 |
size(4); |
|
7256 |
format %{ "SDBR $dst,$src" %}
|
|
7257 |
opcode(SDBR_ZOPC); |
|
7258 |
ins_encode(z_rreform(dst, src)); |
|
7259 |
ins_pipe(pipe_class_dummy); |
|
7260 |
%} |
|
7261 |
||
7262 |
instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
|
|
7263 |
match(Set dst (SubD dst (LoadD src))); |
|
7264 |
effect(KILL cr); |
|
7265 |
ins_cost(ALU_MEMORY_COST); |
|
7266 |
size(6); |
|
7267 |
format %{ "SDB $dst,$src\t # doubleMemory" %}
|
|
7268 |
opcode(SDB_ZOPC); |
|
7269 |
ins_encode(z_form_rt_memFP(dst, src)); |
|
7270 |
ins_pipe(pipe_class_dummy); |
|
7271 |
%} |
|
7272 |
||
7273 |
// MUL |
|
7274 |
||
7275 |
// Mul float single precision |
|
7276 |
instruct mulF_reg_reg(regF dst, regF src) %{
|
|
7277 |
match(Set dst (MulF dst src)); |
|
7278 |
// CC unchanged by MUL. |
|
7279 |
ins_cost(ALU_REG_COST); |
|
7280 |
size(4); |
|
7281 |
format %{ "MEEBR $dst,$src" %}
|
|
7282 |
opcode(MEEBR_ZOPC); |
|
7283 |
ins_encode(z_rreform(dst, src)); |
|
7284 |
ins_pipe(pipe_class_dummy); |
|
7285 |
%} |
|
7286 |
||
7287 |
instruct mulF_reg_mem(regF dst, memoryRX src)%{
|
|
7288 |
match(Set dst (MulF dst (LoadF src))); |
|
7289 |
// CC unchanged by MUL. |
|
7290 |
ins_cost(ALU_MEMORY_COST); |
|
7291 |
size(6); |
|
7292 |
format %{ "MEEB $dst,$src\t # floatMemory" %}
|
|
7293 |
opcode(MEEB_ZOPC); |
|
7294 |
ins_encode(z_form_rt_memFP(dst, src)); |
|
7295 |
ins_pipe(pipe_class_dummy); |
|
7296 |
%} |
|
7297 |
||
7298 |
// Mul float double precision |
|
7299 |
instruct mulD_reg_reg(regD dst, regD src) %{
|
|
7300 |
match(Set dst (MulD dst src)); |
|
7301 |
// CC unchanged by MUL. |
|
7302 |
ins_cost(ALU_REG_COST); |
|
7303 |
size(4); |
|
7304 |
format %{ "MDBR $dst,$src" %}
|
|
7305 |
opcode(MDBR_ZOPC); |
|
7306 |
ins_encode(z_rreform(dst, src)); |
|
7307 |
ins_pipe(pipe_class_dummy); |
|
7308 |
%} |
|
7309 |
||
7310 |
instruct mulD_reg_mem(regD dst, memoryRX src)%{
|
|
7311 |
match(Set dst (MulD dst (LoadD src))); |
|
7312 |
// CC unchanged by MUL. |
|
7313 |
ins_cost(ALU_MEMORY_COST); |
|
7314 |
size(6); |
|
7315 |
format %{ "MDB $dst,$src\t # doubleMemory" %}
|
|
7316 |
opcode(MDB_ZOPC); |
|
7317 |
ins_encode(z_form_rt_memFP(dst, src)); |
|
7318 |
ins_pipe(pipe_class_dummy); |
|
7319 |
%} |
|
7320 |
||
|
42897
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7321 |
// Multiply-Accumulate |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7322 |
// src1 * src2 + dst |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7323 |
instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7324 |
match(Set dst (FmaF dst (Binary src1 src2))); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7325 |
// CC unchanged by MUL-ADD. |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7326 |
ins_cost(ALU_REG_COST); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7327 |
size(4); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7328 |
format %{ "MAEBR $dst, $src1, $src2" %}
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7329 |
ins_encode %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7330 |
__ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7331 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7332 |
ins_pipe(pipe_class_dummy); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7333 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7334 |
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7335 |
// src1 * src2 + dst |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7336 |
instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7337 |
match(Set dst (FmaD dst (Binary src1 src2))); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7338 |
// CC unchanged by MUL-ADD. |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7339 |
ins_cost(ALU_REG_COST); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7340 |
size(4); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7341 |
format %{ "MADBR $dst, $src1, $src2" %}
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7342 |
ins_encode %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7343 |
__ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7344 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7345 |
ins_pipe(pipe_class_dummy); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7346 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7347 |
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7348 |
// src1 * src2 - dst |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7349 |
instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7350 |
match(Set dst (FmaF (NegF dst) (Binary src1 src2))); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7351 |
// CC unchanged by MUL-SUB. |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7352 |
ins_cost(ALU_REG_COST); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7353 |
size(4); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7354 |
format %{ "MSEBR $dst, $src1, $src2" %}
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7355 |
ins_encode %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7356 |
__ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7357 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7358 |
ins_pipe(pipe_class_dummy); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7359 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7360 |
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7361 |
// src1 * src2 - dst |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7362 |
instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7363 |
match(Set dst (FmaD (NegD dst) (Binary src1 src2))); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7364 |
// CC unchanged by MUL-SUB. |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7365 |
ins_cost(ALU_REG_COST); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7366 |
size(4); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7367 |
format %{ "MSDBR $dst, $src1, $src2" %}
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7368 |
ins_encode %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7369 |
__ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7370 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7371 |
ins_pipe(pipe_class_dummy); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7372 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7373 |
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7374 |
// src1 * src2 + dst |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7375 |
instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7376 |
match(Set dst (FmaF dst (Binary src1 (LoadF src2)))); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7377 |
// CC unchanged by MUL-ADD. |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7378 |
ins_cost(ALU_MEMORY_COST); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7379 |
size(6); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7380 |
format %{ "MAEB $dst, $src1, $src2" %}
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7381 |
ins_encode %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7382 |
__ z_maeb($dst$$FloatRegister, $src1$$FloatRegister, |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7383 |
Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7384 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7385 |
ins_pipe(pipe_class_dummy); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7386 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7387 |
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7388 |
// src1 * src2 + dst |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7389 |
instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7390 |
match(Set dst (FmaD dst (Binary src1 (LoadD src2)))); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7391 |
// CC unchanged by MUL-ADD. |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7392 |
ins_cost(ALU_MEMORY_COST); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7393 |
size(6); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7394 |
format %{ "MADB $dst, $src1, $src2" %}
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7395 |
ins_encode %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7396 |
__ z_madb($dst$$FloatRegister, $src1$$FloatRegister, |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7397 |
Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7398 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7399 |
ins_pipe(pipe_class_dummy); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7400 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7401 |
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7402 |
// src1 * src2 - dst |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7403 |
instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7404 |
match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2)))); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7405 |
// CC unchanged by MUL-SUB. |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7406 |
ins_cost(ALU_MEMORY_COST); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7407 |
size(6); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7408 |
format %{ "MSEB $dst, $src1, $src2" %}
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7409 |
ins_encode %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7410 |
__ z_mseb($dst$$FloatRegister, $src1$$FloatRegister, |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7411 |
Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7412 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7413 |
ins_pipe(pipe_class_dummy); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7414 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7415 |
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7416 |
// src1 * src2 - dst |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7417 |
instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7418 |
match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2)))); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7419 |
// CC unchanged by MUL-SUB. |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7420 |
ins_cost(ALU_MEMORY_COST); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7421 |
size(6); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7422 |
format %{ "MSDB $dst, $src1, $src2" %}
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7423 |
ins_encode %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7424 |
__ z_msdb($dst$$FloatRegister, $src1$$FloatRegister, |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7425 |
Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7426 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7427 |
ins_pipe(pipe_class_dummy); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7428 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7429 |
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7430 |
// src1 * src2 + dst |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7431 |
instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7432 |
match(Set dst (FmaF dst (Binary (LoadF src1) src2))); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7433 |
// CC unchanged by MUL-ADD. |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7434 |
ins_cost(ALU_MEMORY_COST); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7435 |
size(6); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7436 |
format %{ "MAEB $dst, $src1, $src2" %}
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7437 |
ins_encode %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7438 |
__ z_maeb($dst$$FloatRegister, $src2$$FloatRegister, |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7439 |
Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7440 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7441 |
ins_pipe(pipe_class_dummy); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7442 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7443 |
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7444 |
// src1 * src2 + dst |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7445 |
instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7446 |
match(Set dst (FmaD dst (Binary (LoadD src1) src2))); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7447 |
// CC unchanged by MUL-ADD. |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7448 |
ins_cost(ALU_MEMORY_COST); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7449 |
size(6); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7450 |
format %{ "MADB $dst, $src1, $src2" %}
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7451 |
ins_encode %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7452 |
__ z_madb($dst$$FloatRegister, $src2$$FloatRegister, |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7453 |
Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7454 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7455 |
ins_pipe(pipe_class_dummy); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7456 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7457 |
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7458 |
// src1 * src2 - dst |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7459 |
instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7460 |
match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2))); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7461 |
// CC unchanged by MUL-SUB. |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7462 |
ins_cost(ALU_MEMORY_COST); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7463 |
size(6); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7464 |
format %{ "MSEB $dst, $src1, $src2" %}
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7465 |
ins_encode %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7466 |
__ z_mseb($dst$$FloatRegister, $src2$$FloatRegister, |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7467 |
Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7468 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7469 |
ins_pipe(pipe_class_dummy); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7470 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7471 |
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7472 |
// src1 * src2 - dst |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7473 |
instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7474 |
match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2))); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7475 |
// CC unchanged by MUL-SUB. |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7476 |
ins_cost(ALU_MEMORY_COST); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7477 |
size(6); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7478 |
format %{ "MSDB $dst, $src1, $src2" %}
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7479 |
ins_encode %{
|
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7480 |
__ z_msdb($dst$$FloatRegister, $src2$$FloatRegister, |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7481 |
Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7482 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7483 |
ins_pipe(pipe_class_dummy); |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7484 |
%} |
|
57e7b1c75d17
8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
mdoerr
parents:
42556
diff
changeset
|
7485 |
|
| 42065 | 7486 |
// DIV |
7487 |
||
7488 |
// Div float single precision |
|
7489 |
instruct divF_reg_reg(regF dst, regF src) %{
|
|
7490 |
match(Set dst (DivF dst src)); |
|
7491 |
// CC unchanged by DIV. |
|
7492 |
ins_cost(ALU_REG_COST); |
|
7493 |
size(4); |
|
7494 |
format %{ "DEBR $dst,$src" %}
|
|
7495 |
opcode(DEBR_ZOPC); |
|
7496 |
ins_encode(z_rreform(dst, src)); |
|
7497 |
ins_pipe(pipe_class_dummy); |
|
7498 |
%} |
|
7499 |
||
7500 |
instruct divF_reg_mem(regF dst, memoryRX src)%{
|
|
7501 |
match(Set dst (DivF dst (LoadF src))); |
|
7502 |
// CC unchanged by DIV. |
|
7503 |
ins_cost(ALU_MEMORY_COST); |
|
7504 |
size(6); |
|
7505 |
format %{ "DEB $dst,$src\t # floatMemory" %}
|
|
7506 |
opcode(DEB_ZOPC); |
|
7507 |
ins_encode(z_form_rt_memFP(dst, src)); |
|
7508 |
ins_pipe(pipe_class_dummy); |
|
7509 |
%} |
|
7510 |
||
7511 |
// Div float double precision |
|
7512 |
instruct divD_reg_reg(regD dst, regD src) %{
|
|
7513 |
match(Set dst (DivD dst src)); |
|
7514 |
// CC unchanged by DIV. |
|
7515 |
ins_cost(ALU_REG_COST); |
|
7516 |
size(4); |
|
7517 |
format %{ "DDBR $dst,$src" %}
|
|
7518 |
opcode(DDBR_ZOPC); |
|
7519 |
ins_encode(z_rreform(dst, src)); |
|
7520 |
ins_pipe(pipe_class_dummy); |
|
7521 |
%} |
|
7522 |
||
7523 |
instruct divD_reg_mem(regD dst, memoryRX src)%{
|
|
7524 |
match(Set dst (DivD dst (LoadD src))); |
|
7525 |
// CC unchanged by DIV. |
|
7526 |
ins_cost(ALU_MEMORY_COST); |
|
7527 |
size(6); |
|
7528 |
format %{ "DDB $dst,$src\t # doubleMemory" %}
|
|
7529 |
opcode(DDB_ZOPC); |
|
7530 |
ins_encode(z_form_rt_memFP(dst, src)); |
|
7531 |
ins_pipe(pipe_class_dummy); |
|
7532 |
%} |
|
7533 |
||
7534 |
// ABS |
|
7535 |
||
7536 |
// Absolute float single precision |
|
7537 |
instruct absF_reg(regF dst, regF src, flagsReg cr) %{
|
|
7538 |
match(Set dst (AbsF src)); |
|
7539 |
effect(KILL cr); |
|
7540 |
size(4); |
|
7541 |
format %{ "LPEBR $dst,$src\t float" %}
|
|
7542 |
opcode(LPEBR_ZOPC); |
|
7543 |
ins_encode(z_rreform(dst, src)); |
|
7544 |
ins_pipe(pipe_class_dummy); |
|
7545 |
%} |
|
7546 |
||
7547 |
// Absolute float double precision |
|
7548 |
instruct absD_reg(regD dst, regD src, flagsReg cr) %{
|
|
7549 |
match(Set dst (AbsD src)); |
|
7550 |
effect(KILL cr); |
|
7551 |
size(4); |
|
7552 |
format %{ "LPDBR $dst,$src\t double" %}
|
|
7553 |
opcode(LPDBR_ZOPC); |
|
7554 |
ins_encode(z_rreform(dst, src)); |
|
7555 |
ins_pipe(pipe_class_dummy); |
|
7556 |
%} |
|
7557 |
||
7558 |
// NEG(ABS) |
|
7559 |
||
7560 |
// Negative absolute float single precision |
|
7561 |
instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{
|
|
7562 |
match(Set dst (NegF (AbsF src))); |
|
7563 |
effect(KILL cr); |
|
7564 |
size(4); |
|
7565 |
format %{ "LNEBR $dst,$src\t float" %}
|
|
7566 |
opcode(LNEBR_ZOPC); |
|
7567 |
ins_encode(z_rreform(dst, src)); |
|
7568 |
ins_pipe(pipe_class_dummy); |
|
7569 |
%} |
|
7570 |
||
7571 |
// Negative absolute float double precision |
|
7572 |
instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{
|
|
7573 |
match(Set dst (NegD (AbsD src))); |
|
7574 |
effect(KILL cr); |
|
7575 |
size(4); |
|
7576 |
format %{ "LNDBR $dst,$src\t double" %}
|
|
7577 |
opcode(LNDBR_ZOPC); |
|
7578 |
ins_encode(z_rreform(dst, src)); |
|
7579 |
ins_pipe(pipe_class_dummy); |
|
7580 |
%} |
|
7581 |
||
7582 |
// NEG |
|
7583 |
||
7584 |
instruct negF_reg(regF dst, regF src, flagsReg cr) %{
|
|
7585 |
match(Set dst (NegF src)); |
|
7586 |
effect(KILL cr); |
|
7587 |
size(4); |
|
7588 |
format %{ "NegF $dst,$src\t float" %}
|
|
7589 |
ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %}
|
|
7590 |
ins_pipe(pipe_class_dummy); |
|
7591 |
%} |
|
7592 |
||
7593 |
instruct negD_reg(regD dst, regD src, flagsReg cr) %{
|
|
7594 |
match(Set dst (NegD src)); |
|
7595 |
effect(KILL cr); |
|
7596 |
size(4); |
|
7597 |
format %{ "NegD $dst,$src\t double" %}
|
|
7598 |
ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %}
|
|
7599 |
ins_pipe(pipe_class_dummy); |
|
7600 |
%} |
|
7601 |
||
7602 |
// SQRT |
|
7603 |
||
7604 |
// Sqrt float precision |
|
7605 |
instruct sqrtF_reg(regF dst, regF src) %{
|
|
7606 |
match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); |
|
7607 |
// CC remains unchanged. |
|
7608 |
ins_cost(ALU_REG_COST); |
|
7609 |
size(4); |
|
7610 |
format %{ "SQEBR $dst,$src" %}
|
|
7611 |
opcode(SQEBR_ZOPC); |
|
7612 |
ins_encode(z_rreform(dst, src)); |
|
7613 |
ins_pipe(pipe_class_dummy); |
|
7614 |
%} |
|
7615 |
||
7616 |
// Sqrt double precision |
|
7617 |
instruct sqrtD_reg(regD dst, regD src) %{
|
|
7618 |
match(Set dst (SqrtD src)); |
|
7619 |
// CC remains unchanged. |
|
7620 |
ins_cost(ALU_REG_COST); |
|
7621 |
size(4); |
|
7622 |
format %{ "SQDBR $dst,$src" %}
|
|
7623 |
opcode(SQDBR_ZOPC); |
|
7624 |
ins_encode(z_rreform(dst, src)); |
|
7625 |
ins_pipe(pipe_class_dummy); |
|
7626 |
%} |
|
7627 |
||
7628 |
instruct sqrtF_mem(regF dst, memoryRX src) %{
|
|
7629 |
match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); |
|
7630 |
// CC remains unchanged. |
|
7631 |
ins_cost(ALU_MEMORY_COST); |
|
7632 |
size(6); |
|
7633 |
format %{ "SQEB $dst,$src\t # floatMemory" %}
|
|
7634 |
opcode(SQEB_ZOPC); |
|
7635 |
ins_encode(z_form_rt_memFP(dst, src)); |
|
7636 |
ins_pipe(pipe_class_dummy); |
|
7637 |
%} |
|
7638 |
||
7639 |
instruct sqrtD_mem(regD dst, memoryRX src) %{
|
|
7640 |
match(Set dst (SqrtD src)); |
|
7641 |
// CC remains unchanged. |
|
7642 |
ins_cost(ALU_MEMORY_COST); |
|
7643 |
// TODO: s390 port size(FIXED_SIZE); |
|
7644 |
format %{ "SQDB $dst,$src\t # doubleMemory" %}
|
|
7645 |
opcode(SQDB_ZOPC); |
|
7646 |
ins_encode(z_form_rt_memFP(dst, src)); |
|
7647 |
ins_pipe(pipe_class_dummy); |
|
7648 |
%} |
|
7649 |
||
7650 |
//----------Logical Instructions----------------------------------------------- |
|
7651 |
||
7652 |
// Register And |
|
7653 |
instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
|
|
7654 |
match(Set dst (AndI dst src)); |
|
7655 |
effect(KILL cr); |
|
7656 |
ins_cost(DEFAULT_COST_LOW); |
|
7657 |
size(2); |
|
7658 |
format %{ "NR $dst,$src\t # int" %}
|
|
7659 |
opcode(NR_ZOPC); |
|
7660 |
ins_encode(z_rrform(dst, src)); |
|
7661 |
ins_pipe(pipe_class_dummy); |
|
7662 |
%} |
|
7663 |
||
7664 |
instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
|
|
7665 |
match(Set dst (AndI dst (LoadI src))); |
|
7666 |
effect(KILL cr); |
|
7667 |
ins_cost(MEMORY_REF_COST); |
|
7668 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
7669 |
format %{ "N(Y) $dst, $src\t # int" %}
|
|
7670 |
opcode(NY_ZOPC, N_ZOPC); |
|
7671 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
7672 |
ins_pipe(pipe_class_dummy); |
|
7673 |
%} |
|
7674 |
||
7675 |
// Immediate And |
|
7676 |
instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
|
|
7677 |
match(Set dst (AndI dst src)); |
|
7678 |
effect(KILL cr); |
|
7679 |
ins_cost(DEFAULT_COST_HIGH); |
|
7680 |
size(6); |
|
7681 |
format %{ "NILF $dst,$src" %}
|
|
7682 |
opcode(NILF_ZOPC); |
|
7683 |
ins_encode(z_rilform_unsigned(dst, src)); |
|
7684 |
ins_pipe(pipe_class_dummy); |
|
7685 |
%} |
|
7686 |
||
7687 |
instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{
|
|
7688 |
match(Set dst (AndI dst src)); |
|
7689 |
effect(KILL cr); |
|
7690 |
ins_cost(DEFAULT_COST); |
|
7691 |
size(4); |
|
7692 |
format %{ "NILH $dst,$src" %}
|
|
7693 |
ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
|
|
7694 |
ins_pipe(pipe_class_dummy); |
|
7695 |
%} |
|
7696 |
||
7697 |
instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{
|
|
7698 |
match(Set dst (AndI dst src)); |
|
7699 |
effect(KILL cr); |
|
7700 |
ins_cost(DEFAULT_COST); |
|
7701 |
size(4); |
|
7702 |
format %{ "NILL $dst,$src" %}
|
|
7703 |
ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
|
|
7704 |
ins_pipe(pipe_class_dummy); |
|
7705 |
%} |
|
7706 |
||
7707 |
// Register And Long |
|
7708 |
instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
|
|
7709 |
match(Set dst (AndL dst src)); |
|
7710 |
effect(KILL cr); |
|
7711 |
ins_cost(DEFAULT_COST); |
|
7712 |
size(4); |
|
7713 |
format %{ "NGR $dst,$src\t # long" %}
|
|
7714 |
opcode(NGR_ZOPC); |
|
7715 |
ins_encode(z_rreform(dst, src)); |
|
7716 |
ins_pipe(pipe_class_dummy); |
|
7717 |
%} |
|
7718 |
||
7719 |
instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
|
|
7720 |
match(Set dst (AndL dst (LoadL src))); |
|
7721 |
effect(KILL cr); |
|
7722 |
ins_cost(MEMORY_REF_COST); |
|
7723 |
size(Z_DISP3_SIZE); |
|
7724 |
format %{ "NG $dst, $src\t # long" %}
|
|
7725 |
opcode(NG_ZOPC, NG_ZOPC); |
|
7726 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
7727 |
ins_pipe(pipe_class_dummy); |
|
7728 |
%} |
|
7729 |
||
7730 |
instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{
|
|
7731 |
match(Set dst (AndL dst src)); |
|
7732 |
effect(KILL cr); |
|
7733 |
ins_cost(DEFAULT_COST); |
|
7734 |
size(4); |
|
7735 |
format %{ "NILL $dst,$src\t # long" %}
|
|
7736 |
ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
|
|
7737 |
ins_pipe(pipe_class_dummy); |
|
7738 |
%} |
|
7739 |
||
7740 |
instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{
|
|
7741 |
match(Set dst (AndL dst src)); |
|
7742 |
effect(KILL cr); |
|
7743 |
ins_cost(DEFAULT_COST); |
|
7744 |
size(4); |
|
7745 |
format %{ "NILH $dst,$src\t # long" %}
|
|
7746 |
ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
|
|
7747 |
ins_pipe(pipe_class_dummy); |
|
7748 |
%} |
|
7749 |
||
7750 |
instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{
|
|
7751 |
match(Set dst (AndL dst src)); |
|
7752 |
effect(KILL cr); |
|
7753 |
ins_cost(DEFAULT_COST); |
|
7754 |
size(4); |
|
7755 |
format %{ "NIHL $dst,$src\t # long" %}
|
|
7756 |
ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %}
|
|
7757 |
ins_pipe(pipe_class_dummy); |
|
7758 |
%} |
|
7759 |
||
7760 |
instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{
|
|
7761 |
match(Set dst (AndL dst src)); |
|
7762 |
effect(KILL cr); |
|
7763 |
ins_cost(DEFAULT_COST); |
|
7764 |
size(4); |
|
7765 |
format %{ "NIHH $dst,$src\t # long" %}
|
|
7766 |
ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %}
|
|
7767 |
ins_pipe(pipe_class_dummy); |
|
7768 |
%} |
|
7769 |
||
7770 |
// OR |
|
7771 |
||
7772 |
// Or Instructions |
|
7773 |
// Register Or |
|
7774 |
instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
|
|
7775 |
match(Set dst (OrI dst src)); |
|
7776 |
effect(KILL cr); |
|
7777 |
size(2); |
|
7778 |
format %{ "OR $dst,$src" %}
|
|
7779 |
opcode(OR_ZOPC); |
|
7780 |
ins_encode(z_rrform(dst, src)); |
|
7781 |
ins_pipe(pipe_class_dummy); |
|
7782 |
%} |
|
7783 |
||
7784 |
instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
|
|
7785 |
match(Set dst (OrI dst (LoadI src))); |
|
7786 |
effect(KILL cr); |
|
7787 |
ins_cost(MEMORY_REF_COST); |
|
7788 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
7789 |
format %{ "O(Y) $dst, $src\t # int" %}
|
|
7790 |
opcode(OY_ZOPC, O_ZOPC); |
|
7791 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
7792 |
ins_pipe(pipe_class_dummy); |
|
7793 |
%} |
|
7794 |
||
7795 |
// Immediate Or |
|
7796 |
instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{
|
|
7797 |
match(Set dst (OrI dst con)); |
|
7798 |
effect(KILL cr); |
|
7799 |
size(4); |
|
7800 |
format %{ "OILL $dst,$con" %}
|
|
7801 |
opcode(OILL_ZOPC); |
|
7802 |
ins_encode(z_riform_unsigned(dst,con)); |
|
7803 |
ins_pipe(pipe_class_dummy); |
|
7804 |
%} |
|
7805 |
||
7806 |
instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{
|
|
7807 |
match(Set dst (OrI dst con)); |
|
7808 |
effect(KILL cr); |
|
7809 |
ins_cost(DEFAULT_COST_HIGH); |
|
7810 |
size(6); |
|
7811 |
format %{ "OILF $dst,$con" %}
|
|
7812 |
opcode(OILF_ZOPC); |
|
7813 |
ins_encode(z_rilform_unsigned(dst,con)); |
|
7814 |
ins_pipe(pipe_class_dummy); |
|
7815 |
%} |
|
7816 |
||
7817 |
// Register Or Long |
|
7818 |
instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
|
|
7819 |
match(Set dst (OrL dst src)); |
|
7820 |
effect(KILL cr); |
|
7821 |
ins_cost(DEFAULT_COST); |
|
7822 |
size(4); |
|
7823 |
format %{ "OGR $dst,$src\t # long" %}
|
|
7824 |
opcode(OGR_ZOPC); |
|
7825 |
ins_encode(z_rreform(dst, src)); |
|
7826 |
ins_pipe(pipe_class_dummy); |
|
7827 |
%} |
|
7828 |
||
7829 |
instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
|
|
7830 |
match(Set dst (OrL dst (LoadL src))); |
|
7831 |
effect(KILL cr); |
|
7832 |
ins_cost(MEMORY_REF_COST); |
|
7833 |
size(Z_DISP3_SIZE); |
|
7834 |
format %{ "OG $dst, $src\t # long" %}
|
|
7835 |
opcode(OG_ZOPC, OG_ZOPC); |
|
7836 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
7837 |
ins_pipe(pipe_class_dummy); |
|
7838 |
%} |
|
7839 |
||
7840 |
// Immediate Or long |
|
7841 |
instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{
|
|
7842 |
match(Set dst (OrL dst con)); |
|
7843 |
effect(KILL cr); |
|
7844 |
ins_cost(DEFAULT_COST); |
|
7845 |
size(4); |
|
7846 |
format %{ "OILL $dst,$con\t # long" %}
|
|
7847 |
opcode(OILL_ZOPC); |
|
7848 |
ins_encode(z_riform_unsigned(dst,con)); |
|
7849 |
ins_pipe(pipe_class_dummy); |
|
7850 |
%} |
|
7851 |
||
7852 |
instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{
|
|
7853 |
match(Set dst (OrI dst con)); |
|
7854 |
effect(KILL cr); |
|
7855 |
ins_cost(DEFAULT_COST_HIGH); |
|
7856 |
// TODO: s390 port size(FIXED_SIZE); |
|
7857 |
format %{ "OILF $dst,$con\t # long" %}
|
|
7858 |
opcode(OILF_ZOPC); |
|
7859 |
ins_encode(z_rilform_unsigned(dst,con)); |
|
7860 |
ins_pipe(pipe_class_dummy); |
|
7861 |
%} |
|
7862 |
||
7863 |
// XOR |
|
7864 |
||
7865 |
// Register Xor |
|
7866 |
instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
|
|
7867 |
match(Set dst (XorI dst src)); |
|
7868 |
effect(KILL cr); |
|
7869 |
size(2); |
|
7870 |
format %{ "XR $dst,$src" %}
|
|
7871 |
opcode(XR_ZOPC); |
|
7872 |
ins_encode(z_rrform(dst, src)); |
|
7873 |
ins_pipe(pipe_class_dummy); |
|
7874 |
%} |
|
7875 |
||
7876 |
instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
|
|
7877 |
match(Set dst (XorI dst (LoadI src))); |
|
7878 |
effect(KILL cr); |
|
7879 |
ins_cost(MEMORY_REF_COST); |
|
7880 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
7881 |
format %{ "X(Y) $dst, $src\t # int" %}
|
|
7882 |
opcode(XY_ZOPC, X_ZOPC); |
|
7883 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
7884 |
ins_pipe(pipe_class_dummy); |
|
7885 |
%} |
|
7886 |
||
7887 |
// Immediate Xor |
|
7888 |
instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
|
|
7889 |
match(Set dst (XorI dst src)); |
|
7890 |
effect(KILL cr); |
|
7891 |
ins_cost(DEFAULT_COST_HIGH); |
|
7892 |
size(6); |
|
7893 |
format %{ "XILF $dst,$src" %}
|
|
7894 |
opcode(XILF_ZOPC); |
|
7895 |
ins_encode(z_rilform_unsigned(dst, src)); |
|
7896 |
ins_pipe(pipe_class_dummy); |
|
7897 |
%} |
|
7898 |
||
7899 |
// Register Xor Long |
|
7900 |
instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
|
|
7901 |
match(Set dst (XorL dst src)); |
|
7902 |
effect(KILL cr); |
|
7903 |
ins_cost(DEFAULT_COST); |
|
7904 |
size(4); |
|
7905 |
format %{ "XGR $dst,$src\t # long" %}
|
|
7906 |
opcode(XGR_ZOPC); |
|
7907 |
ins_encode(z_rreform(dst, src)); |
|
7908 |
ins_pipe(pipe_class_dummy); |
|
7909 |
%} |
|
7910 |
||
7911 |
instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
|
|
7912 |
match(Set dst (XorL dst (LoadL src))); |
|
7913 |
effect(KILL cr); |
|
7914 |
ins_cost(MEMORY_REF_COST); |
|
7915 |
size(Z_DISP3_SIZE); |
|
7916 |
format %{ "XG $dst, $src\t # long" %}
|
|
7917 |
opcode(XG_ZOPC, XG_ZOPC); |
|
7918 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
7919 |
ins_pipe(pipe_class_dummy); |
|
7920 |
%} |
|
7921 |
||
7922 |
// Immediate Xor Long |
|
7923 |
instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{
|
|
7924 |
match(Set dst (XorL dst con)); |
|
7925 |
effect(KILL cr); |
|
7926 |
ins_cost(DEFAULT_COST_HIGH); |
|
7927 |
size(6); |
|
7928 |
format %{ "XILF $dst,$con\t # long" %}
|
|
7929 |
opcode(XILF_ZOPC); |
|
7930 |
ins_encode(z_rilform_unsigned(dst,con)); |
|
7931 |
ins_pipe(pipe_class_dummy); |
|
7932 |
%} |
|
7933 |
||
7934 |
//----------Convert to Boolean------------------------------------------------- |
|
7935 |
||
7936 |
// Convert integer to boolean. |
|
7937 |
instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{
|
|
7938 |
match(Set dst (Conv2B src)); |
|
7939 |
effect(KILL cr); |
|
7940 |
ins_cost(3 * DEFAULT_COST); |
|
7941 |
size(6); |
|
7942 |
format %{ "convI2B $dst,$src" %}
|
|
7943 |
ins_encode %{
|
|
7944 |
__ z_lnr($dst$$Register, $src$$Register); // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0 |
|
7945 |
__ z_srl($dst$$Register, 31); // Rdst := sign(Rdest) |
|
7946 |
%} |
|
7947 |
ins_pipe(pipe_class_dummy); |
|
7948 |
%} |
|
7949 |
||
7950 |
instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{
|
|
7951 |
match(Set dst (Conv2B src)); |
|
7952 |
effect(KILL cr); |
|
7953 |
ins_cost(3 * DEFAULT_COST); |
|
7954 |
size(10); |
|
7955 |
format %{ "convP2B $dst,$src" %}
|
|
7956 |
ins_encode %{
|
|
7957 |
__ z_lngr($dst$$Register, $src$$Register); // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0 |
|
7958 |
__ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest) |
|
7959 |
%} |
|
7960 |
ins_pipe(pipe_class_dummy); |
|
7961 |
%} |
|
7962 |
||
7963 |
instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
|
|
7964 |
match(Set dst (CmpLTMask dst src)); |
|
7965 |
effect(KILL cr); |
|
7966 |
ins_cost(2 * DEFAULT_COST); |
|
7967 |
size(18); |
|
7968 |
format %{ "Set $dst CmpLTMask $dst,$src" %}
|
|
7969 |
ins_encode %{
|
|
7970 |
// Avoid signed 32 bit overflow: Do sign extend and sub 64 bit. |
|
7971 |
__ z_lgfr(Z_R0_scratch, $src$$Register); |
|
7972 |
__ z_lgfr($dst$$Register, $dst$$Register); |
|
7973 |
__ z_sgr($dst$$Register, Z_R0_scratch); |
|
7974 |
__ z_srag($dst$$Register, $dst$$Register, 63); |
|
7975 |
%} |
|
7976 |
ins_pipe(pipe_class_dummy); |
|
7977 |
%} |
|
7978 |
||
7979 |
instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{
|
|
7980 |
match(Set dst (CmpLTMask dst zero)); |
|
7981 |
effect(KILL cr); |
|
7982 |
ins_cost(DEFAULT_COST); |
|
7983 |
size(4); |
|
7984 |
format %{ "Set $dst CmpLTMask $dst,$zero" %}
|
|
7985 |
ins_encode %{ __ z_sra($dst$$Register, 31); %}
|
|
7986 |
ins_pipe(pipe_class_dummy); |
|
7987 |
%} |
|
7988 |
||
7989 |
||
7990 |
//----------Arithmetic Conversion Instructions--------------------------------- |
|
7991 |
// The conversions operations are all Alpha sorted. Please keep it that way! |
|
7992 |
||
7993 |
instruct convD2F_reg(regF dst, regD src) %{
|
|
7994 |
match(Set dst (ConvD2F src)); |
|
7995 |
// CC remains unchanged. |
|
7996 |
size(4); |
|
7997 |
format %{ "LEDBR $dst,$src" %}
|
|
7998 |
opcode(LEDBR_ZOPC); |
|
7999 |
ins_encode(z_rreform(dst, src)); |
|
8000 |
ins_pipe(pipe_class_dummy); |
|
8001 |
%} |
|
8002 |
||
8003 |
instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{
|
|
8004 |
match(Set dst (ConvF2I src)); |
|
8005 |
effect(KILL cr); |
|
8006 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
8007 |
size(16); |
|
8008 |
format %{ "convF2I $dst,$src" %}
|
|
8009 |
ins_encode %{
|
|
8010 |
Label done; |
|
8011 |
__ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0. |
|
8012 |
__ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round. |
|
8013 |
__ z_brno(done); // Result is zero if unordered argument. |
|
8014 |
__ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); |
|
8015 |
__ bind(done); |
|
8016 |
%} |
|
8017 |
ins_pipe(pipe_class_dummy); |
|
8018 |
%} |
|
8019 |
||
8020 |
instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{
|
|
8021 |
match(Set dst (ConvD2I src)); |
|
8022 |
effect(KILL cr); |
|
8023 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
8024 |
size(16); |
|
8025 |
format %{ "convD2I $dst,$src" %}
|
|
8026 |
ins_encode %{
|
|
8027 |
Label done; |
|
8028 |
__ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0. |
|
8029 |
__ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round. |
|
8030 |
__ z_brno(done); // Result is zero if unordered argument. |
|
8031 |
__ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); |
|
8032 |
__ bind(done); |
|
8033 |
%} |
|
8034 |
ins_pipe(pipe_class_dummy); |
|
8035 |
%} |
|
8036 |
||
8037 |
instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{
|
|
8038 |
match(Set dst (ConvF2L src)); |
|
8039 |
effect(KILL cr); |
|
8040 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
8041 |
size(16); |
|
8042 |
format %{ "convF2L $dst,$src" %}
|
|
8043 |
ins_encode %{
|
|
8044 |
Label done; |
|
8045 |
__ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0. |
|
8046 |
__ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round. |
|
8047 |
__ z_brno(done); // Result is zero if unordered argument. |
|
8048 |
__ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); |
|
8049 |
__ bind(done); |
|
8050 |
%} |
|
8051 |
ins_pipe(pipe_class_dummy); |
|
8052 |
%} |
|
8053 |
||
8054 |
instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{
|
|
8055 |
match(Set dst (ConvD2L src)); |
|
8056 |
effect(KILL cr); |
|
8057 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
8058 |
size(16); |
|
8059 |
format %{ "convD2L $dst,$src" %}
|
|
8060 |
ins_encode %{
|
|
8061 |
Label done; |
|
8062 |
__ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0. |
|
8063 |
__ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round. |
|
8064 |
__ z_brno(done); // Result is zero if unordered argument. |
|
8065 |
__ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); |
|
8066 |
__ bind(done); |
|
8067 |
%} |
|
8068 |
ins_pipe(pipe_class_dummy); |
|
8069 |
%} |
|
8070 |
||
8071 |
instruct convF2D_reg(regD dst, regF src) %{
|
|
8072 |
match(Set dst (ConvF2D src)); |
|
8073 |
// CC remains unchanged. |
|
8074 |
size(4); |
|
8075 |
format %{ "LDEBR $dst,$src" %}
|
|
8076 |
opcode(LDEBR_ZOPC); |
|
8077 |
ins_encode(z_rreform(dst, src)); |
|
8078 |
ins_pipe(pipe_class_dummy); |
|
8079 |
%} |
|
8080 |
||
8081 |
instruct convF2D_mem(regD dst, memoryRX src) %{
|
|
8082 |
match(Set dst (ConvF2D src)); |
|
8083 |
// CC remains unchanged. |
|
8084 |
size(6); |
|
8085 |
format %{ "LDEB $dst,$src" %}
|
|
8086 |
opcode(LDEB_ZOPC); |
|
8087 |
ins_encode(z_form_rt_memFP(dst, src)); |
|
8088 |
ins_pipe(pipe_class_dummy); |
|
8089 |
%} |
|
8090 |
||
8091 |
instruct convI2D_reg(regD dst, iRegI src) %{
|
|
8092 |
match(Set dst (ConvI2D src)); |
|
8093 |
// CC remains unchanged. |
|
8094 |
ins_cost(DEFAULT_COST); |
|
8095 |
size(4); |
|
8096 |
format %{ "CDFBR $dst,$src" %}
|
|
8097 |
opcode(CDFBR_ZOPC); |
|
8098 |
ins_encode(z_rreform(dst, src)); |
|
8099 |
ins_pipe(pipe_class_dummy); |
|
8100 |
%} |
|
8101 |
||
8102 |
// Optimization that saves up to two memory operations for each conversion. |
|
8103 |
instruct convI2F_ireg(regF dst, iRegI src) %{
|
|
8104 |
match(Set dst (ConvI2F src)); |
|
8105 |
// CC remains unchanged. |
|
8106 |
ins_cost(DEFAULT_COST); |
|
8107 |
size(4); |
|
8108 |
format %{ "CEFBR $dst,$src\t # convert int to float" %}
|
|
8109 |
opcode(CEFBR_ZOPC); |
|
8110 |
ins_encode(z_rreform(dst, src)); |
|
8111 |
ins_pipe(pipe_class_dummy); |
|
8112 |
%} |
|
8113 |
||
8114 |
instruct convI2L_reg(iRegL dst, iRegI src) %{
|
|
8115 |
match(Set dst (ConvI2L src)); |
|
8116 |
size(4); |
|
8117 |
format %{ "LGFR $dst,$src\t # int->long" %}
|
|
8118 |
opcode(LGFR_ZOPC); |
|
8119 |
ins_encode(z_rreform(dst, src)); |
|
8120 |
ins_pipe(pipe_class_dummy); |
|
8121 |
%} |
|
8122 |
||
8123 |
// Zero-extend convert int to long. |
|
8124 |
instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{
|
|
8125 |
match(Set dst (AndL (ConvI2L src) mask)); |
|
8126 |
size(4); |
|
8127 |
format %{ "LLGFR $dst, $src \t # zero-extend int to long" %}
|
|
8128 |
ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
|
|
8129 |
ins_pipe(pipe_class_dummy); |
|
8130 |
%} |
|
8131 |
||
8132 |
// Zero-extend convert int to long. |
|
8133 |
instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{
|
|
8134 |
match(Set dst (AndL (ConvI2L (LoadI src)) mask)); |
|
8135 |
// Uses load_const_optmized, so size can vary. |
|
8136 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8137 |
format %{ "LLGF $dst, $src \t # zero-extend int to long" %}
|
|
8138 |
opcode(LLGF_ZOPC, LLGF_ZOPC); |
|
8139 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
8140 |
ins_pipe(pipe_class_dummy); |
|
8141 |
%} |
|
8142 |
||
8143 |
// Zero-extend long |
|
8144 |
instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{
|
|
8145 |
match(Set dst (AndL src mask)); |
|
8146 |
size(4); |
|
8147 |
format %{ "LLGFR $dst, $src \t # zero-extend long to long" %}
|
|
8148 |
ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
|
|
8149 |
ins_pipe(pipe_class_dummy); |
|
8150 |
%} |
|
8151 |
||
8152 |
instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{
|
|
8153 |
match(Set dst (RShiftI (LShiftI src amount) amount)); |
|
8154 |
size(4); |
|
8155 |
format %{ "LHR $dst,$src\t short->int" %}
|
|
8156 |
opcode(LHR_ZOPC); |
|
8157 |
ins_encode(z_rreform(dst, src)); |
|
8158 |
ins_pipe(pipe_class_dummy); |
|
8159 |
%} |
|
8160 |
||
8161 |
instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{
|
|
8162 |
match(Set dst (RShiftI (LShiftI src amount) amount)); |
|
8163 |
size(4); |
|
8164 |
format %{ "LBR $dst,$src\t byte->int" %}
|
|
8165 |
opcode(LBR_ZOPC); |
|
8166 |
ins_encode(z_rreform(dst, src)); |
|
8167 |
ins_pipe(pipe_class_dummy); |
|
8168 |
%} |
|
8169 |
||
8170 |
instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
|
|
8171 |
match(Set dst (MoveF2I src)); |
|
8172 |
ins_cost(MEMORY_REF_COST); |
|
8173 |
size(4); |
|
8174 |
format %{ "L $dst,$src\t # MoveF2I" %}
|
|
8175 |
opcode(L_ZOPC); |
|
8176 |
ins_encode(z_form_rt_mem(dst, src)); |
|
8177 |
ins_pipe(pipe_class_dummy); |
|
8178 |
%} |
|
8179 |
||
8180 |
// javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII) |
|
8181 |
instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
|
|
8182 |
match(Set dst (MoveI2F src)); |
|
8183 |
ins_cost(MEMORY_REF_COST); |
|
8184 |
// TODO: s390 port size(FIXED_SIZE); |
|
8185 |
format %{ "LE $dst,$src\t # MoveI2F" %}
|
|
8186 |
opcode(LE_ZOPC); |
|
8187 |
ins_encode(z_form_rt_mem(dst, src)); |
|
8188 |
ins_pipe(pipe_class_dummy); |
|
8189 |
%} |
|
8190 |
||
8191 |
instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
|
|
8192 |
match(Set dst (MoveD2L src)); |
|
8193 |
ins_cost(MEMORY_REF_COST); |
|
8194 |
size(6); |
|
8195 |
format %{ "LG $src,$dst\t # MoveD2L" %}
|
|
8196 |
opcode(LG_ZOPC); |
|
8197 |
ins_encode(z_form_rt_mem(dst, src)); |
|
8198 |
ins_pipe(pipe_class_dummy); |
|
8199 |
%} |
|
8200 |
||
8201 |
instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
|
|
8202 |
match(Set dst (MoveL2D src)); |
|
8203 |
ins_cost(MEMORY_REF_COST); |
|
8204 |
size(4); |
|
8205 |
format %{ "LD $dst,$src\t # MoveL2D" %}
|
|
8206 |
opcode(LD_ZOPC); |
|
8207 |
ins_encode(z_form_rt_mem(dst, src)); |
|
8208 |
ins_pipe(pipe_class_dummy); |
|
8209 |
%} |
|
8210 |
||
8211 |
instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
|
|
8212 |
match(Set dst (MoveI2F src)); |
|
8213 |
ins_cost(MEMORY_REF_COST); |
|
8214 |
size(4); |
|
8215 |
format %{ "ST $src,$dst\t # MoveI2F" %}
|
|
8216 |
opcode(ST_ZOPC); |
|
8217 |
ins_encode(z_form_rt_mem(src, dst)); |
|
8218 |
ins_pipe(pipe_class_dummy); |
|
8219 |
%} |
|
8220 |
||
8221 |
instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
|
|
8222 |
match(Set dst (MoveD2L src)); |
|
8223 |
effect(DEF dst, USE src); |
|
8224 |
ins_cost(MEMORY_REF_COST); |
|
8225 |
size(4); |
|
8226 |
format %{ "STD $src,$dst\t # MoveD2L" %}
|
|
8227 |
opcode(STD_ZOPC); |
|
8228 |
ins_encode(z_form_rt_mem(src,dst)); |
|
8229 |
ins_pipe(pipe_class_dummy); |
|
8230 |
%} |
|
8231 |
||
8232 |
instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
|
|
8233 |
match(Set dst (MoveL2D src)); |
|
8234 |
ins_cost(MEMORY_REF_COST); |
|
8235 |
size(6); |
|
8236 |
format %{ "STG $src,$dst\t # MoveL2D" %}
|
|
8237 |
opcode(STG_ZOPC); |
|
8238 |
ins_encode(z_form_rt_mem(src,dst)); |
|
8239 |
ins_pipe(pipe_class_dummy); |
|
8240 |
%} |
|
8241 |
||
8242 |
instruct convL2F_reg(regF dst, iRegL src) %{
|
|
8243 |
match(Set dst (ConvL2F src)); |
|
8244 |
// CC remains unchanged. |
|
8245 |
ins_cost(DEFAULT_COST); |
|
8246 |
size(4); |
|
8247 |
format %{ "CEGBR $dst,$src" %}
|
|
8248 |
opcode(CEGBR_ZOPC); |
|
8249 |
ins_encode(z_rreform(dst, src)); |
|
8250 |
ins_pipe(pipe_class_dummy); |
|
8251 |
%} |
|
8252 |
||
8253 |
instruct convL2D_reg(regD dst, iRegL src) %{
|
|
8254 |
match(Set dst (ConvL2D src)); |
|
8255 |
// CC remains unchanged. |
|
8256 |
ins_cost(DEFAULT_COST); |
|
8257 |
size(4); |
|
8258 |
format %{ "CDGBR $dst,$src" %}
|
|
8259 |
opcode(CDGBR_ZOPC); |
|
8260 |
ins_encode(z_rreform(dst, src)); |
|
8261 |
ins_pipe(pipe_class_dummy); |
|
8262 |
%} |
|
8263 |
||
8264 |
instruct convL2I_reg(iRegI dst, iRegL src) %{
|
|
8265 |
match(Set dst (ConvL2I src)); |
|
8266 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8267 |
format %{ "LR $dst,$src\t # long->int (if needed)" %}
|
|
8268 |
ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %}
|
|
8269 |
ins_pipe(pipe_class_dummy); |
|
8270 |
%} |
|
8271 |
||
8272 |
// Register Shift Right Immediate |
|
8273 |
instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{
|
|
8274 |
match(Set dst (ConvL2I (RShiftL src cnt))); |
|
8275 |
effect(KILL cr); |
|
8276 |
size(6); |
|
8277 |
format %{ "SRAG $dst,$src,$cnt" %}
|
|
8278 |
opcode(SRAG_ZOPC); |
|
8279 |
ins_encode(z_rsyform_const(dst, src, cnt)); |
|
8280 |
ins_pipe(pipe_class_dummy); |
|
8281 |
%} |
|
8282 |
||
8283 |
//----------TRAP based zero checks and range checks---------------------------- |
|
8284 |
||
8285 |
// SIGTRAP based implicit range checks in compiled code. |
|
8286 |
// A range check in the ideal world has one of the following shapes: |
|
8287 |
// - (If le (CmpU length index)), (IfTrue throw exception) |
|
8288 |
// - (If lt (CmpU index length)), (IfFalse throw exception) |
|
8289 |
// |
|
8290 |
// Match range check 'If le (CmpU length index)' |
|
8291 |
instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{
|
|
8292 |
match(If cmp (CmpU length index)); |
|
8293 |
effect(USE labl); |
|
8294 |
predicate(TrapBasedRangeChecks && |
|
8295 |
_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && |
|
8296 |
PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS && |
|
8297 |
Matcher::branches_to_uncommon_trap(_leaf)); |
|
8298 |
ins_cost(1); |
|
8299 |
// TODO: s390 port size(FIXED_SIZE); |
|
8300 |
||
8301 |
ins_is_TrapBasedCheckNode(true); |
|
8302 |
||
8303 |
format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %}
|
|
8304 |
ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %}
|
|
8305 |
ins_pipe(pipe_class_trap); |
|
8306 |
%} |
|
8307 |
||
8308 |
// Match range check 'If lt (CmpU index length)' |
|
8309 |
instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{
|
|
8310 |
match(If cmp (CmpU index length)); |
|
8311 |
effect(USE labl, KILL cr); |
|
8312 |
predicate(TrapBasedRangeChecks && |
|
8313 |
_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && |
|
8314 |
_leaf->as_If ()->_prob >= PROB_ALWAYS && |
|
8315 |
Matcher::branches_to_uncommon_trap(_leaf)); |
|
8316 |
ins_cost(1); |
|
8317 |
// TODO: s390 port size(FIXED_SIZE); |
|
8318 |
||
8319 |
ins_is_TrapBasedCheckNode(true); |
|
8320 |
||
8321 |
format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %}
|
|
8322 |
ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %}
|
|
8323 |
ins_pipe(pipe_class_trap); |
|
8324 |
%} |
|
8325 |
||
8326 |
// Match range check 'If lt (CmpU index length)' |
|
8327 |
instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{
|
|
8328 |
match(If cmp (CmpU index length)); |
|
8329 |
effect(USE labl); |
|
8330 |
predicate(TrapBasedRangeChecks && |
|
8331 |
_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && |
|
8332 |
_leaf->as_If ()->_prob >= PROB_ALWAYS && |
|
8333 |
Matcher::branches_to_uncommon_trap(_leaf)); |
|
8334 |
ins_cost(1); |
|
8335 |
// TODO: s390 port size(FIXED_SIZE); |
|
8336 |
||
8337 |
ins_is_TrapBasedCheckNode(true); |
|
8338 |
||
8339 |
format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %}
|
|
8340 |
ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %}
|
|
8341 |
ins_pipe(pipe_class_trap); |
|
8342 |
%} |
|
8343 |
||
8344 |
// Implicit zero checks (more implicit null checks). |
|
8345 |
instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{
|
|
8346 |
match(If cmp (CmpP value zero)); |
|
8347 |
effect(USE labl); |
|
8348 |
predicate(TrapBasedNullChecks && |
|
8349 |
_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && |
|
8350 |
_leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) && |
|
8351 |
Matcher::branches_to_uncommon_trap(_leaf)); |
|
8352 |
size(6); |
|
8353 |
||
8354 |
ins_is_TrapBasedCheckNode(true); |
|
8355 |
||
8356 |
format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %}
|
|
8357 |
ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %}
|
|
8358 |
ins_pipe(pipe_class_trap); |
|
8359 |
%} |
|
8360 |
||
8361 |
// Implicit zero checks (more implicit null checks). |
|
8362 |
instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{
|
|
8363 |
match(If cmp (CmpN value zero)); |
|
8364 |
effect(USE labl); |
|
8365 |
predicate(TrapBasedNullChecks && |
|
8366 |
_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && |
|
8367 |
_leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) && |
|
8368 |
Matcher::branches_to_uncommon_trap(_leaf)); |
|
8369 |
size(6); |
|
8370 |
||
8371 |
ins_is_TrapBasedCheckNode(true); |
|
8372 |
||
8373 |
format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %}
|
|
8374 |
ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %}
|
|
8375 |
ins_pipe(pipe_class_trap); |
|
8376 |
%} |
|
8377 |
||
8378 |
//----------Compare instructions----------------------------------------------- |
|
8379 |
||
8380 |
// INT signed |
|
8381 |
||
8382 |
// Compare Integers |
|
8383 |
instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
|
|
8384 |
match(Set cr (CmpI op1 op2)); |
|
8385 |
size(2); |
|
8386 |
format %{ "CR $op1,$op2" %}
|
|
8387 |
opcode(CR_ZOPC); |
|
8388 |
ins_encode(z_rrform(op1, op2)); |
|
8389 |
ins_pipe(pipe_class_dummy); |
|
8390 |
%} |
|
8391 |
||
8392 |
instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
|
|
8393 |
match(Set cr (CmpI op1 op2)); |
|
8394 |
size(6); |
|
8395 |
format %{ "CFI $op1,$op2" %}
|
|
8396 |
opcode(CFI_ZOPC); |
|
8397 |
ins_encode(z_rilform_signed(op1, op2)); |
|
8398 |
ins_pipe(pipe_class_dummy); |
|
8399 |
%} |
|
8400 |
||
8401 |
instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{
|
|
8402 |
match(Set cr (CmpI op1 op2)); |
|
8403 |
size(4); |
|
8404 |
format %{ "CHI $op1,$op2" %}
|
|
8405 |
opcode(CHI_ZOPC); |
|
8406 |
ins_encode(z_riform_signed(op1, op2)); |
|
8407 |
ins_pipe(pipe_class_dummy); |
|
8408 |
%} |
|
8409 |
||
8410 |
instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
|
|
8411 |
match(Set cr (CmpI op1 zero)); |
|
8412 |
ins_cost(DEFAULT_COST_LOW); |
|
8413 |
size(2); |
|
8414 |
format %{ "LTR $op1,$op1" %}
|
|
8415 |
opcode(LTR_ZOPC); |
|
8416 |
ins_encode(z_rrform(op1, op1)); |
|
8417 |
ins_pipe(pipe_class_dummy); |
|
8418 |
%} |
|
8419 |
||
8420 |
instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
|
|
8421 |
match(Set cr (CmpI op1 (LoadI op2))); |
|
8422 |
ins_cost(MEMORY_REF_COST); |
|
8423 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8424 |
format %{ "C(Y) $op1, $op2\t # int" %}
|
|
8425 |
opcode(CY_ZOPC, C_ZOPC); |
|
8426 |
ins_encode(z_form_rt_mem_opt(op1, op2)); |
|
8427 |
ins_pipe(pipe_class_dummy); |
|
8428 |
%} |
|
8429 |
||
8430 |
// INT unsigned |
|
8431 |
||
8432 |
instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
|
|
8433 |
match(Set cr (CmpU op1 op2)); |
|
8434 |
size(2); |
|
8435 |
format %{ "CLR $op1,$op2\t # unsigned" %}
|
|
8436 |
opcode(CLR_ZOPC); |
|
8437 |
ins_encode(z_rrform(op1, op2)); |
|
8438 |
ins_pipe(pipe_class_dummy); |
|
8439 |
%} |
|
8440 |
||
8441 |
instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
|
|
8442 |
match(Set cr (CmpU op1 op2)); |
|
8443 |
size(6); |
|
8444 |
format %{ "CLFI $op1,$op2\t # unsigned" %}
|
|
8445 |
opcode(CLFI_ZOPC); |
|
8446 |
ins_encode(z_rilform_unsigned(op1, op2)); |
|
8447 |
ins_pipe(pipe_class_dummy); |
|
8448 |
%} |
|
8449 |
||
8450 |
instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
|
|
8451 |
match(Set cr (CmpU op1 (LoadI op2))); |
|
8452 |
ins_cost(MEMORY_REF_COST); |
|
8453 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8454 |
format %{ "CL(Y) $op1, $op2\t # unsigned" %}
|
|
8455 |
opcode(CLY_ZOPC, CL_ZOPC); |
|
8456 |
ins_encode(z_form_rt_mem_opt(op1, op2)); |
|
8457 |
ins_pipe(pipe_class_dummy); |
|
8458 |
%} |
|
8459 |
||
8460 |
// LONG signed |
|
8461 |
||
8462 |
instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
|
|
8463 |
match(Set cr (CmpL op1 op2)); |
|
8464 |
size(4); |
|
8465 |
format %{ "CGR $op1,$op2\t # long" %}
|
|
8466 |
opcode(CGR_ZOPC); |
|
8467 |
ins_encode(z_rreform(op1, op2)); |
|
8468 |
ins_pipe(pipe_class_dummy); |
|
8469 |
%} |
|
8470 |
||
8471 |
instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{
|
|
8472 |
match(Set cr (CmpL op1 (ConvI2L op2))); |
|
8473 |
size(4); |
|
8474 |
format %{ "CGFR $op1,$op2\t # long/int" %}
|
|
8475 |
opcode(CGFR_ZOPC); |
|
8476 |
ins_encode(z_rreform(op1, op2)); |
|
8477 |
ins_pipe(pipe_class_dummy); |
|
8478 |
%} |
|
8479 |
||
8480 |
instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{
|
|
8481 |
match(Set cr (CmpL op1 con)); |
|
8482 |
size(6); |
|
8483 |
format %{ "CGFI $op1,$con" %}
|
|
8484 |
opcode(CGFI_ZOPC); |
|
8485 |
ins_encode(z_rilform_signed(op1, con)); |
|
8486 |
ins_pipe(pipe_class_dummy); |
|
8487 |
%} |
|
8488 |
||
8489 |
instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{
|
|
8490 |
match(Set cr (CmpL op1 con)); |
|
8491 |
size(4); |
|
8492 |
format %{ "CGHI $op1,$con" %}
|
|
8493 |
opcode(CGHI_ZOPC); |
|
8494 |
ins_encode(z_riform_signed(op1, con)); |
|
8495 |
ins_pipe(pipe_class_dummy); |
|
8496 |
%} |
|
8497 |
||
8498 |
instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{
|
|
8499 |
match(Set cr (CmpL op1 con)); |
|
8500 |
ins_cost(DEFAULT_COST_LOW); |
|
8501 |
size(4); |
|
8502 |
format %{ "LTGR $op1,$op1" %}
|
|
8503 |
opcode(LTGR_ZOPC); |
|
8504 |
ins_encode(z_rreform(op1, op1)); |
|
8505 |
ins_pipe(pipe_class_dummy); |
|
8506 |
%} |
|
8507 |
||
8508 |
instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{
|
|
8509 |
match(Set cr (CmpL (ConvI2L op1) con)); |
|
8510 |
ins_cost(DEFAULT_COST_LOW); |
|
8511 |
size(4); |
|
8512 |
format %{ "LTGFR $op1,$op1" %}
|
|
8513 |
opcode(LTGFR_ZOPC); |
|
8514 |
ins_encode(z_rreform(op1, op1)); |
|
8515 |
ins_pipe(pipe_class_dummy); |
|
8516 |
%} |
|
8517 |
||
8518 |
instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{
|
|
8519 |
match(Set cr (CmpL dst (LoadL src))); |
|
8520 |
ins_cost(MEMORY_REF_COST); |
|
8521 |
size(Z_DISP3_SIZE); |
|
8522 |
format %{ "CG $dst, $src\t # long" %}
|
|
8523 |
opcode(CG_ZOPC, CG_ZOPC); |
|
8524 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
8525 |
ins_pipe(pipe_class_dummy); |
|
8526 |
%} |
|
8527 |
||
8528 |
instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{
|
|
8529 |
match(Set cr (CmpL dst (ConvI2L (LoadI src)))); |
|
8530 |
ins_cost(MEMORY_REF_COST); |
|
8531 |
size(Z_DISP3_SIZE); |
|
8532 |
format %{ "CGF $dst, $src\t # long/int" %}
|
|
8533 |
opcode(CGF_ZOPC, CGF_ZOPC); |
|
8534 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
8535 |
ins_pipe(pipe_class_dummy); |
|
8536 |
%} |
|
8537 |
||
8538 |
// LONG unsigned |
|
| 45966 | 8539 |
// Added CmpUL for LoopPredicate. |
8540 |
instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
|
|
8541 |
match(Set cr (CmpUL op1 op2)); |
|
8542 |
size(4); |
|
8543 |
format %{ "CLGR $op1,$op2\t # long" %}
|
|
8544 |
opcode(CLGR_ZOPC); |
|
8545 |
ins_encode(z_rreform(op1, op2)); |
|
8546 |
ins_pipe(pipe_class_dummy); |
|
8547 |
%} |
|
8548 |
||
8549 |
instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{
|
|
8550 |
match(Set cr (CmpUL op1 con)); |
|
8551 |
size(6); |
|
8552 |
format %{ "CLGFI $op1,$con" %}
|
|
8553 |
opcode(CLGFI_ZOPC); |
|
8554 |
ins_encode(z_rilform_unsigned(op1, con)); |
|
8555 |
ins_pipe(pipe_class_dummy); |
|
8556 |
%} |
|
| 42065 | 8557 |
|
8558 |
// PTR unsigned |
|
8559 |
||
8560 |
instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{
|
|
8561 |
match(Set cr (CmpP op1 op2)); |
|
8562 |
size(4); |
|
8563 |
format %{ "CLGR $op1,$op2\t # ptr" %}
|
|
8564 |
opcode(CLGR_ZOPC); |
|
8565 |
ins_encode(z_rreform(op1, op2)); |
|
8566 |
ins_pipe(pipe_class_dummy); |
|
8567 |
%} |
|
8568 |
||
8569 |
instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{
|
|
8570 |
match(Set cr (CmpP op1 op2)); |
|
8571 |
ins_cost(DEFAULT_COST_LOW); |
|
8572 |
size(4); |
|
8573 |
format %{ "LTGR $op1, $op1\t # ptr" %}
|
|
8574 |
opcode(LTGR_ZOPC); |
|
8575 |
ins_encode(z_rreform(op1, op1)); |
|
8576 |
ins_pipe(pipe_class_dummy); |
|
8577 |
%} |
|
8578 |
||
8579 |
// Don't use LTGFR which performs sign extend. |
|
8580 |
instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{
|
|
8581 |
match(Set cr (CmpP (DecodeN op1) op2)); |
|
|
54780
f8d182aedc92
8223136: Move compressed oops functions to CompressedOops class
stefank
parents:
54542
diff
changeset
|
8582 |
predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0); |
| 42065 | 8583 |
ins_cost(DEFAULT_COST_LOW); |
8584 |
size(2); |
|
8585 |
format %{ "LTR $op1, $op1\t # ptr" %}
|
|
8586 |
opcode(LTR_ZOPC); |
|
8587 |
ins_encode(z_rrform(op1, op1)); |
|
8588 |
ins_pipe(pipe_class_dummy); |
|
8589 |
%} |
|
8590 |
||
8591 |
instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{
|
|
8592 |
match(Set cr (CmpP dst (LoadP src))); |
|
8593 |
ins_cost(MEMORY_REF_COST); |
|
8594 |
size(Z_DISP3_SIZE); |
|
8595 |
format %{ "CLG $dst, $src\t # ptr" %}
|
|
8596 |
opcode(CLG_ZOPC, CLG_ZOPC); |
|
8597 |
ins_encode(z_form_rt_mem_opt(dst, src)); |
|
8598 |
ins_pipe(pipe_class_dummy); |
|
8599 |
%} |
|
8600 |
||
8601 |
//----------Max and Min-------------------------------------------------------- |
|
8602 |
||
8603 |
// Max Register with Register |
|
8604 |
instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
|
|
8605 |
match(Set dst (MinI src1 src2)); |
|
8606 |
effect(KILL cr); |
|
8607 |
predicate(VM_Version::has_LoadStoreConditional()); |
|
8608 |
ins_cost(3 * DEFAULT_COST); |
|
8609 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8610 |
format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %}
|
|
8611 |
ins_encode %{
|
|
8612 |
Register Rdst = $dst$$Register; |
|
8613 |
Register Rsrc1 = $src1$$Register; |
|
8614 |
Register Rsrc2 = $src2$$Register; |
|
8615 |
||
8616 |
if (Rsrc1 == Rsrc2) {
|
|
8617 |
if (Rdst != Rsrc1) {
|
|
8618 |
__ z_lgfr(Rdst, Rsrc1); |
|
8619 |
} |
|
8620 |
} else if (Rdst == Rsrc1) { // Rdst preset with src1.
|
|
8621 |
__ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotLow. |
|
8622 |
__ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow); |
|
8623 |
} else if (Rdst == Rsrc2) { // Rdst preset with src2.
|
|
8624 |
__ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotLow. |
|
8625 |
__ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow); |
|
8626 |
} else {
|
|
8627 |
// Rdst is disjoint from operands, move in either case. |
|
8628 |
__ z_cr(Rsrc1, Rsrc2); |
|
8629 |
__ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow); |
|
8630 |
__ z_locr(Rdst, Rsrc1, Assembler::bcondLow); |
|
8631 |
} |
|
8632 |
%} |
|
8633 |
ins_pipe(pipe_class_dummy); |
|
8634 |
%} |
|
8635 |
||
8636 |
// Min Register with Register. |
|
8637 |
instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
|
|
8638 |
match(Set dst (MinI src1 src2)); |
|
8639 |
effect(KILL cr); |
|
8640 |
predicate(VM_Version::has_CompareBranch()); |
|
8641 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
8642 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8643 |
format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %}
|
|
8644 |
ins_encode %{
|
|
8645 |
Register Rdst = $dst$$Register; |
|
8646 |
Register Rsrc1 = $src1$$Register; |
|
8647 |
Register Rsrc2 = $src2$$Register; |
|
8648 |
Label done; |
|
8649 |
||
8650 |
if (Rsrc1 == Rsrc2) {
|
|
8651 |
if (Rdst != Rsrc1) {
|
|
8652 |
__ z_lgfr(Rdst, Rsrc1); |
|
8653 |
} |
|
8654 |
} else if (Rdst == Rsrc1) {
|
|
8655 |
__ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done); |
|
8656 |
__ z_lgfr(Rdst, Rsrc2); |
|
8657 |
} else if (Rdst == Rsrc2) {
|
|
8658 |
__ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done); |
|
8659 |
__ z_lgfr(Rdst, Rsrc1); |
|
8660 |
} else {
|
|
8661 |
__ z_lgfr(Rdst, Rsrc1); |
|
8662 |
__ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done); |
|
8663 |
__ z_lgfr(Rdst, Rsrc2); |
|
8664 |
} |
|
8665 |
__ bind(done); |
|
8666 |
%} |
|
8667 |
ins_pipe(pipe_class_dummy); |
|
8668 |
%} |
|
8669 |
||
8670 |
instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
|
|
8671 |
match(Set dst (MinI src1 src2)); |
|
8672 |
effect(KILL cr); |
|
8673 |
predicate(!VM_Version::has_CompareBranch()); |
|
8674 |
ins_cost(3 * DEFAULT_COST + BRANCH_COST); |
|
8675 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8676 |
format %{ "MinI $dst $src1,$src2\t MinI" %}
|
|
8677 |
ins_encode %{
|
|
8678 |
Register Rdst = $dst$$Register; |
|
8679 |
Register Rsrc1 = $src1$$Register; |
|
8680 |
Register Rsrc2 = $src2$$Register; |
|
8681 |
Label done; |
|
8682 |
||
8683 |
if (Rsrc1 == Rsrc2) {
|
|
8684 |
if (Rdst != Rsrc1) {
|
|
8685 |
__ z_lgfr(Rdst, Rsrc1); |
|
8686 |
} |
|
8687 |
} else if (Rdst == Rsrc1) {
|
|
8688 |
__ z_cr(Rsrc1, Rsrc2); |
|
8689 |
__ z_brl(done); |
|
8690 |
__ z_lgfr(Rdst, Rsrc2); |
|
8691 |
} else if (Rdst == Rsrc2) {
|
|
8692 |
__ z_cr(Rsrc2, Rsrc1); |
|
8693 |
__ z_brl(done); |
|
8694 |
__ z_lgfr(Rdst, Rsrc1); |
|
8695 |
} else {
|
|
8696 |
__ z_lgfr(Rdst, Rsrc1); |
|
8697 |
__ z_cr(Rsrc1, Rsrc2); |
|
8698 |
__ z_brl(done); |
|
8699 |
__ z_lgfr(Rdst, Rsrc2); |
|
8700 |
} |
|
8701 |
__ bind(done); |
|
8702 |
%} |
|
8703 |
ins_pipe(pipe_class_dummy); |
|
8704 |
%} |
|
8705 |
||
8706 |
instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
|
|
8707 |
match(Set dst (MinI src1 src2)); |
|
8708 |
effect(KILL cr); |
|
8709 |
predicate(VM_Version::has_LoadStoreConditional()); |
|
8710 |
ins_cost(3 * DEFAULT_COST); |
|
8711 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8712 |
format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %}
|
|
8713 |
ins_encode %{
|
|
8714 |
Register Rdst = $dst$$Register; |
|
8715 |
Register Rsrc1 = $src1$$Register; |
|
8716 |
int Isrc2 = $src2$$constant; |
|
8717 |
||
8718 |
if (Rdst == Rsrc1) {
|
|
8719 |
__ load_const_optimized(Z_R0_scratch, Isrc2); |
|
8720 |
__ z_cfi(Rsrc1, Isrc2); |
|
8721 |
__ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow); |
|
8722 |
} else {
|
|
8723 |
__ load_const_optimized(Rdst, Isrc2); |
|
8724 |
__ z_cfi(Rsrc1, Isrc2); |
|
8725 |
__ z_locr(Rdst, Rsrc1, Assembler::bcondLow); |
|
8726 |
} |
|
8727 |
%} |
|
8728 |
ins_pipe(pipe_class_dummy); |
|
8729 |
%} |
|
8730 |
||
8731 |
instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
|
|
8732 |
match(Set dst (MinI src1 src2)); |
|
8733 |
effect(KILL cr); |
|
8734 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
8735 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8736 |
format %{ "MinI $dst $src1,$src2\t MinI const32" %}
|
|
8737 |
ins_encode %{
|
|
8738 |
Label done; |
|
8739 |
if ($dst$$Register != $src1$$Register) {
|
|
8740 |
__ z_lgfr($dst$$Register, $src1$$Register); |
|
8741 |
} |
|
8742 |
__ z_cfi($src1$$Register, $src2$$constant); |
|
8743 |
__ z_brl(done); |
|
8744 |
__ z_lgfi($dst$$Register, $src2$$constant); |
|
8745 |
__ bind(done); |
|
8746 |
%} |
|
8747 |
ins_pipe(pipe_class_dummy); |
|
8748 |
%} |
|
8749 |
||
8750 |
instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
|
|
8751 |
match(Set dst (MinI src1 src2)); |
|
8752 |
effect(KILL cr); |
|
8753 |
predicate(VM_Version::has_LoadStoreConditional()); |
|
8754 |
ins_cost(3 * DEFAULT_COST); |
|
8755 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8756 |
format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %}
|
|
8757 |
ins_encode %{
|
|
8758 |
Register Rdst = $dst$$Register; |
|
8759 |
Register Rsrc1 = $src1$$Register; |
|
8760 |
int Isrc2 = $src2$$constant; |
|
8761 |
||
8762 |
if (Rdst == Rsrc1) {
|
|
8763 |
__ load_const_optimized(Z_R0_scratch, Isrc2); |
|
8764 |
__ z_chi(Rsrc1, Isrc2); |
|
8765 |
__ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow); |
|
8766 |
} else {
|
|
8767 |
__ load_const_optimized(Rdst, Isrc2); |
|
8768 |
__ z_chi(Rsrc1, Isrc2); |
|
8769 |
__ z_locr(Rdst, Rsrc1, Assembler::bcondLow); |
|
8770 |
} |
|
8771 |
%} |
|
8772 |
ins_pipe(pipe_class_dummy); |
|
8773 |
%} |
|
8774 |
||
8775 |
instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
|
|
8776 |
match(Set dst (MinI src1 src2)); |
|
8777 |
effect(KILL cr); |
|
8778 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
8779 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8780 |
format %{ "MinI $dst $src1,$src2\t MinI const16" %}
|
|
8781 |
ins_encode %{
|
|
8782 |
Label done; |
|
8783 |
if ($dst$$Register != $src1$$Register) {
|
|
8784 |
__ z_lgfr($dst$$Register, $src1$$Register); |
|
8785 |
} |
|
8786 |
__ z_chi($src1$$Register, $src2$$constant); |
|
8787 |
__ z_brl(done); |
|
8788 |
__ z_lghi($dst$$Register, $src2$$constant); |
|
8789 |
__ bind(done); |
|
8790 |
%} |
|
8791 |
ins_pipe(pipe_class_dummy); |
|
8792 |
%} |
|
8793 |
||
8794 |
instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
|
|
8795 |
match(Set dst (MinI src1 src2)); |
|
8796 |
effect(KILL cr); |
|
8797 |
predicate(VM_Version::has_CompareBranch()); |
|
8798 |
ins_cost(DEFAULT_COST + BRANCH_COST); |
|
8799 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8800 |
format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %}
|
|
8801 |
ins_encode %{
|
|
8802 |
Label done; |
|
8803 |
if ($dst$$Register != $src1$$Register) {
|
|
8804 |
__ z_lgfr($dst$$Register, $src1$$Register); |
|
8805 |
} |
|
8806 |
__ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done); |
|
8807 |
__ z_lghi($dst$$Register, $src2$$constant); |
|
8808 |
__ bind(done); |
|
8809 |
%} |
|
8810 |
ins_pipe(pipe_class_dummy); |
|
8811 |
%} |
|
8812 |
||
8813 |
// Max Register with Register |
|
8814 |
instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
|
|
8815 |
match(Set dst (MaxI src1 src2)); |
|
8816 |
effect(KILL cr); |
|
8817 |
predicate(VM_Version::has_LoadStoreConditional()); |
|
8818 |
ins_cost(3 * DEFAULT_COST); |
|
8819 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8820 |
format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %}
|
|
8821 |
ins_encode %{
|
|
8822 |
Register Rdst = $dst$$Register; |
|
8823 |
Register Rsrc1 = $src1$$Register; |
|
8824 |
Register Rsrc2 = $src2$$Register; |
|
8825 |
||
8826 |
if (Rsrc1 == Rsrc2) {
|
|
8827 |
if (Rdst != Rsrc1) {
|
|
8828 |
__ z_lgfr(Rdst, Rsrc1); |
|
8829 |
} |
|
8830 |
} else if (Rdst == Rsrc1) { // Rdst preset with src1.
|
|
8831 |
__ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotHigh. |
|
8832 |
__ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh); |
|
8833 |
} else if (Rdst == Rsrc2) { // Rdst preset with src2.
|
|
8834 |
__ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotHigh. |
|
8835 |
__ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh); |
|
8836 |
} else { // Rdst is disjoint from operands, move in either case.
|
|
8837 |
__ z_cr(Rsrc1, Rsrc2); |
|
8838 |
__ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh); |
|
8839 |
__ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); |
|
8840 |
} |
|
8841 |
%} |
|
8842 |
ins_pipe(pipe_class_dummy); |
|
8843 |
%} |
|
8844 |
||
8845 |
// Max Register with Register |
|
8846 |
instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
|
|
8847 |
match(Set dst (MaxI src1 src2)); |
|
8848 |
effect(KILL cr); |
|
8849 |
predicate(VM_Version::has_CompareBranch()); |
|
8850 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
8851 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8852 |
format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %}
|
|
8853 |
ins_encode %{
|
|
8854 |
Register Rdst = $dst$$Register; |
|
8855 |
Register Rsrc1 = $src1$$Register; |
|
8856 |
Register Rsrc2 = $src2$$Register; |
|
8857 |
Label done; |
|
8858 |
||
8859 |
if (Rsrc1 == Rsrc2) {
|
|
8860 |
if (Rdst != Rsrc1) {
|
|
8861 |
__ z_lgfr(Rdst, Rsrc1); |
|
8862 |
} |
|
8863 |
} else if (Rdst == Rsrc1) {
|
|
8864 |
__ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done); |
|
8865 |
__ z_lgfr(Rdst, Rsrc2); |
|
8866 |
} else if (Rdst == Rsrc2) {
|
|
8867 |
__ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done); |
|
8868 |
__ z_lgfr(Rdst, Rsrc1); |
|
8869 |
} else {
|
|
8870 |
__ z_lgfr(Rdst, Rsrc1); |
|
8871 |
__ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done); |
|
8872 |
__ z_lgfr(Rdst, Rsrc2); |
|
8873 |
} |
|
8874 |
__ bind(done); |
|
8875 |
%} |
|
8876 |
ins_pipe(pipe_class_dummy); |
|
8877 |
%} |
|
8878 |
||
8879 |
instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
|
|
8880 |
match(Set dst (MaxI src1 src2)); |
|
8881 |
effect(KILL cr); |
|
8882 |
predicate(!VM_Version::has_CompareBranch()); |
|
8883 |
ins_cost(3 * DEFAULT_COST + BRANCH_COST); |
|
8884 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8885 |
format %{ "MaxI $dst $src1,$src2\t MaxI" %}
|
|
8886 |
ins_encode %{
|
|
8887 |
Register Rdst = $dst$$Register; |
|
8888 |
Register Rsrc1 = $src1$$Register; |
|
8889 |
Register Rsrc2 = $src2$$Register; |
|
8890 |
Label done; |
|
8891 |
||
8892 |
if (Rsrc1 == Rsrc2) {
|
|
8893 |
if (Rdst != Rsrc1) {
|
|
8894 |
__ z_lgfr(Rdst, Rsrc1); |
|
8895 |
} |
|
8896 |
} else if (Rdst == Rsrc1) {
|
|
8897 |
__ z_cr(Rsrc1, Rsrc2); |
|
8898 |
__ z_brh(done); |
|
8899 |
__ z_lgfr(Rdst, Rsrc2); |
|
8900 |
} else if (Rdst == Rsrc2) {
|
|
8901 |
__ z_cr(Rsrc2, Rsrc1); |
|
8902 |
__ z_brh(done); |
|
8903 |
__ z_lgfr(Rdst, Rsrc1); |
|
8904 |
} else {
|
|
8905 |
__ z_lgfr(Rdst, Rsrc1); |
|
8906 |
__ z_cr(Rsrc1, Rsrc2); |
|
8907 |
__ z_brh(done); |
|
8908 |
__ z_lgfr(Rdst, Rsrc2); |
|
8909 |
} |
|
8910 |
||
8911 |
__ bind(done); |
|
8912 |
%} |
|
8913 |
||
8914 |
ins_pipe(pipe_class_dummy); |
|
8915 |
%} |
|
8916 |
||
8917 |
instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
|
|
8918 |
match(Set dst (MaxI src1 src2)); |
|
8919 |
effect(KILL cr); |
|
8920 |
predicate(VM_Version::has_LoadStoreConditional()); |
|
8921 |
ins_cost(3 * DEFAULT_COST); |
|
8922 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8923 |
format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %}
|
|
8924 |
ins_encode %{
|
|
8925 |
Register Rdst = $dst$$Register; |
|
8926 |
Register Rsrc1 = $src1$$Register; |
|
8927 |
int Isrc2 = $src2$$constant; |
|
8928 |
||
8929 |
if (Rdst == Rsrc1) {
|
|
8930 |
__ load_const_optimized(Z_R0_scratch, Isrc2); |
|
8931 |
__ z_cfi(Rsrc1, Isrc2); |
|
8932 |
__ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh); |
|
8933 |
} else {
|
|
8934 |
__ load_const_optimized(Rdst, Isrc2); |
|
8935 |
__ z_cfi(Rsrc1, Isrc2); |
|
8936 |
__ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); |
|
8937 |
} |
|
8938 |
%} |
|
8939 |
ins_pipe(pipe_class_dummy); |
|
8940 |
%} |
|
8941 |
||
8942 |
instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
|
|
8943 |
match(Set dst (MaxI src1 src2)); |
|
8944 |
effect(KILL cr); |
|
8945 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
8946 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8947 |
format %{ "MaxI $dst $src1,$src2\t MaxI const32" %}
|
|
8948 |
ins_encode %{
|
|
8949 |
Label done; |
|
8950 |
if ($dst$$Register != $src1$$Register) {
|
|
8951 |
__ z_lgfr($dst$$Register, $src1$$Register); |
|
8952 |
} |
|
8953 |
__ z_cfi($src1$$Register, $src2$$constant); |
|
8954 |
__ z_brh(done); |
|
8955 |
__ z_lgfi($dst$$Register, $src2$$constant); |
|
8956 |
__ bind(done); |
|
8957 |
%} |
|
8958 |
ins_pipe(pipe_class_dummy); |
|
8959 |
%} |
|
8960 |
||
8961 |
instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
|
|
8962 |
match(Set dst (MaxI src1 src2)); |
|
8963 |
effect(KILL cr); |
|
8964 |
predicate(VM_Version::has_LoadStoreConditional()); |
|
8965 |
ins_cost(3 * DEFAULT_COST); |
|
8966 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8967 |
format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %}
|
|
8968 |
ins_encode %{
|
|
8969 |
Register Rdst = $dst$$Register; |
|
8970 |
Register Rsrc1 = $src1$$Register; |
|
8971 |
int Isrc2 = $src2$$constant; |
|
8972 |
if (Rdst == Rsrc1) {
|
|
8973 |
__ load_const_optimized(Z_R0_scratch, Isrc2); |
|
8974 |
__ z_chi(Rsrc1, Isrc2); |
|
8975 |
__ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh); |
|
8976 |
} else {
|
|
8977 |
__ load_const_optimized(Rdst, Isrc2); |
|
8978 |
__ z_chi(Rsrc1, Isrc2); |
|
8979 |
__ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); |
|
8980 |
} |
|
8981 |
%} |
|
8982 |
ins_pipe(pipe_class_dummy); |
|
8983 |
%} |
|
8984 |
||
8985 |
instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
|
|
8986 |
match(Set dst (MaxI src1 src2)); |
|
8987 |
effect(KILL cr); |
|
8988 |
ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
|
8989 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
8990 |
format %{ "MaxI $dst $src1,$src2\t MaxI const16" %}
|
|
8991 |
ins_encode %{
|
|
8992 |
Label done; |
|
8993 |
if ($dst$$Register != $src1$$Register) {
|
|
8994 |
__ z_lgfr($dst$$Register, $src1$$Register); |
|
8995 |
} |
|
8996 |
__ z_chi($src1$$Register, $src2$$constant); |
|
8997 |
__ z_brh(done); |
|
8998 |
__ z_lghi($dst$$Register, $src2$$constant); |
|
8999 |
__ bind(done); |
|
9000 |
%} |
|
9001 |
ins_pipe(pipe_class_dummy); |
|
9002 |
%} |
|
9003 |
||
9004 |
instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
|
|
9005 |
match(Set dst (MaxI src1 src2)); |
|
9006 |
effect(KILL cr); |
|
9007 |
predicate(VM_Version::has_CompareBranch()); |
|
9008 |
ins_cost(DEFAULT_COST + BRANCH_COST); |
|
9009 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
9010 |
format %{ "MaxI $dst $src1,$src2\t MaxI const8" %}
|
|
9011 |
ins_encode %{
|
|
9012 |
Label done; |
|
9013 |
if ($dst$$Register != $src1$$Register) {
|
|
9014 |
__ z_lgfr($dst$$Register, $src1$$Register); |
|
9015 |
} |
|
9016 |
__ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done); |
|
9017 |
__ z_lghi($dst$$Register, $src2$$constant); |
|
9018 |
__ bind(done); |
|
9019 |
%} |
|
9020 |
ins_pipe(pipe_class_dummy); |
|
9021 |
%} |
|
9022 |
||
9023 |
//----------Abs--------------------------------------------------------------- |
|
9024 |
||
9025 |
instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
|
|
9026 |
match(Set dst (AbsI src)); |
|
9027 |
effect(KILL cr); |
|
9028 |
ins_cost(DEFAULT_COST_LOW); |
|
9029 |
// TODO: s390 port size(FIXED_SIZE); |
|
9030 |
format %{ "LPR $dst, $src" %}
|
|
9031 |
opcode(LPR_ZOPC); |
|
9032 |
ins_encode(z_rrform(dst, src)); |
|
9033 |
ins_pipe(pipe_class_dummy); |
|
9034 |
%} |
|
9035 |
||
9036 |
instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
|
|
9037 |
match(Set dst (SubI zero (AbsI src))); |
|
9038 |
effect(KILL cr); |
|
9039 |
ins_cost(DEFAULT_COST_LOW); |
|
9040 |
// TODO: s390 port size(FIXED_SIZE); |
|
9041 |
format %{ "LNR $dst, $src" %}
|
|
9042 |
opcode(LNR_ZOPC); |
|
9043 |
ins_encode(z_rrform(dst, src)); |
|
9044 |
ins_pipe(pipe_class_dummy); |
|
9045 |
%} |
|
9046 |
||
9047 |
//----------Float Compares---------------------------------------------------- |
|
9048 |
||
9049 |
// Compare floating, generate condition code. |
|
9050 |
instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{
|
|
9051 |
match(Set cr (CmpF src1 src2)); |
|
9052 |
ins_cost(ALU_REG_COST); |
|
9053 |
size(4); |
|
9054 |
format %{ "FCMPcc $src1,$src2\t # float" %}
|
|
9055 |
ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %}
|
|
9056 |
ins_pipe(pipe_class_dummy); |
|
9057 |
%} |
|
9058 |
||
9059 |
instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{
|
|
9060 |
match(Set cr (CmpD src1 src2)); |
|
9061 |
ins_cost(ALU_REG_COST); |
|
9062 |
size(4); |
|
9063 |
format %{ "FCMPcc $src1,$src2 \t # double" %}
|
|
9064 |
ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %}
|
|
9065 |
ins_pipe(pipe_class_dummy); |
|
9066 |
%} |
|
9067 |
||
9068 |
instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{
|
|
9069 |
match(Set cr (CmpF src1 (LoadF src2))); |
|
9070 |
ins_cost(ALU_MEMORY_COST); |
|
9071 |
size(6); |
|
9072 |
format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %}
|
|
9073 |
opcode(CEB_ZOPC); |
|
9074 |
ins_encode(z_form_rt_memFP(src1, src2)); |
|
9075 |
ins_pipe(pipe_class_dummy); |
|
9076 |
%} |
|
9077 |
||
9078 |
instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{
|
|
9079 |
match(Set cr (CmpD src1 (LoadD src2))); |
|
9080 |
ins_cost(ALU_MEMORY_COST); |
|
9081 |
size(6); |
|
9082 |
format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %}
|
|
9083 |
opcode(CDB_ZOPC); |
|
9084 |
ins_encode(z_form_rt_memFP(src1, src2)); |
|
9085 |
ins_pipe(pipe_class_dummy); |
|
9086 |
%} |
|
9087 |
||
9088 |
// Compare floating, generate condition code |
|
9089 |
instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{
|
|
9090 |
match(Set cr (CmpF src1 src2)); |
|
9091 |
ins_cost(DEFAULT_COST); |
|
9092 |
size(4); |
|
9093 |
format %{ "LTEBR $src1,$src1\t # float" %}
|
|
9094 |
opcode(LTEBR_ZOPC); |
|
9095 |
ins_encode(z_rreform(src1, src1)); |
|
9096 |
ins_pipe(pipe_class_dummy); |
|
9097 |
%} |
|
9098 |
||
9099 |
instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{
|
|
9100 |
match(Set cr (CmpD src1 src2)); |
|
9101 |
ins_cost(DEFAULT_COST); |
|
9102 |
size(4); |
|
9103 |
format %{ "LTDBR $src1,$src1 \t # double" %}
|
|
9104 |
opcode(LTDBR_ZOPC); |
|
9105 |
ins_encode(z_rreform(src1, src1)); |
|
9106 |
ins_pipe(pipe_class_dummy); |
|
9107 |
%} |
|
9108 |
||
9109 |
// Compare floating, generate -1,0,1 |
|
9110 |
instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{
|
|
9111 |
match(Set dst (CmpF3 src1 src2)); |
|
9112 |
effect(KILL cr); |
|
9113 |
ins_cost(DEFAULT_COST * 5 + BRANCH_COST); |
|
9114 |
size(24); |
|
9115 |
format %{ "CmpF3 $dst,$src1,$src2" %}
|
|
9116 |
ins_encode %{
|
|
9117 |
// compare registers |
|
9118 |
__ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); |
|
9119 |
// Convert condition code into -1,0,1, where |
|
9120 |
// -1 means unordered or less |
|
9121 |
// 0 means equal |
|
9122 |
// 1 means greater. |
|
9123 |
if (VM_Version::has_LoadStoreConditional()) {
|
|
9124 |
Register one = Z_R0_scratch; |
|
9125 |
Register minus_one = Z_R1_scratch; |
|
9126 |
__ z_lghi(minus_one, -1); |
|
9127 |
__ z_lghi(one, 1); |
|
9128 |
__ z_lghi( $dst$$Register, 0); |
|
9129 |
__ z_locgr($dst$$Register, one, Assembler::bcondHigh); |
|
9130 |
__ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered); |
|
9131 |
} else {
|
|
9132 |
Label done; |
|
9133 |
__ clear_reg($dst$$Register, true, false); |
|
9134 |
__ z_bre(done); |
|
9135 |
__ z_lhi($dst$$Register, 1); |
|
9136 |
__ z_brh(done); |
|
9137 |
__ z_lhi($dst$$Register, -1); |
|
9138 |
__ bind(done); |
|
9139 |
} |
|
9140 |
%} |
|
9141 |
ins_pipe(pipe_class_dummy); |
|
9142 |
%} |
|
9143 |
||
9144 |
instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{
|
|
9145 |
match(Set dst (CmpD3 src1 src2)); |
|
9146 |
effect(KILL cr); |
|
9147 |
ins_cost(DEFAULT_COST * 5 + BRANCH_COST); |
|
9148 |
size(24); |
|
9149 |
format %{ "CmpD3 $dst,$src1,$src2" %}
|
|
9150 |
ins_encode %{
|
|
9151 |
// compare registers |
|
9152 |
__ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); |
|
9153 |
// Convert condition code into -1,0,1, where |
|
9154 |
// -1 means unordered or less |
|
9155 |
// 0 means equal |
|
9156 |
// 1 means greater. |
|
9157 |
if (VM_Version::has_LoadStoreConditional()) {
|
|
9158 |
Register one = Z_R0_scratch; |
|
9159 |
Register minus_one = Z_R1_scratch; |
|
9160 |
__ z_lghi(minus_one, -1); |
|
9161 |
__ z_lghi(one, 1); |
|
9162 |
__ z_lghi( $dst$$Register, 0); |
|
9163 |
__ z_locgr($dst$$Register, one, Assembler::bcondHigh); |
|
9164 |
__ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered); |
|
9165 |
} else {
|
|
9166 |
Label done; |
|
9167 |
// indicate unused result |
|
9168 |
(void) __ clear_reg($dst$$Register, true, false); |
|
9169 |
__ z_bre(done); |
|
9170 |
__ z_lhi($dst$$Register, 1); |
|
9171 |
__ z_brh(done); |
|
9172 |
__ z_lhi($dst$$Register, -1); |
|
9173 |
__ bind(done); |
|
9174 |
} |
|
9175 |
%} |
|
9176 |
ins_pipe(pipe_class_dummy); |
|
9177 |
%} |
|
9178 |
||
9179 |
//----------Branches--------------------------------------------------------- |
|
9180 |
// Jump |
|
9181 |
||
9182 |
// Direct Branch. |
|
9183 |
instruct branch(label labl) %{
|
|
9184 |
match(Goto); |
|
9185 |
effect(USE labl); |
|
9186 |
ins_cost(BRANCH_COST); |
|
9187 |
size(4); |
|
9188 |
format %{ "BRU $labl" %}
|
|
9189 |
ins_encode(z_enc_bru(labl)); |
|
9190 |
ins_pipe(pipe_class_dummy); |
|
9191 |
// If set to 1 this indicates that the current instruction is a |
|
9192 |
// short variant of a long branch. This avoids using this |
|
9193 |
// instruction in first-pass matching. It will then only be used in |
|
9194 |
// the `Shorten_branches' pass. |
|
9195 |
ins_short_branch(1); |
|
9196 |
%} |
|
9197 |
||
9198 |
// Direct Branch. |
|
9199 |
instruct branchFar(label labl) %{
|
|
9200 |
match(Goto); |
|
9201 |
effect(USE labl); |
|
9202 |
ins_cost(BRANCH_COST); |
|
9203 |
size(6); |
|
9204 |
format %{ "BRUL $labl" %}
|
|
9205 |
ins_encode(z_enc_brul(labl)); |
|
9206 |
ins_pipe(pipe_class_dummy); |
|
9207 |
// This is not a short variant of a branch, but the long variant. |
|
9208 |
ins_short_branch(0); |
|
9209 |
%} |
|
9210 |
||
9211 |
// Conditional Near Branch |
|
9212 |
instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{
|
|
9213 |
// Same match rule as `branchConFar'. |
|
9214 |
match(If cmp cr); |
|
9215 |
effect(USE lbl); |
|
9216 |
ins_cost(BRANCH_COST); |
|
9217 |
size(4); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
9218 |
format %{ "branch_con_short,$cmp $lbl" %}
|
| 42065 | 9219 |
ins_encode(z_enc_branch_con_short(cmp, lbl)); |
9220 |
ins_pipe(pipe_class_dummy); |
|
9221 |
// If set to 1 this indicates that the current instruction is a |
|
9222 |
// short variant of a long branch. This avoids using this |
|
9223 |
// instruction in first-pass matching. It will then only be used in |
|
9224 |
// the `Shorten_branches' pass. |
|
9225 |
ins_short_branch(1); |
|
9226 |
%} |
|
9227 |
||
9228 |
// This is for cases when the z/Architecture conditional branch instruction |
|
9229 |
// does not reach far enough. So we emit a far branch here, which is |
|
9230 |
// more expensive. |
|
9231 |
// |
|
9232 |
// Conditional Far Branch |
|
9233 |
instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{
|
|
9234 |
// Same match rule as `branchCon'. |
|
9235 |
match(If cmp cr); |
|
9236 |
effect(USE cr, USE lbl); |
|
9237 |
// Make more expensive to prefer compare_and_branch over separate instructions. |
|
9238 |
ins_cost(2 * BRANCH_COST); |
|
9239 |
size(6); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
9240 |
format %{ "branch_con_far,$cmp $lbl" %}
|
| 42065 | 9241 |
ins_encode(z_enc_branch_con_far(cmp, lbl)); |
9242 |
ins_pipe(pipe_class_dummy); |
|
9243 |
// This is not a short variant of a branch, but the long variant.. |
|
9244 |
ins_short_branch(0); |
|
9245 |
%} |
|
9246 |
||
9247 |
instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{
|
|
9248 |
match(CountedLoopEnd cmp cr); |
|
9249 |
effect(USE labl); |
|
9250 |
ins_cost(BRANCH_COST); |
|
9251 |
size(4); |
|
9252 |
format %{ "branch_con_short,$cmp $labl\t # counted loop end" %}
|
|
9253 |
ins_encode(z_enc_branch_con_short(cmp, labl)); |
|
9254 |
ins_pipe(pipe_class_dummy); |
|
9255 |
// If set to 1 this indicates that the current instruction is a |
|
9256 |
// short variant of a long branch. This avoids using this |
|
9257 |
// instruction in first-pass matching. It will then only be used in |
|
9258 |
// the `Shorten_branches' pass. |
|
9259 |
ins_short_branch(1); |
|
9260 |
%} |
|
9261 |
||
9262 |
instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{
|
|
9263 |
match(CountedLoopEnd cmp cr); |
|
9264 |
effect(USE labl); |
|
9265 |
ins_cost(BRANCH_COST); |
|
9266 |
size(6); |
|
9267 |
format %{ "branch_con_far,$cmp $labl\t # counted loop end" %}
|
|
9268 |
ins_encode(z_enc_branch_con_far(cmp, labl)); |
|
9269 |
ins_pipe(pipe_class_dummy); |
|
9270 |
// This is not a short variant of a branch, but the long variant. |
|
9271 |
ins_short_branch(0); |
|
9272 |
%} |
|
9273 |
||
9274 |
//----------Compare and Branch (short distance)------------------------------ |
|
9275 |
||
9276 |
// INT REG operands for loop counter processing. |
|
9277 |
instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
|
|
9278 |
match(CountedLoopEnd boolnode (CmpI src1 src2)); |
|
9279 |
effect(USE labl, KILL cr); |
|
9280 |
predicate(VM_Version::has_CompareBranch()); |
|
9281 |
ins_cost(BRANCH_COST); |
|
9282 |
// TODO: s390 port size(FIXED_SIZE); |
|
9283 |
format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
|
|
9284 |
opcode(CRJ_ZOPC); |
|
9285 |
ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); |
|
9286 |
ins_pipe(pipe_class_dummy); |
|
9287 |
ins_short_branch(1); |
|
9288 |
%} |
|
9289 |
||
9290 |
// INT REG operands. |
|
9291 |
instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
|
|
9292 |
match(If boolnode (CmpI src1 src2)); |
|
9293 |
effect(USE labl, KILL cr); |
|
9294 |
predicate(VM_Version::has_CompareBranch()); |
|
9295 |
ins_cost(BRANCH_COST); |
|
9296 |
// TODO: s390 port size(FIXED_SIZE); |
|
9297 |
format %{ "CRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
|
|
9298 |
opcode(CRJ_ZOPC); |
|
9299 |
ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); |
|
9300 |
ins_pipe(pipe_class_dummy); |
|
9301 |
ins_short_branch(1); |
|
9302 |
%} |
|
9303 |
||
9304 |
// Unsigned INT REG operands |
|
9305 |
instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
|
|
9306 |
match(If boolnode (CmpU src1 src2)); |
|
9307 |
effect(USE labl, KILL cr); |
|
9308 |
predicate(VM_Version::has_CompareBranch()); |
|
9309 |
ins_cost(BRANCH_COST); |
|
9310 |
// TODO: s390 port size(FIXED_SIZE); |
|
9311 |
format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
|
|
9312 |
opcode(CLRJ_ZOPC); |
|
9313 |
ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); |
|
9314 |
ins_pipe(pipe_class_dummy); |
|
9315 |
ins_short_branch(1); |
|
9316 |
%} |
|
9317 |
||
9318 |
// LONG REG operands |
|
9319 |
instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
|
|
9320 |
match(If boolnode (CmpL src1 src2)); |
|
9321 |
effect(USE labl, KILL cr); |
|
9322 |
predicate(VM_Version::has_CompareBranch()); |
|
9323 |
ins_cost(BRANCH_COST); |
|
9324 |
// TODO: s390 port size(FIXED_SIZE); |
|
9325 |
format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
|
|
9326 |
opcode(CGRJ_ZOPC); |
|
9327 |
ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); |
|
9328 |
ins_pipe(pipe_class_dummy); |
|
9329 |
ins_short_branch(1); |
|
9330 |
%} |
|
9331 |
||
9332 |
// PTR REG operands |
|
9333 |
||
9334 |
// Separate rules for regular and narrow oops. ADLC can't recognize |
|
9335 |
// rules with polymorphic operands to be sisters -> shorten_branches |
|
9336 |
// will not shorten. |
|
9337 |
||
9338 |
instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
|
|
9339 |
match(If boolnode (CmpP src1 src2)); |
|
9340 |
effect(USE labl, KILL cr); |
|
9341 |
predicate(VM_Version::has_CompareBranch()); |
|
9342 |
ins_cost(BRANCH_COST); |
|
9343 |
// TODO: s390 port size(FIXED_SIZE); |
|
9344 |
format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
|
|
9345 |
opcode(CLGRJ_ZOPC); |
|
9346 |
ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); |
|
9347 |
ins_pipe(pipe_class_dummy); |
|
9348 |
ins_short_branch(1); |
|
9349 |
%} |
|
9350 |
||
9351 |
instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
|
|
9352 |
match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); |
|
9353 |
effect(USE labl, KILL cr); |
|
9354 |
predicate(VM_Version::has_CompareBranch()); |
|
9355 |
ins_cost(BRANCH_COST); |
|
9356 |
// TODO: s390 port size(FIXED_SIZE); |
|
9357 |
format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
|
|
9358 |
opcode(CLGRJ_ZOPC); |
|
9359 |
ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); |
|
9360 |
ins_pipe(pipe_class_dummy); |
|
9361 |
ins_short_branch(1); |
|
9362 |
%} |
|
9363 |
||
9364 |
// INT REG/IMM operands for loop counter processing |
|
9365 |
instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
|
|
9366 |
match(CountedLoopEnd boolnode (CmpI src1 src2)); |
|
9367 |
effect(USE labl, KILL cr); |
|
9368 |
predicate(VM_Version::has_CompareBranch()); |
|
9369 |
ins_cost(BRANCH_COST); |
|
9370 |
// TODO: s390 port size(FIXED_SIZE); |
|
9371 |
format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
|
|
9372 |
opcode(CIJ_ZOPC); |
|
9373 |
ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); |
|
9374 |
ins_pipe(pipe_class_dummy); |
|
9375 |
ins_short_branch(1); |
|
9376 |
%} |
|
9377 |
||
9378 |
// INT REG/IMM operands |
|
9379 |
instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
|
|
9380 |
match(If boolnode (CmpI src1 src2)); |
|
9381 |
effect(USE labl, KILL cr); |
|
9382 |
predicate(VM_Version::has_CompareBranch()); |
|
9383 |
ins_cost(BRANCH_COST); |
|
9384 |
// TODO: s390 port size(FIXED_SIZE); |
|
9385 |
format %{ "CIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
|
|
9386 |
opcode(CIJ_ZOPC); |
|
9387 |
ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); |
|
9388 |
ins_pipe(pipe_class_dummy); |
|
9389 |
ins_short_branch(1); |
|
9390 |
%} |
|
9391 |
||
9392 |
// INT REG/IMM operands |
|
9393 |
instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
|
|
9394 |
match(If boolnode (CmpU src1 src2)); |
|
9395 |
effect(USE labl, KILL cr); |
|
9396 |
predicate(VM_Version::has_CompareBranch()); |
|
9397 |
ins_cost(BRANCH_COST); |
|
9398 |
// TODO: s390 port size(FIXED_SIZE); |
|
9399 |
format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
|
|
9400 |
opcode(CLIJ_ZOPC); |
|
9401 |
ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); |
|
9402 |
ins_pipe(pipe_class_dummy); |
|
9403 |
ins_short_branch(1); |
|
9404 |
%} |
|
9405 |
||
9406 |
// LONG REG/IMM operands |
|
9407 |
instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
|
|
9408 |
match(If boolnode (CmpL src1 src2)); |
|
9409 |
effect(USE labl, KILL cr); |
|
9410 |
predicate(VM_Version::has_CompareBranch()); |
|
9411 |
ins_cost(BRANCH_COST); |
|
9412 |
// TODO: s390 port size(FIXED_SIZE); |
|
9413 |
format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
|
|
9414 |
opcode(CGIJ_ZOPC); |
|
9415 |
ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); |
|
9416 |
ins_pipe(pipe_class_dummy); |
|
9417 |
ins_short_branch(1); |
|
9418 |
%} |
|
9419 |
||
9420 |
// PTR REG-imm operands |
|
9421 |
||
9422 |
// Separate rules for regular and narrow oops. ADLC can't recognize |
|
9423 |
// rules with polymorphic operands to be sisters -> shorten_branches |
|
9424 |
// will not shorten. |
|
9425 |
||
9426 |
instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
|
|
9427 |
match(If boolnode (CmpP src1 src2)); |
|
9428 |
effect(USE labl, KILL cr); |
|
9429 |
predicate(VM_Version::has_CompareBranch()); |
|
9430 |
ins_cost(BRANCH_COST); |
|
9431 |
// TODO: s390 port size(FIXED_SIZE); |
|
9432 |
format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
|
|
9433 |
opcode(CLGIJ_ZOPC); |
|
9434 |
ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); |
|
9435 |
ins_pipe(pipe_class_dummy); |
|
9436 |
ins_short_branch(1); |
|
9437 |
%} |
|
9438 |
||
9439 |
// Compare against zero only, do not mix N and P oops (encode/decode required). |
|
9440 |
instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
|
|
9441 |
match(If boolnode (CmpP (DecodeN src1) src2)); |
|
9442 |
effect(USE labl, KILL cr); |
|
9443 |
predicate(VM_Version::has_CompareBranch()); |
|
9444 |
ins_cost(BRANCH_COST); |
|
9445 |
// TODO: s390 port size(FIXED_SIZE); |
|
9446 |
format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
|
|
9447 |
opcode(CLGIJ_ZOPC); |
|
9448 |
ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); |
|
9449 |
ins_pipe(pipe_class_dummy); |
|
9450 |
ins_short_branch(1); |
|
9451 |
%} |
|
9452 |
||
9453 |
instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
|
|
9454 |
match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); |
|
9455 |
effect(USE labl, KILL cr); |
|
9456 |
predicate(VM_Version::has_CompareBranch()); |
|
9457 |
ins_cost(BRANCH_COST); |
|
9458 |
// TODO: s390 port size(FIXED_SIZE); |
|
9459 |
format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
|
|
9460 |
opcode(CLGIJ_ZOPC); |
|
9461 |
ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); |
|
9462 |
ins_pipe(pipe_class_dummy); |
|
9463 |
ins_short_branch(1); |
|
9464 |
%} |
|
9465 |
||
9466 |
||
9467 |
//----------Compare and Branch (far distance)------------------------------ |
|
9468 |
||
9469 |
// INT REG operands for loop counter processing |
|
9470 |
instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
|
|
9471 |
match(CountedLoopEnd boolnode (CmpI src1 src2)); |
|
9472 |
effect(USE labl, KILL cr); |
|
9473 |
predicate(VM_Version::has_CompareBranch()); |
|
9474 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9475 |
// TODO: s390 port size(FIXED_SIZE); |
|
9476 |
format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
|
|
9477 |
opcode(CR_ZOPC, BRCL_ZOPC); |
|
9478 |
ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); |
|
9479 |
ins_pipe(pipe_class_dummy); |
|
9480 |
ins_short_branch(0); |
|
9481 |
%} |
|
9482 |
||
9483 |
// INT REG operands |
|
9484 |
instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
|
|
9485 |
match(If boolnode (CmpI src1 src2)); |
|
9486 |
effect(USE labl, KILL cr); |
|
9487 |
predicate(VM_Version::has_CompareBranch()); |
|
9488 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9489 |
// TODO: s390 port size(FIXED_SIZE); |
|
9490 |
format %{ "CRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
|
|
9491 |
opcode(CR_ZOPC, BRCL_ZOPC); |
|
9492 |
ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); |
|
9493 |
ins_pipe(pipe_class_dummy); |
|
9494 |
ins_short_branch(0); |
|
9495 |
%} |
|
9496 |
||
9497 |
// INT REG operands |
|
9498 |
instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
|
|
9499 |
match(If boolnode (CmpU src1 src2)); |
|
9500 |
effect(USE labl, KILL cr); |
|
9501 |
predicate(VM_Version::has_CompareBranch()); |
|
9502 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9503 |
// TODO: s390 port size(FIXED_SIZE); |
|
9504 |
format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
|
|
9505 |
opcode(CLR_ZOPC, BRCL_ZOPC); |
|
9506 |
ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); |
|
9507 |
ins_pipe(pipe_class_dummy); |
|
9508 |
ins_short_branch(0); |
|
9509 |
%} |
|
9510 |
||
9511 |
// LONG REG operands |
|
9512 |
instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
|
|
9513 |
match(If boolnode (CmpL src1 src2)); |
|
9514 |
effect(USE labl, KILL cr); |
|
9515 |
predicate(VM_Version::has_CompareBranch()); |
|
9516 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9517 |
// TODO: s390 port size(FIXED_SIZE); |
|
9518 |
format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
|
|
9519 |
opcode(CGR_ZOPC, BRCL_ZOPC); |
|
9520 |
ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); |
|
9521 |
ins_pipe(pipe_class_dummy); |
|
9522 |
ins_short_branch(0); |
|
9523 |
%} |
|
9524 |
||
9525 |
// PTR REG operands |
|
9526 |
||
9527 |
// Separate rules for regular and narrow oops. ADLC can't recognize |
|
9528 |
// rules with polymorphic operands to be sisters -> shorten_branches |
|
9529 |
// will not shorten. |
|
9530 |
||
9531 |
instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
|
|
9532 |
match(If boolnode (CmpP src1 src2)); |
|
9533 |
effect(USE labl, KILL cr); |
|
9534 |
predicate(VM_Version::has_CompareBranch()); |
|
9535 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9536 |
// TODO: s390 port size(FIXED_SIZE); |
|
9537 |
format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
|
|
9538 |
opcode(CLGR_ZOPC, BRCL_ZOPC); |
|
9539 |
ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); |
|
9540 |
ins_pipe(pipe_class_dummy); |
|
9541 |
ins_short_branch(0); |
|
9542 |
%} |
|
9543 |
||
9544 |
instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
|
|
9545 |
match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); |
|
9546 |
effect(USE labl, KILL cr); |
|
9547 |
predicate(VM_Version::has_CompareBranch()); |
|
9548 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9549 |
// TODO: s390 port size(FIXED_SIZE); |
|
9550 |
format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
|
|
9551 |
opcode(CLGR_ZOPC, BRCL_ZOPC); |
|
9552 |
ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); |
|
9553 |
ins_pipe(pipe_class_dummy); |
|
9554 |
ins_short_branch(0); |
|
9555 |
%} |
|
9556 |
||
9557 |
// INT REG/IMM operands for loop counter processing |
|
9558 |
instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
|
|
9559 |
match(CountedLoopEnd boolnode (CmpI src1 src2)); |
|
9560 |
effect(USE labl, KILL cr); |
|
9561 |
predicate(VM_Version::has_CompareBranch()); |
|
9562 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9563 |
// TODO: s390 port size(FIXED_SIZE); |
|
9564 |
format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
|
|
9565 |
opcode(CHI_ZOPC, BRCL_ZOPC); |
|
9566 |
ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); |
|
9567 |
ins_pipe(pipe_class_dummy); |
|
9568 |
ins_short_branch(0); |
|
9569 |
%} |
|
9570 |
||
9571 |
// INT REG/IMM operands |
|
9572 |
instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
|
|
9573 |
match(If boolnode (CmpI src1 src2)); |
|
9574 |
effect(USE labl, KILL cr); |
|
9575 |
predicate(VM_Version::has_CompareBranch()); |
|
9576 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9577 |
// TODO: s390 port size(FIXED_SIZE); |
|
9578 |
format %{ "CIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
|
|
9579 |
opcode(CHI_ZOPC, BRCL_ZOPC); |
|
9580 |
ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); |
|
9581 |
ins_pipe(pipe_class_dummy); |
|
9582 |
ins_short_branch(0); |
|
9583 |
%} |
|
9584 |
||
9585 |
// INT REG/IMM operands |
|
9586 |
instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
|
|
9587 |
match(If boolnode (CmpU src1 src2)); |
|
9588 |
effect(USE labl, KILL cr); |
|
9589 |
predicate(VM_Version::has_CompareBranch()); |
|
9590 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9591 |
// TODO: s390 port size(FIXED_SIZE); |
|
9592 |
format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
|
|
9593 |
opcode(CLFI_ZOPC, BRCL_ZOPC); |
|
9594 |
ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); |
|
9595 |
ins_pipe(pipe_class_dummy); |
|
9596 |
ins_short_branch(0); |
|
9597 |
%} |
|
9598 |
||
9599 |
// LONG REG/IMM operands |
|
9600 |
instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
|
|
9601 |
match(If boolnode (CmpL src1 src2)); |
|
9602 |
effect(USE labl, KILL cr); |
|
9603 |
predicate(VM_Version::has_CompareBranch()); |
|
9604 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9605 |
// TODO: s390 port size(FIXED_SIZE); |
|
9606 |
format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
|
|
9607 |
opcode(CGHI_ZOPC, BRCL_ZOPC); |
|
9608 |
ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); |
|
9609 |
ins_pipe(pipe_class_dummy); |
|
9610 |
ins_short_branch(0); |
|
9611 |
%} |
|
9612 |
||
9613 |
// PTR REG-imm operands |
|
9614 |
||
9615 |
// Separate rules for regular and narrow oops. ADLC can't recognize |
|
9616 |
// rules with polymorphic operands to be sisters -> shorten_branches |
|
9617 |
// will not shorten. |
|
9618 |
||
9619 |
instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
|
|
9620 |
match(If boolnode (CmpP src1 src2)); |
|
9621 |
effect(USE labl, KILL cr); |
|
9622 |
predicate(VM_Version::has_CompareBranch()); |
|
9623 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9624 |
// TODO: s390 port size(FIXED_SIZE); |
|
9625 |
format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
|
|
9626 |
opcode(CLGFI_ZOPC, BRCL_ZOPC); |
|
9627 |
ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); |
|
9628 |
ins_pipe(pipe_class_dummy); |
|
9629 |
ins_short_branch(0); |
|
9630 |
%} |
|
9631 |
||
9632 |
// Compare against zero only, do not mix N and P oops (encode/decode required). |
|
9633 |
instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
|
|
9634 |
match(If boolnode (CmpP (DecodeN src1) src2)); |
|
9635 |
effect(USE labl, KILL cr); |
|
9636 |
predicate(VM_Version::has_CompareBranch()); |
|
9637 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9638 |
// TODO: s390 port size(FIXED_SIZE); |
|
9639 |
format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
|
|
9640 |
opcode(CLGFI_ZOPC, BRCL_ZOPC); |
|
9641 |
ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); |
|
9642 |
ins_pipe(pipe_class_dummy); |
|
9643 |
ins_short_branch(0); |
|
9644 |
%} |
|
9645 |
||
9646 |
instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
|
|
9647 |
match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); |
|
9648 |
effect(USE labl, KILL cr); |
|
9649 |
predicate(VM_Version::has_CompareBranch()); |
|
9650 |
ins_cost(BRANCH_COST+DEFAULT_COST); |
|
9651 |
// TODO: s390 port size(FIXED_SIZE); |
|
9652 |
format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
|
|
9653 |
opcode(CLGFI_ZOPC, BRCL_ZOPC); |
|
9654 |
ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); |
|
9655 |
ins_pipe(pipe_class_dummy); |
|
9656 |
ins_short_branch(0); |
|
9657 |
%} |
|
9658 |
||
9659 |
// ============================================================================ |
|
9660 |
// Long Compare |
|
9661 |
||
9662 |
// Due to a shortcoming in the ADLC, it mixes up expressions like: |
|
9663 |
// (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the |
|
9664 |
// difference between 'Y' and '0L'. The tree-matches for the CmpI sections |
|
9665 |
// are collapsed internally in the ADLC's dfa-gen code. The match for |
|
9666 |
// (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the |
|
9667 |
// foo match ends up with the wrong leaf. One fix is to not match both |
|
9668 |
// reg-reg and reg-zero forms of long-compare. This is unfortunate because |
|
9669 |
// both forms beat the trinary form of long-compare and both are very useful |
|
9670 |
// on platforms which have few registers. |
|
9671 |
||
9672 |
// Manifest a CmpL3 result in an integer register. Very painful. |
|
9673 |
// This is the test to avoid. |
|
9674 |
instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{
|
|
9675 |
match(Set dst (CmpL3 src1 src2)); |
|
9676 |
effect(KILL cr); |
|
9677 |
ins_cost(DEFAULT_COST * 5 + BRANCH_COST); |
|
9678 |
size(24); |
|
9679 |
format %{ "CmpL3 $dst,$src1,$src2" %}
|
|
9680 |
ins_encode %{
|
|
9681 |
Label done; |
|
9682 |
// compare registers |
|
9683 |
__ z_cgr($src1$$Register, $src2$$Register); |
|
9684 |
// Convert condition code into -1,0,1, where |
|
9685 |
// -1 means less |
|
9686 |
// 0 means equal |
|
9687 |
// 1 means greater. |
|
9688 |
if (VM_Version::has_LoadStoreConditional()) {
|
|
9689 |
Register one = Z_R0_scratch; |
|
9690 |
Register minus_one = Z_R1_scratch; |
|
9691 |
__ z_lghi(minus_one, -1); |
|
9692 |
__ z_lghi(one, 1); |
|
9693 |
__ z_lghi( $dst$$Register, 0); |
|
9694 |
__ z_locgr($dst$$Register, one, Assembler::bcondHigh); |
|
9695 |
__ z_locgr($dst$$Register, minus_one, Assembler::bcondLow); |
|
9696 |
} else {
|
|
9697 |
__ clear_reg($dst$$Register, true, false); |
|
9698 |
__ z_bre(done); |
|
9699 |
__ z_lhi($dst$$Register, 1); |
|
9700 |
__ z_brh(done); |
|
9701 |
__ z_lhi($dst$$Register, -1); |
|
9702 |
} |
|
9703 |
__ bind(done); |
|
9704 |
%} |
|
9705 |
ins_pipe(pipe_class_dummy); |
|
9706 |
%} |
|
9707 |
||
9708 |
// ============================================================================ |
|
9709 |
// Safepoint Instruction |
|
9710 |
||
9711 |
instruct safePoint() %{
|
|
9712 |
match(SafePoint); |
|
9713 |
predicate(false); |
|
9714 |
// TODO: s390 port size(FIXED_SIZE); |
|
9715 |
format %{ "UNIMPLEMENTED Safepoint_ " %}
|
|
9716 |
ins_encode(enc_unimplemented()); |
|
9717 |
ins_pipe(pipe_class_dummy); |
|
9718 |
%} |
|
9719 |
||
9720 |
instruct safePoint_poll(iRegP poll, flagsReg cr) %{
|
|
9721 |
match(SafePoint poll); |
|
9722 |
effect(USE poll, KILL cr); // R0 is killed, too. |
|
9723 |
// TODO: s390 port size(FIXED_SIZE); |
|
9724 |
format %{ "TM #0[,$poll],#111\t # Safepoint: poll for GC" %}
|
|
9725 |
ins_encode %{
|
|
9726 |
// Mark the code position where the load from the safepoint |
|
9727 |
// polling page was emitted as relocInfo::poll_type. |
|
9728 |
__ relocate(relocInfo::poll_type); |
|
9729 |
__ load_from_polling_page($poll$$Register); |
|
9730 |
%} |
|
9731 |
ins_pipe(pipe_class_dummy); |
|
9732 |
%} |
|
9733 |
||
9734 |
// ============================================================================ |
|
9735 |
||
9736 |
// Call Instructions |
|
9737 |
||
9738 |
// Call Java Static Instruction |
|
9739 |
instruct CallStaticJavaDirect_dynTOC(method meth) %{
|
|
9740 |
match(CallStaticJava); |
|
9741 |
effect(USE meth); |
|
9742 |
ins_cost(CALL_COST); |
|
9743 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
9744 |
format %{ "CALL,static dynTOC $meth; ==> " %}
|
|
9745 |
ins_encode( z_enc_java_static_call(meth) ); |
|
9746 |
ins_pipe(pipe_class_dummy); |
|
9747 |
ins_alignment(2); |
|
9748 |
%} |
|
9749 |
||
9750 |
// Call Java Dynamic Instruction |
|
9751 |
instruct CallDynamicJavaDirect_dynTOC(method meth) %{
|
|
9752 |
match(CallDynamicJava); |
|
9753 |
effect(USE meth); |
|
9754 |
ins_cost(CALL_COST); |
|
9755 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
9756 |
format %{ "CALL,dynamic dynTOC $meth; ==> " %}
|
|
9757 |
ins_encode(z_enc_java_dynamic_call(meth)); |
|
9758 |
ins_pipe(pipe_class_dummy); |
|
9759 |
ins_alignment(2); |
|
9760 |
%} |
|
9761 |
||
9762 |
// Call Runtime Instruction |
|
9763 |
instruct CallRuntimeDirect(method meth) %{
|
|
9764 |
match(CallRuntime); |
|
9765 |
effect(USE meth); |
|
9766 |
ins_cost(CALL_COST); |
|
9767 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
9768 |
ins_num_consts(1); |
|
9769 |
ins_alignment(2); |
|
9770 |
format %{ "CALL,runtime" %}
|
|
9771 |
ins_encode( z_enc_java_to_runtime_call(meth) ); |
|
9772 |
ins_pipe(pipe_class_dummy); |
|
9773 |
%} |
|
9774 |
||
9775 |
// Call runtime without safepoint - same as CallRuntime |
|
9776 |
instruct CallLeafDirect(method meth) %{
|
|
9777 |
match(CallLeaf); |
|
9778 |
effect(USE meth); |
|
9779 |
ins_cost(CALL_COST); |
|
9780 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
9781 |
ins_num_consts(1); |
|
9782 |
ins_alignment(2); |
|
9783 |
format %{ "CALL,runtime leaf $meth" %}
|
|
9784 |
ins_encode( z_enc_java_to_runtime_call(meth) ); |
|
9785 |
ins_pipe(pipe_class_dummy); |
|
9786 |
%} |
|
9787 |
||
9788 |
// Call runtime without safepoint - same as CallLeaf |
|
9789 |
instruct CallLeafNoFPDirect(method meth) %{
|
|
9790 |
match(CallLeafNoFP); |
|
9791 |
effect(USE meth); |
|
9792 |
ins_cost(CALL_COST); |
|
9793 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
9794 |
ins_num_consts(1); |
|
9795 |
format %{ "CALL,runtime leaf nofp $meth" %}
|
|
9796 |
ins_encode( z_enc_java_to_runtime_call(meth) ); |
|
9797 |
ins_pipe(pipe_class_dummy); |
|
9798 |
ins_alignment(2); |
|
9799 |
%} |
|
9800 |
||
9801 |
// Tail Call; Jump from runtime stub to Java code. |
|
9802 |
// Also known as an 'interprocedural jump'. |
|
9803 |
// Target of jump will eventually return to caller. |
|
9804 |
// TailJump below removes the return address. |
|
9805 |
instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_oop) %{
|
|
9806 |
match(TailCall jump_target method_oop); |
|
9807 |
ins_cost(CALL_COST); |
|
9808 |
size(2); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
9809 |
format %{ "Jmp $jump_target\t # $method_oop holds method oop" %}
|
| 42065 | 9810 |
ins_encode %{ __ z_br($jump_target$$Register); %}
|
9811 |
ins_pipe(pipe_class_dummy); |
|
9812 |
%} |
|
9813 |
||
9814 |
// Return Instruction |
|
9815 |
instruct Ret() %{
|
|
9816 |
match(Return); |
|
9817 |
size(2); |
|
9818 |
format %{ "BR(Z_R14) // branch to link register" %}
|
|
9819 |
ins_encode %{ __ z_br(Z_R14); %}
|
|
9820 |
ins_pipe(pipe_class_dummy); |
|
9821 |
%} |
|
9822 |
||
9823 |
// Tail Jump; remove the return address; jump to target. |
|
9824 |
// TailCall above leaves the return address around. |
|
9825 |
// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). |
|
9826 |
// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a |
|
9827 |
// "restore" before this instruction (in Epilogue), we need to materialize it |
|
9828 |
// in %i0. |
|
9829 |
instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{
|
|
9830 |
match(TailJump jump_target ex_oop); |
|
9831 |
ins_cost(CALL_COST); |
|
9832 |
size(8); |
|
9833 |
format %{ "TailJump $jump_target" %}
|
|
9834 |
ins_encode %{
|
|
9835 |
__ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP); |
|
9836 |
__ z_br($jump_target$$Register); |
|
9837 |
%} |
|
9838 |
ins_pipe(pipe_class_dummy); |
|
9839 |
%} |
|
9840 |
||
9841 |
// Create exception oop: created by stack-crawling runtime code. |
|
9842 |
// Created exception is now available to this handler, and is setup |
|
9843 |
// just prior to jumping to this handler. No code emitted. |
|
9844 |
instruct CreateException(rarg1RegP ex_oop) %{
|
|
9845 |
match(Set ex_oop (CreateEx)); |
|
9846 |
ins_cost(0); |
|
9847 |
size(0); |
|
9848 |
format %{ "# exception oop; no code emitted" %}
|
|
9849 |
ins_encode(/*empty*/); |
|
9850 |
ins_pipe(pipe_class_dummy); |
|
9851 |
%} |
|
9852 |
||
9853 |
// Rethrow exception: The exception oop will come in the first |
|
9854 |
// argument position. Then JUMP (not call) to the rethrow stub code. |
|
9855 |
instruct RethrowException() %{
|
|
9856 |
match(Rethrow); |
|
9857 |
ins_cost(CALL_COST); |
|
9858 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
9859 |
format %{ "Jmp rethrow_stub" %}
|
|
9860 |
ins_encode %{
|
|
9861 |
cbuf.set_insts_mark(); |
|
9862 |
__ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub()); |
|
9863 |
__ z_br(Z_R1_scratch); |
|
9864 |
%} |
|
9865 |
ins_pipe(pipe_class_dummy); |
|
9866 |
%} |
|
9867 |
||
9868 |
// Die now. |
|
9869 |
instruct ShouldNotReachHere() %{
|
|
9870 |
match(Halt); |
|
9871 |
ins_cost(CALL_COST); |
|
9872 |
size(2); |
|
9873 |
format %{ "ILLTRAP; ShouldNotReachHere" %}
|
|
9874 |
ins_encode %{ __ z_illtrap(); %}
|
|
9875 |
ins_pipe(pipe_class_dummy); |
|
9876 |
%} |
|
9877 |
||
9878 |
// ============================================================================ |
|
9879 |
// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass |
|
9880 |
// array for an instance of the superklass. Set a hidden internal cache on a |
|
9881 |
// hit (cache is checked with exposed code in gen_subtype_check()). Return |
|
9882 |
// not zero for a miss or zero for a hit. The encoding ALSO sets flags. |
|
9883 |
instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc, |
|
9884 |
rarg4RegP scratch1, rarg5RegP scratch2) %{
|
|
9885 |
match(Set index (PartialSubtypeCheck sub super)); |
|
9886 |
effect(KILL pcc, KILL scratch1, KILL scratch2); |
|
9887 |
ins_cost(10 * DEFAULT_COST); |
|
|
51009
44b07bd68f6d
8206459: [s390] Prevent restoring incorrect bcp and locals in interpreter and avoid incorrect size of partialSubtypeCheckNode in C2
mdoerr
parents:
50162
diff
changeset
|
9888 |
// TODO: s390 port size(FIXED_SIZE); |
| 42065 | 9889 |
format %{ " CALL PartialSubtypeCheck\n" %}
|
9890 |
ins_encode %{
|
|
9891 |
AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check()); |
|
9892 |
__ load_const_optimized(Z_ARG4, stub_address); |
|
9893 |
__ z_basr(Z_R14, Z_ARG4); |
|
9894 |
%} |
|
9895 |
ins_pipe(pipe_class_dummy); |
|
9896 |
%} |
|
9897 |
||
9898 |
instruct partialSubtypeCheck_vs_zero(flagsReg pcc, rarg2RegP sub, rarg3RegP super, immP0 zero, |
|
9899 |
rarg1RegP index, rarg4RegP scratch1, rarg5RegP scratch2) %{
|
|
9900 |
match(Set pcc (CmpI (PartialSubtypeCheck sub super) zero)); |
|
9901 |
effect(KILL scratch1, KILL scratch2, KILL index); |
|
9902 |
ins_cost(10 * DEFAULT_COST); |
|
9903 |
// TODO: s390 port size(FIXED_SIZE); |
|
9904 |
format %{ "CALL PartialSubtypeCheck_vs_zero\n" %}
|
|
9905 |
ins_encode %{
|
|
9906 |
AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check()); |
|
9907 |
__ load_const_optimized(Z_ARG4, stub_address); |
|
9908 |
__ z_basr(Z_R14, Z_ARG4); |
|
9909 |
%} |
|
9910 |
ins_pipe(pipe_class_dummy); |
|
9911 |
%} |
|
9912 |
||
9913 |
// ============================================================================ |
|
9914 |
// inlined locking and unlocking |
|
9915 |
||
9916 |
instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
|
|
9917 |
match(Set pcc (FastLock oop box)); |
|
9918 |
effect(TEMP tmp1, TEMP tmp2); |
|
9919 |
ins_cost(100); |
|
9920 |
// TODO: s390 port size(VARIABLE_SIZE); // Uses load_const_optimized. |
|
9921 |
format %{ "FASTLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
|
|
9922 |
ins_encode %{ __ compiler_fast_lock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register,
|
|
9923 |
UseBiasedLocking && !UseOptoBiasInlining); %} |
|
9924 |
ins_pipe(pipe_class_dummy); |
|
9925 |
%} |
|
9926 |
||
9927 |
instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
|
|
9928 |
match(Set pcc (FastUnlock oop box)); |
|
9929 |
effect(TEMP tmp1, TEMP tmp2); |
|
9930 |
ins_cost(100); |
|
9931 |
// TODO: s390 port size(FIXED_SIZE); // emitted code depends on UseBiasedLocking being on/off. |
|
9932 |
format %{ "FASTUNLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
|
|
9933 |
ins_encode %{ __ compiler_fast_unlock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register,
|
|
9934 |
UseBiasedLocking && !UseOptoBiasInlining); %} |
|
9935 |
ins_pipe(pipe_class_dummy); |
|
9936 |
%} |
|
9937 |
||
9938 |
instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{
|
|
9939 |
match(Set dummy (ClearArray cnt base)); |
|
9940 |
effect(KILL cr); |
|
9941 |
ins_cost(100); |
|
9942 |
// TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to varying #instructions. |
|
9943 |
format %{ "ClearArrayConst $cnt,$base" %}
|
|
9944 |
ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %}
|
|
9945 |
ins_pipe(pipe_class_dummy); |
|
9946 |
%} |
|
9947 |
||
|
54542
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
9948 |
instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
|
| 42065 | 9949 |
match(Set dummy (ClearArray cnt base)); |
|
54542
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
9950 |
effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too. |
| 42065 | 9951 |
ins_cost(200); |
9952 |
// TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader. |
|
9953 |
format %{ "ClearArrayConstBig $cnt,$base" %}
|
|
|
54542
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
9954 |
ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $tmpL$$Register); %}
|
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
9955 |
ins_pipe(pipe_class_dummy); |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
9956 |
%} |
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
9957 |
|
|
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
9958 |
instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
|
| 42065 | 9959 |
match(Set dummy (ClearArray cnt base)); |
|
54542
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
9960 |
effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too. |
| 42065 | 9961 |
ins_cost(300); |
9962 |
// TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off. |
|
9963 |
format %{ "ClearArrayVar $cnt,$base" %}
|
|
|
54542
0a4214c90a55
8222271: [s390] optimize register usage in C2 instruction forms for clearing arrays
rrich
parents:
52412
diff
changeset
|
9964 |
ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $tmpL$$Register); %}
|
| 42065 | 9965 |
ins_pipe(pipe_class_dummy); |
9966 |
%} |
|
9967 |
||
9968 |
// ============================================================================ |
|
9969 |
// CompactStrings |
|
9970 |
||
9971 |
// String equals |
|
9972 |
instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
9973 |
match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
9974 |
effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
9975 |
predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL); |
|
9976 |
ins_cost(300); |
|
9977 |
format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
|
|
9978 |
ins_encode %{
|
|
9979 |
__ array_equals(false, $str1$$Register, $str2$$Register, |
|
9980 |
$cnt$$Register, $oddReg$$Register, $evenReg$$Register, |
|
9981 |
$result$$Register, true /* byte */); |
|
9982 |
%} |
|
9983 |
ins_pipe(pipe_class_dummy); |
|
9984 |
%} |
|
9985 |
||
9986 |
instruct string_equalsU(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
9987 |
match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
9988 |
effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
9989 |
predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none); |
|
9990 |
ins_cost(300); |
|
9991 |
format %{ "String Equals char[] $str1,$str2,$cnt -> $result" %}
|
|
9992 |
ins_encode %{
|
|
9993 |
__ array_equals(false, $str1$$Register, $str2$$Register, |
|
9994 |
$cnt$$Register, $oddReg$$Register, $evenReg$$Register, |
|
9995 |
$result$$Register, false /* byte */); |
|
9996 |
%} |
|
9997 |
ins_pipe(pipe_class_dummy); |
|
9998 |
%} |
|
9999 |
||
10000 |
instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{
|
|
10001 |
match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
10002 |
effect(KILL cr); // R0 is killed, too. |
|
10003 |
predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU); |
|
10004 |
ins_cost(100); |
|
10005 |
format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
|
|
10006 |
ins_encode %{
|
|
10007 |
const int cnt_imm = $cnt$$constant; |
|
10008 |
if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); }
|
|
10009 |
__ z_lhi($result$$Register, 1); |
|
10010 |
if (cnt_imm) {
|
|
10011 |
if (VM_Version::has_LoadStoreConditional()) {
|
|
10012 |
__ z_lhi(Z_R0_scratch, 0); |
|
10013 |
__ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual); |
|
10014 |
} else {
|
|
10015 |
Label Lskip; |
|
10016 |
__ z_bre(Lskip); |
|
10017 |
__ clear_reg($result$$Register); |
|
10018 |
__ bind(Lskip); |
|
10019 |
} |
|
10020 |
} |
|
10021 |
%} |
|
10022 |
ins_pipe(pipe_class_dummy); |
|
10023 |
%} |
|
10024 |
||
10025 |
instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{
|
|
10026 |
match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
10027 |
effect(KILL cr); // R0 is killed, too. |
|
10028 |
predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none); |
|
10029 |
ins_cost(100); |
|
10030 |
format %{ "String Equals $str1,$str2,$cnt -> $result" %}
|
|
10031 |
ins_encode %{
|
|
10032 |
const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used) |
|
10033 |
if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); }
|
|
10034 |
__ z_lhi($result$$Register, 1); |
|
10035 |
if (cnt_imm) {
|
|
10036 |
if (VM_Version::has_LoadStoreConditional()) {
|
|
10037 |
__ z_lhi(Z_R0_scratch, 0); |
|
10038 |
__ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual); |
|
10039 |
} else {
|
|
10040 |
Label Lskip; |
|
10041 |
__ z_bre(Lskip); |
|
10042 |
__ clear_reg($result$$Register); |
|
10043 |
__ bind(Lskip); |
|
10044 |
} |
|
10045 |
} |
|
10046 |
%} |
|
10047 |
ins_pipe(pipe_class_dummy); |
|
10048 |
%} |
|
10049 |
||
10050 |
// Array equals |
|
10051 |
instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10052 |
match(Set result (AryEq ary1 ary2)); |
|
10053 |
effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
10054 |
predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL); |
|
10055 |
ins_cost(300); |
|
10056 |
format %{ "Array Equals $ary1,$ary2 -> $result" %}
|
|
10057 |
ins_encode %{
|
|
10058 |
__ array_equals(true, $ary1$$Register, $ary2$$Register, |
|
10059 |
noreg, $oddReg$$Register, $evenReg$$Register, |
|
10060 |
$result$$Register, true /* byte */); |
|
10061 |
%} |
|
10062 |
ins_pipe(pipe_class_dummy); |
|
10063 |
%} |
|
10064 |
||
10065 |
instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10066 |
match(Set result (AryEq ary1 ary2)); |
|
10067 |
effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
10068 |
predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU); |
|
10069 |
ins_cost(300); |
|
10070 |
format %{ "Array Equals $ary1,$ary2 -> $result" %}
|
|
10071 |
ins_encode %{
|
|
10072 |
__ array_equals(true, $ary1$$Register, $ary2$$Register, |
|
10073 |
noreg, $oddReg$$Register, $evenReg$$Register, |
|
10074 |
$result$$Register, false /* byte */); |
|
10075 |
%} |
|
10076 |
ins_pipe(pipe_class_dummy); |
|
10077 |
%} |
|
10078 |
||
10079 |
// String CompareTo |
|
10080 |
instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10081 |
match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
10082 |
effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
10083 |
predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL); |
|
10084 |
ins_cost(300); |
|
10085 |
format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
|
|
10086 |
ins_encode %{
|
|
10087 |
__ string_compare($str1$$Register, $str2$$Register, |
|
10088 |
$cnt1$$Register, $cnt2$$Register, |
|
10089 |
$oddReg$$Register, $evenReg$$Register, |
|
10090 |
$result$$Register, StrIntrinsicNode::LL); |
|
10091 |
%} |
|
10092 |
ins_pipe(pipe_class_dummy); |
|
10093 |
%} |
|
10094 |
||
10095 |
instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10096 |
match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
10097 |
effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
10098 |
predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none); |
|
10099 |
ins_cost(300); |
|
10100 |
format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
|
|
10101 |
ins_encode %{
|
|
10102 |
__ string_compare($str1$$Register, $str2$$Register, |
|
10103 |
$cnt1$$Register, $cnt2$$Register, |
|
10104 |
$oddReg$$Register, $evenReg$$Register, |
|
10105 |
$result$$Register, StrIntrinsicNode::UU); |
|
10106 |
%} |
|
10107 |
ins_pipe(pipe_class_dummy); |
|
10108 |
%} |
|
10109 |
||
10110 |
instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10111 |
match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
10112 |
effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
10113 |
predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU); |
|
10114 |
ins_cost(300); |
|
10115 |
format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
|
|
10116 |
ins_encode %{
|
|
10117 |
__ string_compare($str1$$Register, $str2$$Register, |
|
10118 |
$cnt1$$Register, $cnt2$$Register, |
|
10119 |
$oddReg$$Register, $evenReg$$Register, |
|
10120 |
$result$$Register, StrIntrinsicNode::LU); |
|
10121 |
%} |
|
10122 |
ins_pipe(pipe_class_dummy); |
|
10123 |
%} |
|
10124 |
||
10125 |
instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10126 |
match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
10127 |
effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
10128 |
predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL); |
|
10129 |
ins_cost(300); |
|
10130 |
format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
|
|
10131 |
ins_encode %{
|
|
10132 |
__ string_compare($str2$$Register, $str1$$Register, |
|
10133 |
$cnt2$$Register, $cnt1$$Register, |
|
10134 |
$oddReg$$Register, $evenReg$$Register, |
|
10135 |
$result$$Register, StrIntrinsicNode::UL); |
|
10136 |
%} |
|
10137 |
ins_pipe(pipe_class_dummy); |
|
10138 |
%} |
|
10139 |
||
10140 |
// String IndexOfChar |
|
10141 |
instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10142 |
match(Set result (StrIndexOfChar (Binary haystack haycnt) ch)); |
|
10143 |
effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. |
|
10144 |
ins_cost(200); |
|
10145 |
format %{ "String IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
|
|
10146 |
ins_encode %{
|
|
10147 |
__ string_indexof_char($result$$Register, |
|
10148 |
$haystack$$Register, $haycnt$$Register, |
|
10149 |
$ch$$Register, 0 /* unused, ch is in register */, |
|
10150 |
$oddReg$$Register, $evenReg$$Register, false /*is_byte*/); |
|
10151 |
%} |
|
10152 |
ins_pipe(pipe_class_dummy); |
|
10153 |
%} |
|
10154 |
||
10155 |
instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10156 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); |
|
10157 |
effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. |
|
10158 |
predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); |
|
10159 |
ins_cost(200); |
|
10160 |
format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
|
|
10161 |
ins_encode %{
|
|
10162 |
immPOper *needleOper = (immPOper *)$needle; |
|
10163 |
const TypeOopPtr *t = needleOper->type()->isa_oopptr(); |
|
10164 |
ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * |
|
10165 |
jchar chr; |
|
10166 |
#ifdef VM_LITTLE_ENDIAN |
|
10167 |
Unimplemented(); |
|
10168 |
#else |
|
10169 |
chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) | |
|
10170 |
((jchar)(unsigned char)needle_values->element_value(1).as_byte()); |
|
10171 |
#endif |
|
10172 |
__ string_indexof_char($result$$Register, |
|
10173 |
$haystack$$Register, $haycnt$$Register, |
|
10174 |
noreg, chr, |
|
10175 |
$oddReg$$Register, $evenReg$$Register, false /*is_byte*/); |
|
10176 |
%} |
|
10177 |
ins_pipe(pipe_class_dummy); |
|
10178 |
%} |
|
10179 |
||
10180 |
instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10181 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); |
|
10182 |
effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. |
|
10183 |
predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); |
|
10184 |
ins_cost(200); |
|
10185 |
format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %}
|
|
10186 |
ins_encode %{
|
|
10187 |
immPOper *needleOper = (immPOper *)$needle; |
|
10188 |
const TypeOopPtr *t = needleOper->type()->isa_oopptr(); |
|
10189 |
ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * |
|
10190 |
jchar chr = (jchar)needle_values->element_value(0).as_byte(); |
|
10191 |
__ string_indexof_char($result$$Register, |
|
10192 |
$haystack$$Register, $haycnt$$Register, |
|
10193 |
noreg, chr, |
|
10194 |
$oddReg$$Register, $evenReg$$Register, true /*is_byte*/); |
|
10195 |
%} |
|
10196 |
ins_pipe(pipe_class_dummy); |
|
10197 |
%} |
|
10198 |
||
10199 |
instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10200 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); |
|
10201 |
effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. |
|
10202 |
predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); |
|
10203 |
ins_cost(200); |
|
10204 |
format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
|
|
10205 |
ins_encode %{
|
|
10206 |
immPOper *needleOper = (immPOper *)$needle; |
|
10207 |
const TypeOopPtr *t = needleOper->type()->isa_oopptr(); |
|
10208 |
ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * |
|
10209 |
jchar chr = (jchar)needle_values->element_value(0).as_byte(); |
|
10210 |
__ string_indexof_char($result$$Register, |
|
10211 |
$haystack$$Register, $haycnt$$Register, |
|
10212 |
noreg, chr, |
|
10213 |
$oddReg$$Register, $evenReg$$Register, false /*is_byte*/); |
|
10214 |
%} |
|
10215 |
ins_pipe(pipe_class_dummy); |
|
10216 |
%} |
|
10217 |
||
10218 |
// String IndexOf |
|
10219 |
instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10220 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); |
|
10221 |
effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
10222 |
predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); |
|
10223 |
ins_cost(250); |
|
10224 |
format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
|
|
10225 |
ins_encode %{
|
|
10226 |
__ string_indexof($result$$Register, |
|
10227 |
$haystack$$Register, $haycnt$$Register, |
|
10228 |
$needle$$Register, noreg, $needlecntImm$$constant, |
|
10229 |
$oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU); |
|
10230 |
%} |
|
10231 |
ins_pipe(pipe_class_dummy); |
|
10232 |
%} |
|
10233 |
||
10234 |
instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10235 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); |
|
10236 |
effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
10237 |
predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); |
|
10238 |
ins_cost(250); |
|
10239 |
format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
|
|
10240 |
ins_encode %{
|
|
10241 |
__ string_indexof($result$$Register, |
|
10242 |
$haystack$$Register, $haycnt$$Register, |
|
10243 |
$needle$$Register, noreg, $needlecntImm$$constant, |
|
10244 |
$oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL); |
|
10245 |
%} |
|
10246 |
ins_pipe(pipe_class_dummy); |
|
10247 |
%} |
|
10248 |
||
10249 |
instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10250 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); |
|
10251 |
effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
10252 |
predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); |
|
10253 |
ins_cost(250); |
|
10254 |
format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
|
|
10255 |
ins_encode %{
|
|
10256 |
__ string_indexof($result$$Register, |
|
10257 |
$haystack$$Register, $haycnt$$Register, |
|
10258 |
$needle$$Register, noreg, $needlecntImm$$constant, |
|
10259 |
$oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL); |
|
10260 |
%} |
|
10261 |
ins_pipe(pipe_class_dummy); |
|
10262 |
%} |
|
10263 |
||
10264 |
instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10265 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); |
|
10266 |
effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
10267 |
predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); |
|
10268 |
ins_cost(300); |
|
10269 |
format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
|
|
10270 |
ins_encode %{
|
|
10271 |
__ string_indexof($result$$Register, |
|
10272 |
$haystack$$Register, $haycnt$$Register, |
|
10273 |
$needle$$Register, $needlecnt$$Register, 0, |
|
10274 |
$oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU); |
|
10275 |
%} |
|
10276 |
ins_pipe(pipe_class_dummy); |
|
10277 |
%} |
|
10278 |
||
10279 |
instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10280 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); |
|
10281 |
effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
10282 |
predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); |
|
10283 |
ins_cost(300); |
|
10284 |
format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
|
|
10285 |
ins_encode %{
|
|
10286 |
__ string_indexof($result$$Register, |
|
10287 |
$haystack$$Register, $haycnt$$Register, |
|
10288 |
$needle$$Register, $needlecnt$$Register, 0, |
|
10289 |
$oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL); |
|
10290 |
%} |
|
10291 |
ins_pipe(pipe_class_dummy); |
|
10292 |
%} |
|
10293 |
||
10294 |
instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
|
|
10295 |
match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); |
|
10296 |
effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. |
|
10297 |
predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); |
|
10298 |
ins_cost(300); |
|
10299 |
format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
|
|
10300 |
ins_encode %{
|
|
10301 |
__ string_indexof($result$$Register, |
|
10302 |
$haystack$$Register, $haycnt$$Register, |
|
10303 |
$needle$$Register, $needlecnt$$Register, 0, |
|
10304 |
$oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL); |
|
10305 |
%} |
|
10306 |
ins_pipe(pipe_class_dummy); |
|
10307 |
%} |
|
10308 |
||
10309 |
// char[] to byte[] compression |
|
|
48094
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10310 |
instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{
|
| 42065 | 10311 |
match(Set result (StrCompressedCopy src (Binary dst len))); |
|
48094
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10312 |
effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too. |
| 42065 | 10313 |
ins_cost(300); |
10314 |
format %{ "String Compress $src->$dst($len) -> $result" %}
|
|
10315 |
ins_encode %{
|
|
10316 |
__ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register, |
|
|
48094
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10317 |
$tmp$$Register, false); |
| 42065 | 10318 |
%} |
10319 |
ins_pipe(pipe_class_dummy); |
|
10320 |
%} |
|
10321 |
||
10322 |
// byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop. |
|
10323 |
//instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{
|
|
10324 |
// match(Set dummy (StrInflatedCopy src (Binary dst len))); |
|
10325 |
// effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too. |
|
10326 |
// predicate(VM_Version::has_ETF2Enhancements()); |
|
10327 |
// ins_cost(300); |
|
10328 |
// format %{ "String Inflate (trot) $dst,$src($len)" %}
|
|
10329 |
// ins_encode %{
|
|
10330 |
// __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register); |
|
10331 |
// %} |
|
10332 |
// ins_pipe(pipe_class_dummy); |
|
10333 |
//%} |
|
10334 |
||
10335 |
// byte[] to char[] inflation |
|
|
48094
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10336 |
instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, flagsReg cr) %{
|
| 42065 | 10337 |
match(Set dummy (StrInflatedCopy src (Binary dst len))); |
|
48094
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10338 |
effect(TEMP tmp, KILL cr); // R0, R1 are killed, too. |
| 42065 | 10339 |
ins_cost(300); |
10340 |
format %{ "String Inflate $src->$dst($len)" %}
|
|
10341 |
ins_encode %{
|
|
|
48094
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10342 |
__ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register); |
|
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10343 |
%} |
|
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10344 |
ins_pipe(pipe_class_dummy); |
|
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10345 |
%} |
|
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10346 |
|
|
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10347 |
// byte[] to char[] inflation |
|
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10348 |
instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, flagsReg cr) %{
|
|
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10349 |
match(Set dummy (StrInflatedCopy src (Binary dst len))); |
|
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10350 |
effect(TEMP tmp, KILL cr); // R0, R1 are killed, too. |
|
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10351 |
ins_cost(300); |
|
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10352 |
format %{ "String Inflate (constLen) $src->$dst($len)" %}
|
|
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10353 |
ins_encode %{
|
|
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10354 |
__ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant); |
| 42065 | 10355 |
%} |
10356 |
ins_pipe(pipe_class_dummy); |
|
10357 |
%} |
|
10358 |
||
10359 |
// StringCoding.java intrinsics |
|
10360 |
instruct has_negatives(rarg5RegP ary1, iRegI len, iRegI result, roddRegI oddReg, revenRegI evenReg, iRegI tmp, flagsReg cr) %{
|
|
10361 |
match(Set result (HasNegatives ary1 len)); |
|
10362 |
effect(TEMP_DEF result, USE_KILL ary1, TEMP oddReg, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too. |
|
10363 |
ins_cost(300); |
|
10364 |
format %{ "has negatives byte[] $ary1($len) -> $result" %}
|
|
10365 |
ins_encode %{
|
|
10366 |
__ has_negatives($result$$Register, $ary1$$Register, $len$$Register, |
|
10367 |
$oddReg$$Register, $evenReg$$Register, $tmp$$Register); |
|
10368 |
%} |
|
10369 |
ins_pipe(pipe_class_dummy); |
|
10370 |
%} |
|
10371 |
||
10372 |
// encode char[] to byte[] in ISO_8859_1 |
|
|
48094
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10373 |
instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{
|
| 42065 | 10374 |
match(Set result (EncodeISOArray src (Binary dst len))); |
|
48094
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10375 |
effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too. |
| 42065 | 10376 |
ins_cost(300); |
10377 |
format %{ "Encode array $src->$dst($len) -> $result" %}
|
|
10378 |
ins_encode %{
|
|
10379 |
__ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register, |
|
|
48094
bca569f79fa1
8189793: [s390]: Improve String compress/inflate by exploiting vector instructions
lucy
parents:
47606
diff
changeset
|
10380 |
$tmp$$Register, true); |
| 42065 | 10381 |
%} |
10382 |
ins_pipe(pipe_class_dummy); |
|
10383 |
%} |
|
10384 |
||
10385 |
||
10386 |
//----------PEEPHOLE RULES----------------------------------------------------- |
|
10387 |
// These must follow all instruction definitions as they use the names |
|
10388 |
// defined in the instructions definitions. |
|
10389 |
// |
|
10390 |
// peepmatch (root_instr_name [preceeding_instruction]*); |
|
10391 |
// |
|
10392 |
// peepconstraint %{
|
|
10393 |
// (instruction_number.operand_name relational_op instruction_number.operand_name |
|
10394 |
// [, ...]); |
|
10395 |
// // instruction numbers are zero-based using left to right order in peepmatch |
|
10396 |
// |
|
10397 |
// peepreplace (instr_name([instruction_number.operand_name]*)); |
|
10398 |
// // provide an instruction_number.operand_name for each operand that appears |
|
10399 |
// // in the replacement instruction's match rule |
|
10400 |
// |
|
10401 |
// ---------VM FLAGS--------------------------------------------------------- |
|
10402 |
// |
|
10403 |
// All peephole optimizations can be turned off using -XX:-OptoPeephole |
|
10404 |
// |
|
10405 |
// Each peephole rule is given an identifying number starting with zero and |
|
10406 |
// increasing by one in the order seen by the parser. An individual peephole |
|
10407 |
// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# |
|
10408 |
// on the command-line. |
|
10409 |
// |
|
10410 |
// ---------CURRENT LIMITATIONS---------------------------------------------- |
|
10411 |
// |
|
10412 |
// Only match adjacent instructions in same basic block |
|
10413 |
// Only equality constraints |
|
10414 |
// Only constraints between operands, not (0.dest_reg == EAX_enc) |
|
10415 |
// Only one replacement instruction |
|
10416 |
// |
|
10417 |
// ---------EXAMPLE---------------------------------------------------------- |
|
10418 |
// |
|
10419 |
// // pertinent parts of existing instructions in architecture description |
|
10420 |
// instruct movI(eRegI dst, eRegI src) %{
|
|
10421 |
// match(Set dst (CopyI src)); |
|
10422 |
// %} |
|
10423 |
// |
|
10424 |
// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
|
|
10425 |
// match(Set dst (AddI dst src)); |
|
10426 |
// effect(KILL cr); |
|
10427 |
// %} |
|
10428 |
// |
|
10429 |
// // Change (inc mov) to lea |
|
10430 |
// peephole %{
|
|
10431 |
// // increment preceeded by register-register move |
|
10432 |
// peepmatch (incI_eReg movI); |
|
10433 |
// // require that the destination register of the increment |
|
10434 |
// // match the destination register of the move |
|
10435 |
// peepconstraint (0.dst == 1.dst); |
|
10436 |
// // construct a replacement instruction that sets |
|
10437 |
// // the destination to (move's source register + one) |
|
10438 |
// peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); |
|
10439 |
// %} |
|
10440 |
// |
|
10441 |
// Implementation no longer uses movX instructions since |
|
10442 |
// machine-independent system no longer uses CopyX nodes. |
|
10443 |
// |
|
10444 |
// peephole %{
|
|
10445 |
// peepmatch (incI_eReg movI); |
|
10446 |
// peepconstraint (0.dst == 1.dst); |
|
10447 |
// peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); |
|
10448 |
// %} |
|
10449 |
// |
|
10450 |
// peephole %{
|
|
10451 |
// peepmatch (decI_eReg movI); |
|
10452 |
// peepconstraint (0.dst == 1.dst); |
|
10453 |
// peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); |
|
10454 |
// %} |
|
10455 |
// |
|
10456 |
// peephole %{
|
|
10457 |
// peepmatch (addI_eReg_imm movI); |
|
10458 |
// peepconstraint (0.dst == 1.dst); |
|
10459 |
// peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); |
|
10460 |
// %} |
|
10461 |
// |
|
10462 |
// peephole %{
|
|
10463 |
// peepmatch (addP_eReg_imm movP); |
|
10464 |
// peepconstraint (0.dst == 1.dst); |
|
10465 |
// peepreplace (leaP_eReg_immI(0.dst 1.src 0.src)); |
|
10466 |
// %} |
|
10467 |
||
10468 |
||
10469 |
// This peephole rule does not work, probably because ADLC can't handle two effects: |
|
10470 |
// Effect 1 is defining 0.op1 and effect 2 is setting CC |
|
10471 |
// condense a load from memory and subsequent test for zero |
|
10472 |
// into a single, more efficient ICM instruction. |
|
10473 |
// peephole %{
|
|
10474 |
// peepmatch (compI_iReg_imm0 loadI); |
|
10475 |
// peepconstraint (1.dst == 0.op1); |
|
10476 |
// peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem)); |
|
10477 |
// %} |
|
10478 |
||
10479 |
// // Change load of spilled value to only a spill |
|
10480 |
// instruct storeI(memory mem, eRegI src) %{
|
|
10481 |
// match(Set mem (StoreI mem src)); |
|
10482 |
// %} |
|
10483 |
// |
|
10484 |
// instruct loadI(eRegI dst, memory mem) %{
|
|
10485 |
// match(Set dst (LoadI mem)); |
|
10486 |
// %} |
|
10487 |
// |
|
10488 |
peephole %{
|
|
10489 |
peepmatch (loadI storeI); |
|
10490 |
peepconstraint (1.src == 0.dst, 1.mem == 0.mem); |
|
10491 |
peepreplace (storeI(1.mem 1.mem 1.src)); |
|
10492 |
%} |
|
10493 |
||
10494 |
peephole %{
|
|
10495 |
peepmatch (loadL storeL); |
|
10496 |
peepconstraint (1.src == 0.dst, 1.mem == 0.mem); |
|
10497 |
peepreplace (storeL(1.mem 1.mem 1.src)); |
|
10498 |
%} |
|
10499 |
||
10500 |
peephole %{
|
|
10501 |
peepmatch (loadP storeP); |
|
10502 |
peepconstraint (1.src == 0.dst, 1.dst == 0.mem); |
|
10503 |
peepreplace (storeP(1.dst 1.dst 1.src)); |
|
10504 |
%} |
|
10505 |
||
10506 |
//----------SUPERWORD RULES--------------------------------------------------- |
|
10507 |
||
10508 |
// Expand rules for special cases |
|
10509 |
||
10510 |
instruct expand_storeF(stackSlotF mem, regF src) %{
|
|
10511 |
// No match rule, false predicate, for expand only. |
|
10512 |
effect(DEF mem, USE src); |
|
10513 |
predicate(false); |
|
10514 |
ins_cost(MEMORY_REF_COST); |
|
10515 |
// TODO: s390 port size(FIXED_SIZE); |
|
10516 |
format %{ "STE $src,$mem\t # replicate(float2stack)" %}
|
|
10517 |
opcode(STE_ZOPC, STE_ZOPC); |
|
10518 |
ins_encode(z_form_rt_mem(src, mem)); |
|
10519 |
ins_pipe(pipe_class_dummy); |
|
10520 |
%} |
|
10521 |
||
10522 |
instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{
|
|
10523 |
// No match rule, false predicate, for expand only. |
|
10524 |
effect(DEF dst, USE mem); |
|
10525 |
predicate(false); |
|
10526 |
ins_cost(MEMORY_REF_COST); |
|
10527 |
// TODO: s390 port size(FIXED_SIZE); |
|
10528 |
format %{ "LLGF $dst,$mem\t # replicate(stack2reg(unsigned))" %}
|
|
10529 |
opcode(LLGF_ZOPC, LLGF_ZOPC); |
|
10530 |
ins_encode(z_form_rt_mem(dst, mem)); |
|
10531 |
ins_pipe(pipe_class_dummy); |
|
10532 |
%} |
|
10533 |
||
10534 |
// Replicate scalar int to packed int values (8 Bytes) |
|
10535 |
instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{
|
|
10536 |
// Dummy match rule, false predicate, for expand only. |
|
10537 |
match(Set dst (ConvI2L src)); |
|
10538 |
predicate(false); |
|
10539 |
ins_cost(DEFAULT_COST); |
|
10540 |
// TODO: s390 port size(FIXED_SIZE); |
|
10541 |
format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %}
|
|
10542 |
ins_encode %{
|
|
10543 |
if ($dst$$Register == $src$$Register) {
|
|
10544 |
__ z_sllg(Z_R0_scratch, $src$$Register, 64-32); |
|
10545 |
__ z_ogr($dst$$Register, Z_R0_scratch); |
|
10546 |
} else {
|
|
10547 |
__ z_sllg($dst$$Register, $src$$Register, 64-32); |
|
10548 |
__ z_ogr( $dst$$Register, $src$$Register); |
|
10549 |
} |
|
10550 |
%} |
|
10551 |
ins_pipe(pipe_class_dummy); |
|
10552 |
%} |
|
10553 |
||
10554 |
// Replication |
|
10555 |
||
10556 |
// Exploit rotate_then_insert, if available |
|
10557 |
// Replicate scalar byte to packed byte values (8 Bytes). |
|
10558 |
instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
|
|
10559 |
match(Set dst (ReplicateB src)); |
|
10560 |
effect(KILL cr); |
|
10561 |
predicate((n->as_Vector()->length() == 8)); |
|
10562 |
format %{ "REPLIC8B $dst,$src\t # pack8B" %}
|
|
10563 |
ins_encode %{
|
|
10564 |
if ($dst$$Register != $src$$Register) {
|
|
10565 |
__ z_lgr($dst$$Register, $src$$Register); |
|
10566 |
} |
|
10567 |
__ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55, 8, false); |
|
10568 |
__ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false); |
|
10569 |
__ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); |
|
10570 |
%} |
|
10571 |
ins_pipe(pipe_class_dummy); |
|
10572 |
%} |
|
10573 |
||
10574 |
// Replicate scalar byte to packed byte values (8 Bytes). |
|
10575 |
instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{
|
|
10576 |
match(Set dst (ReplicateB src)); |
|
10577 |
predicate(n->as_Vector()->length() == 8); |
|
10578 |
ins_should_rematerialize(true); |
|
10579 |
format %{ "REPLIC8B $dst,$src\t # pack8B imm" %}
|
|
10580 |
ins_encode %{
|
|
10581 |
int64_t Isrc8 = $src$$constant & 0x000000ff; |
|
10582 |
int64_t Isrc16 = Isrc8 << 8 | Isrc8; |
|
10583 |
int64_t Isrc32 = Isrc16 << 16 | Isrc16; |
|
10584 |
assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules."); |
|
10585 |
||
10586 |
__ z_llilf($dst$$Register, Isrc32); |
|
10587 |
__ z_iihf($dst$$Register, Isrc32); |
|
10588 |
%} |
|
10589 |
ins_pipe(pipe_class_dummy); |
|
10590 |
%} |
|
10591 |
||
10592 |
// Replicate scalar byte to packed byte values (8 Bytes). |
|
10593 |
instruct Repl8B_imm0(iRegL dst, immI_0 src) %{
|
|
10594 |
match(Set dst (ReplicateB src)); |
|
10595 |
predicate(n->as_Vector()->length() == 8); |
|
10596 |
ins_should_rematerialize(true); |
|
10597 |
format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %}
|
|
10598 |
ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
|
|
10599 |
ins_pipe(pipe_class_dummy); |
|
10600 |
%} |
|
10601 |
||
10602 |
// Replicate scalar byte to packed byte values (8 Bytes). |
|
10603 |
instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{
|
|
10604 |
match(Set dst (ReplicateB src)); |
|
10605 |
predicate(n->as_Vector()->length() == 8); |
|
10606 |
ins_should_rematerialize(true); |
|
10607 |
format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %}
|
|
10608 |
ins_encode %{ __ z_lghi($dst$$Register, -1); %}
|
|
10609 |
ins_pipe(pipe_class_dummy); |
|
10610 |
%} |
|
10611 |
||
10612 |
// Exploit rotate_then_insert, if available |
|
10613 |
// Replicate scalar short to packed short values (8 Bytes). |
|
10614 |
instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
|
|
10615 |
match(Set dst (ReplicateS src)); |
|
10616 |
effect(KILL cr); |
|
10617 |
predicate((n->as_Vector()->length() == 4)); |
|
10618 |
format %{ "REPLIC4S $dst,$src\t # pack4S" %}
|
|
10619 |
ins_encode %{
|
|
10620 |
if ($dst$$Register != $src$$Register) {
|
|
10621 |
__ z_lgr($dst$$Register, $src$$Register); |
|
10622 |
} |
|
10623 |
__ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false); |
|
10624 |
__ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); |
|
10625 |
%} |
|
10626 |
ins_pipe(pipe_class_dummy); |
|
10627 |
%} |
|
10628 |
||
10629 |
// Replicate scalar short to packed short values (8 Bytes). |
|
10630 |
instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{
|
|
10631 |
match(Set dst (ReplicateS src)); |
|
10632 |
predicate(n->as_Vector()->length() == 4); |
|
10633 |
ins_should_rematerialize(true); |
|
10634 |
format %{ "REPLIC4S $dst,$src\t # pack4S imm" %}
|
|
10635 |
ins_encode %{
|
|
10636 |
int64_t Isrc16 = $src$$constant & 0x0000ffff; |
|
10637 |
int64_t Isrc32 = Isrc16 << 16 | Isrc16; |
|
10638 |
assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT |
|
10639 |
") should be handled by other match rules.", $src$$constant); |
|
10640 |
||
10641 |
__ z_llilf($dst$$Register, Isrc32); |
|
10642 |
__ z_iihf($dst$$Register, Isrc32); |
|
10643 |
%} |
|
10644 |
ins_pipe(pipe_class_dummy); |
|
10645 |
%} |
|
10646 |
||
10647 |
// Replicate scalar short to packed short values (8 Bytes). |
|
10648 |
instruct Repl4S_imm0(iRegL dst, immI_0 src) %{
|
|
10649 |
match(Set dst (ReplicateS src)); |
|
10650 |
predicate(n->as_Vector()->length() == 4); |
|
10651 |
ins_should_rematerialize(true); |
|
10652 |
format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %}
|
|
10653 |
ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
|
|
10654 |
ins_pipe(pipe_class_dummy); |
|
10655 |
%} |
|
10656 |
||
10657 |
// Replicate scalar short to packed short values (8 Bytes). |
|
10658 |
instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{
|
|
10659 |
match(Set dst (ReplicateS src)); |
|
10660 |
predicate(n->as_Vector()->length() == 4); |
|
10661 |
ins_should_rematerialize(true); |
|
10662 |
format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %}
|
|
10663 |
ins_encode %{ __ z_lghi($dst$$Register, -1); %}
|
|
10664 |
ins_pipe(pipe_class_dummy); |
|
10665 |
%} |
|
10666 |
||
10667 |
// Exploit rotate_then_insert, if available. |
|
10668 |
// Replicate scalar int to packed int values (8 Bytes). |
|
10669 |
instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
|
|
10670 |
match(Set dst (ReplicateI src)); |
|
10671 |
effect(KILL cr); |
|
10672 |
predicate((n->as_Vector()->length() == 2)); |
|
10673 |
format %{ "REPLIC2I $dst,$src\t # pack2I" %}
|
|
10674 |
ins_encode %{
|
|
10675 |
if ($dst$$Register != $src$$Register) {
|
|
10676 |
__ z_lgr($dst$$Register, $src$$Register); |
|
10677 |
} |
|
10678 |
__ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); |
|
10679 |
%} |
|
10680 |
ins_pipe(pipe_class_dummy); |
|
10681 |
%} |
|
10682 |
||
10683 |
// Replicate scalar int to packed int values (8 Bytes). |
|
10684 |
instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{
|
|
10685 |
match(Set dst (ReplicateI src)); |
|
10686 |
predicate(n->as_Vector()->length() == 2); |
|
10687 |
ins_should_rematerialize(true); |
|
10688 |
format %{ "REPLIC2I $dst,$src\t # pack2I imm" %}
|
|
10689 |
ins_encode %{
|
|
10690 |
int64_t Isrc32 = $src$$constant; |
|
10691 |
assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules."); |
|
10692 |
||
10693 |
__ z_llilf($dst$$Register, Isrc32); |
|
10694 |
__ z_iihf($dst$$Register, Isrc32); |
|
10695 |
%} |
|
10696 |
ins_pipe(pipe_class_dummy); |
|
10697 |
%} |
|
10698 |
||
10699 |
// Replicate scalar int to packed int values (8 Bytes). |
|
10700 |
instruct Repl2I_imm0(iRegL dst, immI_0 src) %{
|
|
10701 |
match(Set dst (ReplicateI src)); |
|
10702 |
predicate(n->as_Vector()->length() == 2); |
|
10703 |
ins_should_rematerialize(true); |
|
10704 |
format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %}
|
|
10705 |
ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
|
|
10706 |
ins_pipe(pipe_class_dummy); |
|
10707 |
%} |
|
10708 |
||
10709 |
// Replicate scalar int to packed int values (8 Bytes). |
|
10710 |
instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{
|
|
10711 |
match(Set dst (ReplicateI src)); |
|
10712 |
predicate(n->as_Vector()->length() == 2); |
|
10713 |
ins_should_rematerialize(true); |
|
10714 |
format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %}
|
|
10715 |
ins_encode %{ __ z_lghi($dst$$Register, -1); %}
|
|
10716 |
ins_pipe(pipe_class_dummy); |
|
10717 |
%} |
|
10718 |
||
10719 |
// |
|
10720 |
||
10721 |
instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{
|
|
10722 |
match(Set dst (ReplicateF src)); |
|
10723 |
effect(KILL cr); |
|
10724 |
predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2); |
|
10725 |
format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %}
|
|
10726 |
expand %{
|
|
10727 |
stackSlotF tmp; |
|
10728 |
iRegL tmp2; |
|
10729 |
expand_storeF(tmp, src); |
|
10730 |
expand_LoadLogical_I2L(tmp2, tmp); |
|
10731 |
expand_Repl2I_reg(dst, tmp2); |
|
10732 |
%} |
|
10733 |
%} |
|
10734 |
||
10735 |
// Replicate scalar float to packed float values in GREG (8 Bytes). |
|
10736 |
instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{
|
|
10737 |
match(Set dst (ReplicateF src)); |
|
10738 |
effect(KILL cr); |
|
10739 |
predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2); |
|
10740 |
format %{ "REPLIC2F $dst,$src\t # pack2F direct" %}
|
|
10741 |
ins_encode %{
|
|
10742 |
assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W"); |
|
10743 |
__ z_lgdr($dst$$Register, $src$$FloatRegister); |
|
10744 |
||
10745 |
__ z_srlg(Z_R0_scratch, $dst$$Register, 32); // Floats are left-justified in 64bit reg. |
|
10746 |
__ z_iilf($dst$$Register, 0); // Save a "result not ready" stall. |
|
10747 |
__ z_ogr($dst$$Register, Z_R0_scratch); |
|
10748 |
%} |
|
10749 |
ins_pipe(pipe_class_dummy); |
|
10750 |
%} |
|
10751 |
||
10752 |
// Replicate scalar float immediate to packed float values in GREG (8 Bytes). |
|
10753 |
instruct Repl2F_imm(iRegL dst, immF src) %{
|
|
10754 |
match(Set dst (ReplicateF src)); |
|
10755 |
predicate(n->as_Vector()->length() == 2); |
|
10756 |
ins_should_rematerialize(true); |
|
10757 |
format %{ "REPLIC2F $dst,$src\t # pack2F imm" %}
|
|
10758 |
ins_encode %{
|
|
10759 |
union {
|
|
10760 |
int Isrc32; |
|
10761 |
float Fsrc32; |
|
10762 |
}; |
|
10763 |
Fsrc32 = $src$$constant; |
|
10764 |
__ z_llilf($dst$$Register, Isrc32); |
|
10765 |
__ z_iihf($dst$$Register, Isrc32); |
|
10766 |
%} |
|
10767 |
ins_pipe(pipe_class_dummy); |
|
10768 |
%} |
|
10769 |
||
10770 |
// Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes). |
|
10771 |
// Do this only for 'real' zeroes, especially don't loose sign of negative zeroes. |
|
10772 |
instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
|
|
10773 |
match(Set dst (ReplicateF src)); |
|
10774 |
predicate(n->as_Vector()->length() == 2); |
|
10775 |
ins_should_rematerialize(true); |
|
10776 |
format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %}
|
|
10777 |
ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
|
|
10778 |
ins_pipe(pipe_class_dummy); |
|
10779 |
%} |
|
10780 |
||
10781 |
// Store |
|
10782 |
||
10783 |
// Store Aligned Packed Byte register to memory (8 Bytes). |
|
10784 |
instruct storeA8B(memory mem, iRegL src) %{
|
|
10785 |
match(Set mem (StoreVector mem src)); |
|
10786 |
predicate(n->as_StoreVector()->memory_size() == 8); |
|
10787 |
ins_cost(MEMORY_REF_COST); |
|
10788 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
10789 |
format %{ "STG $src,$mem\t # ST(packed8B)" %}
|
|
10790 |
opcode(STG_ZOPC, STG_ZOPC); |
|
10791 |
ins_encode(z_form_rt_mem_opt(src, mem)); |
|
10792 |
ins_pipe(pipe_class_dummy); |
|
10793 |
%} |
|
10794 |
||
10795 |
// Load |
|
10796 |
||
10797 |
instruct loadV8(iRegL dst, memory mem) %{
|
|
10798 |
match(Set dst (LoadVector mem)); |
|
10799 |
predicate(n->as_LoadVector()->memory_size() == 8); |
|
10800 |
ins_cost(MEMORY_REF_COST); |
|
10801 |
// TODO: s390 port size(VARIABLE_SIZE); |
|
10802 |
format %{ "LG $dst,$mem\t # L(packed8B)" %}
|
|
10803 |
opcode(LG_ZOPC, LG_ZOPC); |
|
10804 |
ins_encode(z_form_rt_mem_opt(dst, mem)); |
|
10805 |
ins_pipe(pipe_class_dummy); |
|
10806 |
%} |
|
10807 |
||
10808 |
//----------POPULATION COUNT RULES-------------------------------------------- |
|
10809 |
||
10810 |
// Byte reverse |
|
10811 |
||
10812 |
instruct bytes_reverse_int(iRegI dst, iRegI src) %{
|
|
10813 |
match(Set dst (ReverseBytesI src)); |
|
10814 |
predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported |
|
10815 |
ins_cost(DEFAULT_COST); |
|
10816 |
size(4); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10817 |
format %{ "LRVR $dst,$src\t # byte reverse int" %}
|
| 42065 | 10818 |
opcode(LRVR_ZOPC); |
10819 |
ins_encode(z_rreform(dst, src)); |
|
10820 |
ins_pipe(pipe_class_dummy); |
|
10821 |
%} |
|
10822 |
||
10823 |
instruct bytes_reverse_long(iRegL dst, iRegL src) %{
|
|
10824 |
match(Set dst (ReverseBytesL src)); |
|
10825 |
predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported |
|
10826 |
ins_cost(DEFAULT_COST); |
|
10827 |
// TODO: s390 port size(FIXED_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10828 |
format %{ "LRVGR $dst,$src\t # byte reverse long" %}
|
| 42065 | 10829 |
opcode(LRVGR_ZOPC); |
10830 |
ins_encode(z_rreform(dst, src)); |
|
10831 |
ins_pipe(pipe_class_dummy); |
|
10832 |
%} |
|
10833 |
||
10834 |
// Leading zeroes |
|
10835 |
||
10836 |
// The instruction FLOGR (Find Leftmost One in Grande (64bit) Register) |
|
10837 |
// returns the bit position of the leftmost 1 in the 64bit source register. |
|
10838 |
// As the bits are numbered from left to right (0..63), the returned |
|
10839 |
// position index is equivalent to the number of leading zeroes. |
|
10840 |
// If no 1-bit is found (i.e. the regsiter contains zero), the instruction |
|
10841 |
// returns position 64. That's exactly what we need. |
|
10842 |
||
10843 |
instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
|
|
10844 |
match(Set dst (CountLeadingZerosI src)); |
|
10845 |
effect(KILL tmp, KILL cr); |
|
10846 |
ins_cost(3 * DEFAULT_COST); |
|
10847 |
size(14); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10848 |
format %{ "SLLG $dst,$src,32\t # no need to always count 32 zeroes first\n\t"
|
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10849 |
"IILH $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t" |
| 42065 | 10850 |
"FLOGR $dst,$dst" |
10851 |
%} |
|
10852 |
ins_encode %{
|
|
10853 |
// Performance experiments indicate that "FLOGR" is using some kind of |
|
10854 |
// iteration to find the leftmost "1" bit. |
|
10855 |
// |
|
10856 |
// The prior implementation zero-extended the 32-bit argument to 64 bit, |
|
10857 |
// thus forcing "FLOGR" to count 32 bits of which we know they are zero. |
|
10858 |
// We could gain measurable speedup in micro benchmark: |
|
10859 |
// |
|
10860 |
// leading trailing |
|
10861 |
// z10: int 2.04 1.68 |
|
10862 |
// long 1.00 1.02 |
|
10863 |
// z196: int 0.99 1.23 |
|
10864 |
// long 1.00 1.11 |
|
10865 |
// |
|
10866 |
// By shifting the argument into the high-word instead of zero-extending it. |
|
10867 |
// The add'l branch on condition (taken for a zero argument, very infrequent, |
|
10868 |
// good prediction) is well compensated for by the savings. |
|
10869 |
// |
|
10870 |
// We leave the previous implementation in for some time in the future when |
|
10871 |
// the "FLOGR" instruction may become less iterative. |
|
10872 |
||
10873 |
// Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original |
|
10874 |
__ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first. |
|
10875 |
__ z_iilh($dst$$Register, 0x8000); // Insert "stop bit" to force result 32 for zero src. |
|
10876 |
__ z_flogr($dst$$Register, $dst$$Register); |
|
10877 |
%} |
|
10878 |
ins_pipe(pipe_class_dummy); |
|
10879 |
%} |
|
10880 |
||
10881 |
instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
|
|
10882 |
match(Set dst (CountLeadingZerosL src)); |
|
10883 |
effect(KILL tmp, KILL cr); |
|
10884 |
ins_cost(DEFAULT_COST); |
|
10885 |
size(4); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10886 |
format %{ "FLOGR $dst,$src \t # count leading zeros (long)\n\t" %}
|
| 42065 | 10887 |
ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
|
10888 |
ins_pipe(pipe_class_dummy); |
|
10889 |
%} |
|
10890 |
||
10891 |
// trailing zeroes |
|
10892 |
||
10893 |
// We transform the trailing zeroes problem to a leading zeroes problem |
|
10894 |
// such that can use the FLOGR instruction to our advantage. |
|
10895 |
||
10896 |
// With |
|
10897 |
// tmp1 = src - 1 |
|
10898 |
// we flip all trailing zeroes to ones and the rightmost one to zero. |
|
10899 |
// All other bits remain unchanged. |
|
10900 |
// With the complement |
|
10901 |
// tmp2 = ~src |
|
10902 |
// we get all ones in the trailing zeroes positions. Thus, |
|
10903 |
// tmp3 = tmp1 & tmp2 |
|
10904 |
// yields ones in the trailing zeroes positions and zeroes elsewhere. |
|
10905 |
// Now we can apply FLOGR and get 64-(trailing zeroes). |
|
10906 |
instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
|
|
10907 |
match(Set dst (CountTrailingZerosI src)); |
|
10908 |
effect(TEMP_DEF dst, TEMP tmp, KILL cr); |
|
10909 |
ins_cost(8 * DEFAULT_COST); |
|
10910 |
// TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10911 |
format %{ "LLGFR $dst,$src \t # clear upper 32 bits (we are dealing with int)\n\t"
|
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10912 |
"LCGFR $tmp,$src \t # load 2's complement (32->64 bit)\n\t" |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10913 |
"AGHI $dst,-1 \t # tmp1 = src-1\n\t" |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10914 |
"AGHI $tmp,-1 \t # tmp2 = -src-1 = ~src\n\t" |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10915 |
"NGR $dst,$tmp \t # tmp3 = tmp1&tmp2\n\t" |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10916 |
"FLOGR $dst,$dst \t # count trailing zeros (int)\n\t" |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10917 |
"AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t" |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10918 |
"LCR $dst,$dst \t # res = -tmp4" |
| 42065 | 10919 |
%} |
10920 |
ins_encode %{
|
|
10921 |
Register Rdst = $dst$$Register; |
|
10922 |
Register Rsrc = $src$$Register; |
|
10923 |
// Rtmp only needed for for zero-argument shortcut. With kill effect in |
|
10924 |
// match rule Rsrc = roddReg would be possible, saving one register. |
|
10925 |
Register Rtmp = $tmp$$Register; |
|
10926 |
||
10927 |
assert_different_registers(Rdst, Rsrc, Rtmp); |
|
10928 |
||
10929 |
// Algorithm: |
|
10930 |
// - Isolate the least significant (rightmost) set bit using (src & (-src)). |
|
10931 |
// All other bits in the result are zero. |
|
10932 |
// - Find the "leftmost one" bit position in the single-bit result from previous step. |
|
10933 |
// - 63-("leftmost one" bit position) gives the # of trailing zeros.
|
|
10934 |
||
10935 |
// Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original. |
|
10936 |
Label done; |
|
10937 |
__ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32. |
|
10938 |
__ z_lcgfr(Rtmp, Rsrc); |
|
10939 |
__ z_bre(done); // Taken very infrequently, good prediction, no BHT entry. |
|
10940 |
||
10941 |
__ z_nr(Rtmp, Rsrc); // (src) & (-src) leaves nothing but least significant bit. |
|
10942 |
__ z_ahi(Rtmp, -1); // Subtract one to fill all trailing zero positions with ones. |
|
10943 |
// Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000) |
|
10944 |
// into upper half of reg. Not relevant with sllg below. |
|
10945 |
__ z_sllg(Rdst, Rtmp, 32); // Shift interesting contents to upper half of register. |
|
10946 |
__ z_bre(done); // Shortcut for argument = 1, result will be 0. |
|
10947 |
// Depends on CC set by ahi above. |
|
10948 |
// Taken very infrequently, good prediction, no BHT entry. |
|
10949 |
// Branch delayed to have Rdst set correctly (Rtmp == 0(32bit) |
|
10950 |
// after SLLG Rdst == 0(64bit)). |
|
10951 |
__ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst. |
|
10952 |
__ add2reg(Rdst, -32); // 32-pos(leftmost1) is #trailing zeros |
|
10953 |
__ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost. |
|
10954 |
__ bind(done); |
|
10955 |
%} |
|
10956 |
ins_pipe(pipe_class_dummy); |
|
10957 |
%} |
|
10958 |
||
10959 |
instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
|
|
10960 |
match(Set dst (CountTrailingZerosL src)); |
|
10961 |
effect(TEMP_DEF dst, KILL tmp, KILL cr); |
|
10962 |
ins_cost(8 * DEFAULT_COST); |
|
10963 |
// TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10964 |
format %{ "LCGR $dst,$src \t # preserve src\n\t"
|
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10965 |
"NGR $dst,$src \t #\n\t" |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10966 |
"AGHI $dst,-1 \t # tmp1 = src-1\n\t" |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10967 |
"FLOGR $dst,$dst \t # count trailing zeros (long), kill $tmp\n\t" |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10968 |
"AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t" |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10969 |
"LCR $dst,$dst \t #" |
| 42065 | 10970 |
%} |
10971 |
ins_encode %{
|
|
10972 |
Register Rdst = $dst$$Register; |
|
10973 |
Register Rsrc = $src$$Register; |
|
10974 |
assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed. |
|
10975 |
||
10976 |
// New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original. |
|
10977 |
__ z_lcgr(Rdst, Rsrc); |
|
10978 |
__ z_ngr(Rdst, Rsrc); |
|
10979 |
__ add2reg(Rdst, -1); |
|
10980 |
__ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst. |
|
10981 |
__ add2reg(Rdst, -64); |
|
10982 |
__ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost. |
|
10983 |
%} |
|
10984 |
ins_pipe(pipe_class_dummy); |
|
10985 |
%} |
|
10986 |
||
10987 |
||
10988 |
// bit count |
|
10989 |
||
10990 |
instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
|
|
10991 |
match(Set dst (PopCountI src)); |
|
10992 |
effect(TEMP_DEF dst, TEMP tmp, KILL cr); |
|
10993 |
predicate(UsePopCountInstruction && VM_Version::has_PopCount()); |
|
10994 |
ins_cost(DEFAULT_COST); |
|
10995 |
size(24); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
10996 |
format %{ "POPCNT $dst,$src\t # pop count int" %}
|
| 42065 | 10997 |
ins_encode %{
|
10998 |
Register Rdst = $dst$$Register; |
|
10999 |
Register Rsrc = $src$$Register; |
|
11000 |
Register Rtmp = $tmp$$Register; |
|
11001 |
||
11002 |
// Prefer compile-time assertion over run-time SIGILL. |
|
11003 |
assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI"); |
|
11004 |
assert_different_registers(Rdst, Rtmp); |
|
11005 |
||
11006 |
// Version 2: shows 10%(z196) improvement over original. |
|
11007 |
__ z_popcnt(Rdst, Rsrc); |
|
11008 |
__ z_srlg(Rtmp, Rdst, 16); // calc byte4+byte6 and byte5+byte7 |
|
11009 |
__ z_alr(Rdst, Rtmp); // into byte6 and byte7 |
|
11010 |
__ z_srlg(Rtmp, Rdst, 8); // calc (byte4+byte6) + (byte5+byte7) |
|
11011 |
__ z_alr(Rdst, Rtmp); // into byte7 |
|
11012 |
__ z_llgcr(Rdst, Rdst); // zero-extend sum |
|
11013 |
%} |
|
11014 |
ins_pipe(pipe_class_dummy); |
|
11015 |
%} |
|
11016 |
||
11017 |
instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
|
|
11018 |
match(Set dst (PopCountL src)); |
|
11019 |
effect(TEMP_DEF dst, TEMP tmp, KILL cr); |
|
11020 |
predicate(UsePopCountInstruction && VM_Version::has_PopCount()); |
|
11021 |
ins_cost(DEFAULT_COST); |
|
11022 |
// TODO: s390 port size(FIXED_SIZE); |
|
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54780
diff
changeset
|
11023 |
format %{ "POPCNT $dst,$src\t # pop count long" %}
|
| 42065 | 11024 |
ins_encode %{
|
11025 |
Register Rdst = $dst$$Register; |
|
11026 |
Register Rsrc = $src$$Register; |
|
11027 |
Register Rtmp = $tmp$$Register; |
|
11028 |
||
11029 |
// Prefer compile-time assertion over run-time SIGILL. |
|
11030 |
assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI"); |
|
11031 |
assert_different_registers(Rdst, Rtmp); |
|
11032 |
||
11033 |
// Original version. Using LA instead of algr seems to be a really bad idea (-35%). |
|
11034 |
__ z_popcnt(Rdst, Rsrc); |
|
11035 |
__ z_ahhlr(Rdst, Rdst, Rdst); |
|
11036 |
__ z_sllg(Rtmp, Rdst, 16); |
|
11037 |
__ z_algr(Rdst, Rtmp); |
|
11038 |
__ z_sllg(Rtmp, Rdst, 8); |
|
11039 |
__ z_algr(Rdst, Rtmp); |
|
11040 |
__ z_srlg(Rdst, Rdst, 56); |
|
11041 |
%} |
|
11042 |
ins_pipe(pipe_class_dummy); |
|
11043 |
%} |
|
11044 |
||
11045 |
//----------SMARTSPILL RULES--------------------------------------------------- |
|
11046 |
// These must follow all instruction definitions as they use the names |
|
11047 |
// defined in the instructions definitions. |
|
11048 |
||
11049 |
// ============================================================================ |
|
11050 |
// TYPE PROFILING RULES |