/*

 * Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved.

 * Copyright (c) 2016, 2019, SAP SE. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "asm/macroAssembler.inline.hpp"

#include "c1/c1_Compilation.hpp"

#include "c1/c1_LIRAssembler.hpp"

#include "c1/c1_MacroAssembler.hpp"

#include "c1/c1_Runtime1.hpp"

#include "c1/c1_ValueStack.hpp"

#include "ci/ciArrayKlass.hpp"

#include "ci/ciInstance.hpp"

#include "gc/shared/collectedHeap.hpp"

#include "gc/shared/barrierSet.hpp"

#include "gc/shared/cardTableBarrierSet.hpp"

#include "memory/universe.hpp"

#include "nativeInst_s390.hpp"

#include "oops/objArrayKlass.hpp"

#include "runtime/frame.inline.hpp"

#include "runtime/safepointMechanism.inline.hpp"

#include "runtime/sharedRuntime.hpp"

#include "vmreg_s390.inline.hpp"

#define __ _masm->

#ifndef PRODUCT

#undef __

#define __ (Verbose ? (_masm->block_comment(FILE_AND_LINE),_masm) : _masm)->

#endif

//------------------------------------------------------------

bool LIR_Assembler::is_small_constant(LIR_Opr opr) {

  // Not used on ZARCH_64

  ShouldNotCallThis();

  return false;

}

LIR_Opr LIR_Assembler::receiverOpr() {

  return FrameMap::Z_R2_oop_opr;

}

LIR_Opr LIR_Assembler::osrBufferPointer() {

  return FrameMap::Z_R2_opr;

}

int LIR_Assembler::initial_frame_size_in_bytes() const {

  return in_bytes(frame_map()->framesize_in_bytes());

}

// Inline cache check: done before the frame is built.

// The inline cached class is in Z_inline_cache(Z_R9).

// We fetch the class of the receiver and compare it with the cached class.

// If they do not match we jump to the slow case.

int LIR_Assembler::check_icache() {

  Register receiver = receiverOpr()->as_register();

  int offset = __ offset();

  __ inline_cache_check(receiver, Z_inline_cache);

  return offset;

}

void LIR_Assembler::clinit_barrier(ciMethod* method) {

  assert(!method->holder()->is_not_initialized(), "initialization should have been started");

  Label L_skip_barrier;

  Register klass = Z_R1_scratch;

  metadata2reg(method->holder()->constant_encoding(), klass);

  __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);

  __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());

  __ z_br(klass);

  __ bind(L_skip_barrier);

}

void LIR_Assembler::osr_entry() {

  // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):

  //

  //   1. Create a new compiled activation.

  //   2. Initialize local variables in the compiled activation. The expression stack must be empty

  //      at the osr_bci; it is not initialized.

  //   3. Jump to the continuation address in compiled code to resume execution.

  // OSR entry point

  offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());

  BlockBegin* osr_entry = compilation()->hir()->osr_entry();

  ValueStack* entry_state = osr_entry->end()->state();

  int number_of_locks = entry_state->locks_size();

  // Create a frame for the compiled activation.

  __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());

  // OSR buffer is

  //

  // locals[nlocals-1..0]

  // monitors[number_of_locks-1..0]

  //

  // Locals is a direct copy of the interpreter frame so in the osr buffer

  // the first slot in the local array is the last local from the interpreter

  // and the last slot is local[0] (receiver) from the interpreter

  //

  // Similarly with locks. The first lock slot in the osr buffer is the nth lock

  // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock

  // in the interpreter frame (the method lock if a sync method)

  // Initialize monitors in the compiled activation.

  //   I0: pointer to osr buffer

  //

  // All other registers are dead at this point and the locals will be

  // copied into place by code emitted in the IR.

  Register OSR_buf = osrBufferPointer()->as_register();

  { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");

    int monitor_offset = BytesPerWord * method()->max_locals() +

      (2 * BytesPerWord) * (number_of_locks - 1);

    // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in

    // the OSR buffer using 2 word entries: first the lock and then

    // the oop.

    for (int i = 0; i < number_of_locks; i++) {

      int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);

      // Verify the interpreter's monitor has a non-null object.

      __ asm_assert_mem8_isnot_zero(slot_offset + 1*BytesPerWord, OSR_buf, "locked object is NULL", __LINE__);

      // Copy the lock field into the compiled activation.

      __ z_lg(Z_R1_scratch, slot_offset + 0, OSR_buf);

      __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_lock(i));

      __ z_lg(Z_R1_scratch, slot_offset + 1*BytesPerWord, OSR_buf);

      __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_object(i));

    }

  }

}

// --------------------------------------------------------------------------------------------

address LIR_Assembler::emit_call_c(address a) {

  __ align_call_far_patchable(__ pc());

  address call_addr = __ call_c_opt(a);

  if (call_addr == NULL) {

    bailout("const section overflow");

  }

  return call_addr;

}

int LIR_Assembler::emit_exception_handler() {

  // If the last instruction is a call (typically to do a throw which

  // is coming at the end after block reordering) the return address

  // must still point into the code area in order to avoid assertion

  // failures when searching for the corresponding bci. => Add a nop.

  // (was bug 5/14/1999 - gri)

  __ nop();

  // Generate code for exception handler.

  address handler_base = __ start_a_stub(exception_handler_size());

  if (handler_base == NULL) {

    // Not enough space left for the handler.

    bailout("exception handler overflow");

    return -1;

  }

  int offset = code_offset();

  address a = Runtime1::entry_for (Runtime1::handle_exception_from_callee_id);

  address call_addr = emit_call_c(a);

  CHECK_BAILOUT_(-1);

  __ should_not_reach_here();

  guarantee(code_offset() - offset <= exception_handler_size(), "overflow");

  __ end_a_stub();

  return offset;

}

// Emit the code to remove the frame from the stack in the exception

// unwind path.

int LIR_Assembler::emit_unwind_handler() {

#ifndef PRODUCT

  if (CommentedAssembly) {

    _masm->block_comment("Unwind handler");

  }

#endif

  int offset = code_offset();

  Register exception_oop_callee_saved = Z_R10; // Z_R10 is callee-saved.

  Register Rtmp1                      = Z_R11;

  Register Rtmp2                      = Z_R12;

  // Fetch the exception from TLS and clear out exception related thread state.

  Address exc_oop_addr = Address(Z_thread, JavaThread::exception_oop_offset());

  Address exc_pc_addr  = Address(Z_thread, JavaThread::exception_pc_offset());

  __ z_lg(Z_EXC_OOP, exc_oop_addr);

  __ clear_mem(exc_oop_addr, sizeof(oop));

  __ clear_mem(exc_pc_addr, sizeof(intptr_t));

  __ bind(_unwind_handler_entry);

  __ verify_not_null_oop(Z_EXC_OOP);

  if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {

    __ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception.

  }

  // Preform needed unlocking.

  MonitorExitStub* stub = NULL;

  if (method()->is_synchronized()) {

    // Runtime1::monitorexit_id expects lock address in Z_R1_scratch.

    LIR_Opr lock = FrameMap::as_opr(Z_R1_scratch);

    monitor_address(0, lock);

    stub = new MonitorExitStub(lock, true, 0);

    __ unlock_object(Rtmp1, Rtmp2, lock->as_register(), *stub->entry());

    __ bind(*stub->continuation());

  }

  if (compilation()->env()->dtrace_method_probes()) {

    ShouldNotReachHere(); // Not supported.

#if 0

    __ mov(rdi, r15_thread);

    __ mov_metadata(rsi, method()->constant_encoding());

    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));

#endif

  }

  if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {

    __ lgr_if_needed(Z_EXC_OOP, exception_oop_callee_saved);  // Restore the exception.

  }

  // Remove the activation and dispatch to the unwind handler.

  __ pop_frame();

  __ z_lg(Z_EXC_PC, _z_abi16(return_pc), Z_SP);

  // Z_EXC_OOP: exception oop

  // Z_EXC_PC: exception pc

  // Dispatch to the unwind logic.

  __ load_const_optimized(Z_R5, Runtime1::entry_for (Runtime1::unwind_exception_id));

  __ z_br(Z_R5);

  // Emit the slow path assembly.

  if (stub != NULL) {

    stub->emit_code(this);

  }

  return offset;

}

int LIR_Assembler::emit_deopt_handler() {

  // If the last instruction is a call (typically to do a throw which

  // is coming at the end after block reordering) the return address

  // must still point into the code area in order to avoid assertion

  // failures when searching for the corresponding bci. => Add a nop.

  // (was bug 5/14/1999 - gri)

  __ nop();

  // Generate code for exception handler.

  address handler_base = __ start_a_stub(deopt_handler_size());

  if (handler_base == NULL) {

    // Not enough space left for the handler.

    bailout("deopt handler overflow");

    return -1;

  }  int offset = code_offset();

  // Size must be constant (see HandlerImpl::emit_deopt_handler).

  __ load_const(Z_R1_scratch, SharedRuntime::deopt_blob()->unpack());

  __ call(Z_R1_scratch);

  guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");

  __ end_a_stub();

  return offset;

}

void LIR_Assembler::jobject2reg(jobject o, Register reg) {

  if (o == NULL) {

    __ clear_reg(reg, true/*64bit*/, false/*set cc*/); // Must not kill cc set by cmove.

  } else {

    AddressLiteral a = __ allocate_oop_address(o);

    bool success = __ load_oop_from_toc(reg, a, reg);

    if (!success) {

      bailout("const section overflow");

    }

  }

}

void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {

  // Allocate a new index in table to hold the object once it's been patched.

  int oop_index = __ oop_recorder()->allocate_oop_index(NULL);

  PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);

  AddressLiteral addrlit((intptr_t)0, oop_Relocation::spec(oop_index));

  assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");

  // The NULL will be dynamically patched later so the sequence to

  // load the address literal must not be optimized.

  __ load_const(reg, addrlit);

  patching_epilog(patch, lir_patch_normal, reg, info);

}

void LIR_Assembler::metadata2reg(Metadata* md, Register reg) {

  bool success = __ set_metadata_constant(md, reg);

  if (!success) {

    bailout("const section overflow");

    return;

  }

}

void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {

  // Allocate a new index in table to hold the klass once it's been patched.

  int index = __ oop_recorder()->allocate_metadata_index(NULL);

  PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);

  AddressLiteral addrlit((intptr_t)0, metadata_Relocation::spec(index));

  assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");

  // The NULL will be dynamically patched later so the sequence to

  // load the address literal must not be optimized.

  __ load_const(reg, addrlit);

  patching_epilog(patch, lir_patch_normal, reg, info);

}

void LIR_Assembler::emit_op3(LIR_Op3* op) {

  switch (op->code()) {

    case lir_idiv:

    case lir_irem:

      arithmetic_idiv(op->code(),

                      op->in_opr1(),

                      op->in_opr2(),

                      op->in_opr3(),

                      op->result_opr(),

                      op->info());

      break;

    case lir_fmad: {

      const FloatRegister opr1 = op->in_opr1()->as_double_reg(),

                          opr2 = op->in_opr2()->as_double_reg(),

                          opr3 = op->in_opr3()->as_double_reg(),

                          res  = op->result_opr()->as_double_reg();

      __ z_madbr(opr3, opr1, opr2);

      if (res != opr3) { __ z_ldr(res, opr3); }

    } break;

    case lir_fmaf: {

      const FloatRegister opr1 = op->in_opr1()->as_float_reg(),

                          opr2 = op->in_opr2()->as_float_reg(),

                          opr3 = op->in_opr3()->as_float_reg(),

                          res  = op->result_opr()->as_float_reg();

      __ z_maebr(opr3, opr1, opr2);

      if (res != opr3) { __ z_ler(res, opr3); }

    } break;

    default: ShouldNotReachHere(); break;

  }

}

void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {

#ifdef ASSERT

  assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");

  if (op->block() != NULL)  { _branch_target_blocks.append(op->block()); }

  if (op->ublock() != NULL) { _branch_target_blocks.append(op->ublock()); }

#endif

  if (op->cond() == lir_cond_always) {

    if (op->info() != NULL) { add_debug_info_for_branch(op->info()); }

    __ branch_optimized(Assembler::bcondAlways, *(op->label()));

  } else {

    Assembler::branch_condition acond = Assembler::bcondZero;

    if (op->code() == lir_cond_float_branch) {

      assert(op->ublock() != NULL, "must have unordered successor");

      __ branch_optimized(Assembler::bcondNotOrdered, *(op->ublock()->label()));

    }

    switch (op->cond()) {

      case lir_cond_equal:        acond = Assembler::bcondEqual;     break;

      case lir_cond_notEqual:     acond = Assembler::bcondNotEqual;  break;

      case lir_cond_less:         acond = Assembler::bcondLow;       break;

      case lir_cond_lessEqual:    acond = Assembler::bcondNotHigh;   break;

      case lir_cond_greaterEqual: acond = Assembler::bcondNotLow;    break;

      case lir_cond_greater:      acond = Assembler::bcondHigh;      break;

      case lir_cond_belowEqual:   acond = Assembler::bcondNotHigh;   break;

      case lir_cond_aboveEqual:   acond = Assembler::bcondNotLow;    break;

      default:                         ShouldNotReachHere();

    }

    __ branch_optimized(acond,*(op->label()));

  }

}

void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {

  LIR_Opr src  = op->in_opr();

  LIR_Opr dest = op->result_opr();

  switch (op->bytecode()) {

    case Bytecodes::_i2l:

      __ move_reg_if_needed(dest->as_register_lo(), T_LONG, src->as_register(), T_INT);

      break;

    case Bytecodes::_l2i:

      __ move_reg_if_needed(dest->as_register(), T_INT, src->as_register_lo(), T_LONG);

      break;

    case Bytecodes::_i2b:

      __ move_reg_if_needed(dest->as_register(), T_BYTE, src->as_register(), T_INT);

      break;

    case Bytecodes::_i2c:

      __ move_reg_if_needed(dest->as_register(), T_CHAR, src->as_register(), T_INT);

      break;

    case Bytecodes::_i2s:

      __ move_reg_if_needed(dest->as_register(), T_SHORT, src->as_register(), T_INT);

      break;

    case Bytecodes::_f2d:

      assert(dest->is_double_fpu(), "check");

      __ move_freg_if_needed(dest->as_double_reg(), T_DOUBLE, src->as_float_reg(), T_FLOAT);

      break;

    case Bytecodes::_d2f:

      assert(dest->is_single_fpu(), "check");

      __ move_freg_if_needed(dest->as_float_reg(), T_FLOAT, src->as_double_reg(), T_DOUBLE);

      break;

    case Bytecodes::_i2f:

      __ z_cefbr(dest->as_float_reg(), src->as_register());

      break;

    case Bytecodes::_i2d:

      __ z_cdfbr(dest->as_double_reg(), src->as_register());

      break;

    case Bytecodes::_l2f:

      __ z_cegbr(dest->as_float_reg(), src->as_register_lo());

      break;

    case Bytecodes::_l2d:

      __ z_cdgbr(dest->as_double_reg(), src->as_register_lo());

      break;

    case Bytecodes::_f2i:

    case Bytecodes::_f2l: {

      Label done;

      FloatRegister Rsrc = src->as_float_reg();

      Register Rdst = (op->bytecode() == Bytecodes::_f2i ? dest->as_register() : dest->as_register_lo());

      __ clear_reg(Rdst, true, false);

      __ z_cebr(Rsrc, Rsrc);

      __ z_brno(done); // NaN -> 0

      if (op->bytecode() == Bytecodes::_f2i) {

        __ z_cfebr(Rdst, Rsrc, Assembler::to_zero);

      } else { // op->bytecode() == Bytecodes::_f2l

        __ z_cgebr(Rdst, Rsrc, Assembler::to_zero);

      }

      __ bind(done);

    }

    break;

    case Bytecodes::_d2i:

    case Bytecodes::_d2l: {

      Label done;

      FloatRegister Rsrc = src->as_double_reg();

      Register Rdst = (op->bytecode() == Bytecodes::_d2i ? dest->as_register() : dest->as_register_lo());

      __ clear_reg(Rdst, true, false);  // Don't set CC.

      __ z_cdbr(Rsrc, Rsrc);

      __ z_brno(done); // NaN -> 0

      if (op->bytecode() == Bytecodes::_d2i) {

        __ z_cfdbr(Rdst, Rsrc, Assembler::to_zero);

      } else { // Bytecodes::_d2l

        __ z_cgdbr(Rdst, Rsrc, Assembler::to_zero);

      }

      __ bind(done);

    }

    break;

    default: ShouldNotReachHere();

  }

}

void LIR_Assembler::align_call(LIR_Code code) {

  // End of call instruction must be 4 byte aligned.

  int offset = __ offset();

  switch (code) {

    case lir_icvirtual_call:

      offset += MacroAssembler::load_const_from_toc_size();

      // no break

    case lir_static_call:

    case lir_optvirtual_call:

    case lir_dynamic_call:

      offset += NativeCall::call_far_pcrelative_displacement_offset;

      break;

    case lir_virtual_call:   // currently, sparc-specific for niagara

    default: ShouldNotReachHere();

  }

  if ((offset & (NativeCall::call_far_pcrelative_displacement_alignment-1)) != 0) {

    __ nop();

  }

}

void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {

  assert((__ offset() + NativeCall::call_far_pcrelative_displacement_offset) % NativeCall::call_far_pcrelative_displacement_alignment == 0,

         "must be aligned (offset=%d)", __ offset());

  assert(rtype == relocInfo::none ||

         rtype == relocInfo::opt_virtual_call_type ||

         rtype == relocInfo::static_call_type, "unexpected rtype");

  // Prepend each BRASL with a nop.

  __ relocate(rtype);

  __ z_nop();

  __ z_brasl(Z_R14, op->addr());

  add_call_info(code_offset(), op->info());

}

void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {

  address virtual_call_oop_addr = NULL;

  AddressLiteral empty_ic((address) Universe::non_oop_word());

  virtual_call_oop_addr = __ pc();

  bool success = __ load_const_from_toc(Z_inline_cache, empty_ic);